TCP-3182H
8.2 pF Passive Tunable
Integrated Circuits (PTIC)
Introduction
ON Semiconductor’s PTICs have excellent RF performance and
power consumption, making them suitable for any mobile handset or
radio application. The fundamental building block of our PTIC
product line is a tunable material called ParaScant, based on Barium
Strontium Titanate (BST). PTICs have the ability to change their
capacitance from a supplied bias voltage generated by the Control IC.
The 8.2 pF PTICs are available as wafer-level chip scale packages
(WLCSP).
http://onsemi.com
WLCSP12
1.13x0.65
CASE 567KG
Key Features
•
•
•
•
•
•
•
High Tuning Range and Operation up to 20 V
Usable Frequency Range: from 700 MHz to 2.7 GHz
High Quality Factor (Q) for Low Loss
High Power Handling Capability
Compatible with PTIC Control IC TCC-10x, 20x
WLCSP Package: 0.652 x 1.134 x 0.285 mm (12 bump)
These devices are Pb−Free and RoHS Compliant
MARKING DIAGRAM
Typical Applications
•
•
•
•
Multi-band, Multi-standard, Advanced and Simple Mobile Phones
Tunable Antenna Matching Networks
Tunable RF Filters
Active Antennas
FUNCTIONAL BLOCK DIAGRAM
PTIC
RF1
RF2
Bias
PTIC Functional Block Diagram
ORDERING INFORMATION
Device
TCP−3182H−DT
Package
Shipping†
WLCSP12
(Pb−Free)
4000 Units /
7” Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 0
1
Publication Order Number:
TCP−3182H/D
TCP−3182H
TYPICAL SPECIFICATIONS
Representative Performance Data at 255C
Table 1. PERFORMANCE DATA
Parameter
Min
Operating Bias Voltage
Typ
2.0
Units
20
V
Capacitance (Vbias = 2 V)
7.38
8.20
9.02
pF
Capacitance (Vbias = 20 V)
1.886
2.050
2.214
pF
Tuning Range (2 V - 20 V)
3.60
4.00
4.50
Leakage Current (WLCSP)
Operating Frequency
700
Quality Factor @ 700 MHz, 10 V
100
Quality Factor @ 2.4 GHz, 10 V
70
IP3 (Vbias = 2 V)
[1,3]
IP3 (Vbias = 20 V) [1,3]
2nd Harmonic (Vbias = 2 V) [2,3]
2nd Harmonic (Vbias = 20 V)
3rd Harmonic (Vbias = 2 V)
[2,3]
[2,3]
3rd Harmonic (Vbias = 20 V)
[2,3]
2.0
mA
2700
MHz
70
dBm
85
dBm
-75
dBm
-85
dBm
-40
dBm
-70
dBm
[4]
80
ms
Transition Time (Cmax ³ Cmin) [4]
70
ms
Transition Time (Cmin ³ Cmax)
1.
2.
3.
4.
Max
f1 = 850 MHz, f2 = 860 MHz, Pin 25 dBm/Tone
850 MHz, Pin +34 dBm
IP3 and Harmonics are measured in the shunt configuration in a 50 W environment
RFIN and RFOUT are both connected to DC ground
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2
TCP−3182H
Representative performance data at 255C for 8.2 pF WLCSP Package
Figure 1. Capacitance
Figure 2. Harmonic Power
Figure 3. IP3
Figure 4. Q
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Input Power
+40
dBm
Bias Voltage
+25 (Note 5)
V
−30 to +85
°C
−55 to +125
°C
Operating Temperature Range
Storage Temperature Range
ESD − Human Body Model
Class 1A JEDEC HBM Standard (Note 6)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. WLCSP: Recommended Bias Voltage not to exceed 20 V
6. Class 1A defined as passing 250 V, but may fail after exposure to 500 V ESD pulse
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3
TCP−3182H
ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE
The following assembly considerations should be observed:
Cleanliness
These chips should be handled in a clean environment.
Electro-static Sensitivity
ON Semiconductor’s PTICs are ESD Class 1A sensitive.
The proper ESD handling procedures should be used.
Mounting
The WLCSP PTIC is fabricated for Flip Chip solder
mounting. Connectivity to the RF and Bias terminations on
the PTIC die is established through SAC305 solder balls
with 65 mm nominal height (45 mm to 85 mm height
variation). The PTIC die is RoHS-compliant and compatible
with lead-free soldering profile.
Molding
The PTIC die is compatible for over-molding or
under-fill.
Figure 5. Reflow Profile
ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES
RF
When configuring the PTIC in your specific circuit
design, at least one of the RF terminals must be connected
to DC ground. If minimum transition times are required, DC
ground on both RF terminals is recommended. To minimize
losses, the PTIC should be oriented such that RF2 is at the
lower RF impedance of the two RF nodes. A shunt PTIC, for
example, should have RF2 connected to RF ground.
ANT
RF1
(PTIC Pad)
RF2
(PTIC Pad)
Bias
Figure 6. PTIC Orientation Functional Block
Diagram
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4
TCP−3182H
PART NUMBER DEFINITION
Example: TCP−3182H−DT
TCP
-
31
82
H
-
D
T
Product
Family
Process Status
Process
Generation
Capacitor
Value
Tuning
Package /
Format
Packing
TCP
“blank” =
Production
X = Pilot
Production
10 = Gen 1.0
30 = Gen 3.0
31 = Gen 3.1
12 = 1.2 pF
18 = 1.8 pF
27 = 2.7 pF
33 = 3.3 pF
39 = 3.9 pF
47 = 4.7 pF
56 = 5.6 pF
68 = 6.8 pF
82 = 8.2 pF
N = Normal
H = High
D = WLCSP
Q = QFN
T = T&R
-
S=
Special/Custom
P = Prototype
-
Table 3. PART NUMBERS
Capacitance
Part Number
TCP-3182H-DT
2V
20 V
Package*
8.20
2.05
12-bump WLCSP
*See PTIC package dimensions on following page.
http://onsemi.com
5
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