TCP-5082UA-DT

TCP-5082UA High-Linearity 8.2 pF Passive Tunable Integrated Circuits (PTIC) Introduction www.onsemi.com ON Semiconductor’s PTICs have excellent RF performance and power consumption, making them suitable for any mobile handset or radio application. The fundamental building block of our PTIC product line is a tunable material called ParaScant, based on Barium Strontium Titanate (BST). PTICs have the ability to change their capacitance from a supplied bias voltage generated by the Control IC. TCP−5082UA has higher linearity for use in applications which require improved harmonic performance. The 8.2 pF ultra−high tuning, high Q PTICs are available as wafer-level chip scale packages (WLCSP). WLCSP3 0.772x0.940 CASE 567PE MARKING DIAGRAM KYW Key Features • • • • • • Ultra−High Tuning Range (5:1) and Operation up to 24 V Usable Frequency Range: from 700 MHz to 2.7 GHz High Quality Factor (Q) for Low Loss High Power Handling Capability Compatible with PTIC Control ICs from ON Semiconductor These devices are Pb−Free and RoHS Compliant K Y W = Specific Device Code = Year = Work Week FUNCTIONAL BLOCK DIAGRAM PTIC Typical Applications • • • • Multi-band, Multi-standard, Advanced and Simple Mobile Phones Tunable Antenna Matching Networks Tunable RF Filters Active Antennas RF1 RF2 Bias PTIC Functional Block Diagram ORDERING INFORMATION Device TCP−5082UA−DT Package Shipping† WLCSP3 (Pb−Free) 4000 Units / 7” Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 December, 2016 − Rev. 4 1 Publication Order Number: TCP−5082UA/D TCP−5082UA Figure 1. PTIC Functional Block Diagram (Top View) Table 1. SIGNAL DESCRIPTIONS Ball / Pad Number Pin Name A2 DC Bias 1 B3 RF1 RF Input B1 RF2 RF Output www.onsemi.com 2 Description DC Bias Voltage TCP−5082UA TYPICAL SPECIFICATIONS Representative Performance Data at 255C Table 2. PERFORMANCE DATA Parameter Min Operating Bias Voltage Typ 1.0 Units 24 V Capacitance (Vbias = 2 V) 7.462 8.200 8.938 pF Capacitance (Vbias = 24 V) 1.605 1.763 1.922 pF Capacitance Accuracy (Vbias = 2−24 V) 9 % Tuning Range (1 V - 24 V) 4.80 5.25 6.00 Tuning Range (2 V - 24 V) 4.20 4.65 5.30 Leakage Current (Vbias = 24 V) Operating Frequency 700 Quality Factor @ 700 MHz, 2 V [5] 0.1 mA 2700 MHz 65 70 Quality Factor @ 700 MHz, 24 V [5] 70 80 Quality Factor @ 2.4 GHz, 2 V [5] 40 45 50 60 30 35 30 35 68 70 dB 83 85 dB Quality Factor @ 2.4 GHz, 24 V Quality Factor @ 2.7 GHz, 2 V IP3 (Vbias = 2 V) [5] [5] Quality Factor @ 2.7 GHz, 24 V [5] [1,3,5] IP3 (Vbias = 24 V) [1,3,5] 2nd Harmonic (Vbias = 2 V) [2,3,5] 2nd Harmonic (Vbias = 24 V) 3rd Harmonic (Vbias = 2 V) [2,3,5] [2,3,5] 3rd Harmonic (Vbias = 24 V) [2,3,5] -65 −57 dBm -75 −67 dBm -40 −35 dBm -70 −65 dBm [4] 66 72 ms Transition Time (Cmax ³ Cmin) [4] 48 53 ms Transition Time (Cmin ³ Cmax) 1. 2. 3. 4. 5. Max f1 = 850 MHz, f2 = 860 MHz, Pin 25 dBm/Tone 850 MHz, Pin +34 dBm Harmonics are measured in the series configuration in a 50 W environment. IP3 is measured in the shunt configuration in a 50 W environment. RFIN and RFOUT must be connected to DC ground using the PTIC Control IC Turbo Mode. Sample testing only. Average Transition Time for all start and stop voltage combinations between 2 V and 24 V is 50 ms. www.onsemi.com 3 TCP−5082UA Representative performance data at 255C for 8.2 pF WLCSP Package Figure 3. Harmonic Power* Figure 2. Capacitance Figure 4. IP3* Figure 5. Q* *Data shown is representative only. Table 3. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Input Power +40 dBm Bias Voltage +30 (Note 6) V Operating Temperature Range −30 to +85 °C Storage Temperature Range −55 to +125 °C ESD − Human Body Model Class 1B JEDEC HBM Standard (Note 7) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 6. WLCSP: Recommended Bias Voltage not to exceed 24 V. 7. Class 1B defined as passing 500 V, but may fail after exposure to 1000 V ESD pulse. www.onsemi.com 4 TCP−5082UA ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE The following assembly considerations should be observed: Cleanliness These chips should be handled in a clean environment. Electro-static Sensitivity ON Semiconductor’s PTICs are ESD Class 1B sensitive. The proper ESD handling procedures should be used. Mounting The WLCSP PTIC is fabricated for Flip Chip solder mounting. Connectivity to the RF and Bias terminations on the PTIC die is established through SAC305 solder balls with 90 mm nominal height (65 mm to 115 mm height variation). The PTIC die is RoHS-compliant and compatible with lead-free soldering profile. Molding The PTIC die is compatible for over-molding or under-fill. Figure 6. Reflow Profile ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES RF When configuring the PTIC in your specific circuit design, at least one of the RF terminals must be connected to DC ground. If minimum transition times are required, DC ground on both RF terminals is recommended. To minimize losses, the PTIC should be oriented such that RF2 is at the lower RF impedance of the two RF nodes. A shunt PTIC, for example, should have RF2 connected to RF ground. ANT RF1 (PTIC Pad) RF2 (PTIC Pad) Bias Figure 7. PTIC Orientation Functional Block Diagram www.onsemi.com 5 TCP−5082UA PART NUMBER DEFINITION Table 4. PART NUMBERS Capacitance Part Number TCP−5082UA-DT Marking 2V 24 V Device ID Trace Code Package* 8.20 1.763 K YW** 3-bump WLCSP *See PTIC package dimensions on following page. **Refer to table below (Table 5) for YW trace code. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. Table 5. Two Digits Year and Work Week Date coding (YW) − In Process Product / Traceability Date Code Marking Code Term Definition YW Year and Work Week Two−character Alpha Code. Example: 2005, workweek 10 = GJ YEAR WORK WEEK CODE YEAR WORK WEEK CODE YEAR WORK WEEK CODE 2003 1 26 27 52 CA CZ DA DZ 2004 1 26 27 52 EA EZ FA FZ 2005 1 26 27 52 GA GZ HA HZ 2006 1 26 27 52 IA IZ JA JZ 2007 1 26 27 52 KA KZ LA LZ 2008 1 26 27 52 MA MZ NA NZ 2009 1 26 27 52 PA PZ RA RZ 2010 1 26 27 52 SA SZ TA TZ 2011 1 26 27 52 UA UZ VA VZ 2012 1 26 27 52 WA WZ XA XZ 2013 1 26 27 52 YA YZ ZA ZZ 2014 1 26 27 52 AA AZ BA BZ 2015 1 26 27 52 CA CZ DA DZ 2016 1 26 27 52 EA EZ FA FZ 2017 1 26 27 52 GA GZ HA HZ For dates outside of the table: the first character of the code is incremented at the start of workweek 01 and workweek 27 each year. The second character begins with “A” in workweek 01 of each year and increments weekly. “A” follows “Z” to make the code continuous. www.onsemi.com 6 TCP−5082UA PACKAGE DIMENSIONS WLCSP3, 0.94x0.772 CASE 567PE ISSUE B ÈÈ ÈÈ ÈÈ E PIN A1 REFERENCE A B 3X 3X b1 0.10 M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE CONTACTS. 4. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. 5. DIMENSIONS b AND b1 ARE MEASURED AT THE MAXIMUM CONTACT DIAMETER PARALLEL TO DATUM C. POSITIONAL TOLERANCE APPLIES TO ALL THREE CONTACTS IN BOTH THE X AND Y AXIS. 6. BACKSIDE TAPE APPLIED TO IMPROVE PIN 1 MARKING. C A B NOTE 5 b D DETAIL A TOP VIEW NOTE 6 TAPE DETAIL B A3 A2 0.06 C 0.05 C A1 NOTE 4 SIDE VIEW DIM A A1 A2 A3 b b1 D E e e2 e3 C A NOTE 3 SEATING PLANE DETAIL B e MILLIMETERS MIN NOM 0.335 0.295 0.065 0.090 0.260 REF 0.025 REF 0.275 0.300 0.075 0.100 0.890 0.940 0.722 0.772 0.55 BSC 0.35 BSC 0.074 BSC MAX 0.375 0.115 0.325 0.125 0.990 0.822 RECOMMENDED SOLDERING FOOTPRINT* e/2 e3 0.55 A2 e2 PACKAGE OUTLINE B DETAIL A 0.42 A 1 2 3 3X BOTTOM VIEW 0.30 3X 0.10 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ParaScan is a trademark of Paratek Microwave, Inc. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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