ON Semiconductor
TL081C,AC
TL082C,AC
TL084C,AC
JFET Input Operational
Amplifiers
These low–cost JFET input operational amplifiers combine two state–of–
the–art linear technologies on a single monolithic integrated circuit. Each
internally compensated operational amplifier has well matched high voltage
JFET input devices for low input offset voltage. The BIFET technology
provides wide bandwidths and fast slew rates with low input bias currents,
input offset currents, and supply currents.
These devices are available in single, dual and quad operational
amplifiers which are pin–compatible with the industry standard MC1741,
MC1458, and the MC3403/LM324 bipolar products.
• Input Offset Voltage Options of 6.0 mV and 15 mV Max
•
•
•
•
•
•
JFET INPUT
OPERATIONAL AMPLIFIERS
SEMICONDUCTOR
TECHNICAL DATA
8
Low Input Bias Current: 30 pA
1
8
1
Low Input Offset Current: 5.0 pA
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
P SUFFIX
PLASTIC PACKAGE
CASE 626
Wide Gain Bandwidth: 4.0 MHz
High Slew Rate: 13 V/µs
Low Supply Current: 1.4 mA per Amplifier
High Input Impedance: 1012 Ω
PIN CONNECTIONS
ORDERING INFORMATION
Op Amp
Function
Device
Single
TL082CD
Dual
Quad
Plastic DIP
5 Offset Null
Output A 1
SO–8
8
2
Inputs A
Plastic DIP
TA = 0° to +70°C
TL084CN, ACN
6 Output
TL081 (Top View)
SO–8
TA = 0° to +70°C
TL082ACP
+
VEE 4
Package
TA = 0° to +70°C
TL081ACP
8 NC
7 VCC
Noninvt Input 3
Operating
Temperature Range
TL081CD
Offset Null 1
Inv + Input 2
–
+
3
–
+
VEE 4
Plastic DIP
VCC
7 Output B
6
Inputs B
5
TL082 (Top View)
Representative Circuit Schematic (Each Amplifier)
Output
Q4
Q3
J1
Inputs
+
VCC
Q2
Q5
PIN CONNECTIONS
2.0 k
Q17
Q20
Q15
Q14
10 pF
Q19
Q21
Q13
Q10
Offset
Null
(TL081
only)
Q23
Inputs 1
24
Q9
Q8
Q7
Inputs 2
Q25
March, 2002 – Rev. 2
3
–
+
–
1
4
+
5
6
13
12
Inputs 4
11 VEE
+
–
2
3
+
–
Output 2 7
1.5k
Semiconductor Components Industries, LLC, 2002
2
VCC 4
Q22 Q24
Q16
Q11
14 Output 4
Output 1 1
J3
Q18
1.5k
14
1
Q1
Q6
J2
Q12
N SUFFIX
PLASTIC PACKAGE
CASE 646
10
9
Inputs 3
8 Output 3
TL084 (Top View)
Bias Circuitry
Common to All
Amplifiers
1
VEE
Publication Order Number:
TL081C/D
TL081C,AC TL082C,AC TL084C,AC
MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
Rating
VCC
VEE
18
–18
V
Differential Input Voltage
VID
±30
V
Input Voltage Range (Note 1)
VIDR
±15
V
tSC
Continuous
PD
1/θJA
680
10
mW
mW/°C
Operating Ambient Temperature Range
TA
0 to +70
°C
Storage Temperature Range
Tstg
–65 to +150
°C
Output Short Circuit Duration (Note 2)
Power Dissipation
Plastic Package (N, P)
Derate above TA = +47°C
NOTES: 1. The magnitude of the input voltage must not exceed the magnitude of the supply voltage or
15 V, whichever is less.
2. The output may be shorted to ground or either supply. Temperature and/or supply voltages
must be limited to ensure that power dissipation ratings are not exceeded.
3. ESD data available upon request.
ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = –15 V, TA = Tlow to Thigh [Note 1].)
Characteristics
Symbol
Input Offset Voltage (RS ≤ 10 k, VCM = 0)
TL081C, TL082C
TL084C
TL08_AC
VIO
Input Offset Current (VCM = 0) (Note 2)
TL08_C
TL08_AC
IIO
Input Bias Current (VCM = 0) (Note 2)
TL08_C
TL08_AC
IIB
Large–Signal Voltage Gain (VO= ±10 V,RL ≥ 2.0 k)
TL08_C
TL08_AC
Min
Typ
Max
–
–
–
–
–
–
20
20
7.5
–
–
–
–
5.0
3.0
–
–
–
–
10
7.0
15
25
–
–
–
–
24
20
–
–
–
–
Unit
mV
nA
nA
AVOL
Output Voltage Swing (Peak–to–Peak)
(RL ≥ 10 k)
(RL ≥ 2.0 k)
V/mV
VO
V
NOTES: 1. Tlow = 0°C for TL081AC,C
Thigh = 70°C for TL081AC
0°C for TL082AC,C
+70°C for TL082AC,C
0°C for TL084AC,C
+70°C for TL084AC,C
2. Input Bias currents of JFET input op amps approximately double for every 10°C rise in Junction Temperature as shown in Figure 3. To maintain
junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing.
Figure 1. Unity Gain Voltage Follower
Figure 2. Inverting Gain of 10 Amplifier
10 k
1.0 k
Vin
VO
+
RL = 2.0 k
Vin
CL = 100 pF
-
VO
+
RL
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2
CL = 100 pF
TL081C,AC TL082C,AC TL084C,AC
ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
–
–
–
5.0
5.0
3.0
15
15
6.0
–
10
–
–
–
5.0
5.0
200
100
–
–
30
30
400
200
–
1012
–
±10
±11
15, –12
15, –12
–
–
25
50
150
150
–
–
24
28
–
70
80
100
100
–
–
70
80
100
100
–
–
ID
–
1.4
2.8
mA
Unity Gain Bandwidth
BW
–
4.0
–
MHz
Slew Rate (See Figure 1)
Vin = 10 V, RL = 2.0 k, CL = 100 pF
SR
–
13
–
V/µs
tr
–
0.1
–
µs
Overshoot (Vin = 20 mV, RL = 2.0 k, CL = 100 pF)
OS
–
10
–
%
Equivalent Input Noise Voltage
RS = 100 Ω, f = 1000 Hz
en
–
25
–
nV/ √ Hz
Channel Separation
AV = 100
CS
–
120
–
dB
Input Offset Voltage (RS ≤ 10 k, VCM = 0)
TL081C, TL082C
TL084C
TL08_AC
VIO
∆VIO/∆T
Average Temperature Coefficient of Input Offset Voltage
RS = 50 Ω, TA = Tlow to Thigh (Note 1)
Input Offset Current (VCM = 0) (Note 2)
TL08_C
TL08_AC
IIO
Input Bias Current (VCM = 0) (Note 2)
TL08_C
TL08_AC
IIB
Input Resistance
ri
Common Mode Input Voltage Range
TL08_C
TL08_AC
VICR
Large Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k)
TL08_C
TL08_AC
AVOL
Output Voltage Swing (Peak–to–Peak)
(RL = 10 k)
VO
Common Mode Rejection Ratio (RS ≤ 10 k)
TL08_C
TL08_AC
CMRR
Supply Voltage Rejection Ratio (RS ≤ 10 k)
TL08_C
TL08_AC
PSRR
Supply Current (Each Amplifier)
Rise Time (See Figure 1)
Unit
mV
µV/°C
pA
pA
Ω
V
V/mV
V
dB
dB
NOTES: 1. Tlow = 0°C for TL081AC,C
Thigh = 70°C for TL081AC
0°C for TL082AC,C
+70°C for TL082AC,C
0°C for TL084AC,C
+70°C for TL084AC,C
2. Input Bias currents of JFET input op amps approximately double for every 10°C rise in Junction Temperature as shown in Figure 3. To maintain
junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing.
http://onsemi.com
3
TL081C,AC TL082C,AC TL084C,AC
Figure 3. Input Bias Current
versus Temperature
Figure 4. Output Voltage Swing
versus Frequency
10
35
VO, OUTPUT VOLTAGE SWING (Vpp )
IIB , INPUT BIAS CURRENT (nA)
100
VCC/VEE = ±15 V
1.0
0.1
0.01
-100 -75
-50
-25
0
25
50
75
100
±5.0 V
10
5.0
1.0 k
10 k
100 k
1.0 M
10 M
40
VO, OUTPUT VOLTAGE SWING (Vpp )
VO, OUTPUT VOLTAGE SWING (Vpp )
15
Figure 6. Output Voltage Swing
versus Supply Voltage
VCC/VEE = ±15 V
TA = 25°C
(See Figure 2)
0.2
0.4
0.7 1.0
2.0
4.0
7.0
20
10
0
5.0
10
15
20
RL, LOAD RESISTANCE (kΩ)
VCC, |VEE| , SUPPLY VOLTAGE (±V)
Figure 7. Output Voltage Swing
versus Temperature
Figure 8. Supply Current per Amplifier
versus Temperature
ID , SUPPLY DRAIN CURRENT (mA)
VCC/VEE = ±15 V
(See Figure 2)
RL = 10 k
30
25
RL = 2.0 k
20
15
10
5.0
-50
RL = 2.0 k
TA = 25°C
30
0
10
40
VO, OUTPUT VOLTAGE SWING (Vpp )
±10 V
Figure 5. Output Voltage Swing
versus Load Resistance
5.0
0
-75
20
f, FREQUENCY (Hz)
10
35
25
TA, AMBIENT TEMPERATURE (°C)
20
0
0.1
RL = 2.0 k
TA = 25°C
(See Figure 2)
VCC/VEE = ±15 V
0
100
125 150
40
30
30
-25
0
25
50
75
100
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-75
125
VCC/VEE = ±15 V
TA, AMBIENT TEMPERATURE (°C)
-50
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
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4
100
125
TL081C,AC TL082C,AC TL084C,AC
Figure 9. Large Signal Voltage Gain and
Phase Shift versus Frequency
Figure 10. Large Signal Voltage Gain
versus Temperature
106
105
104
103
45°
102
1.0
90°
Phase Shift
101
1.0
0°
Gain
10
100
1.0 k
135°
10 k
A VOL, OPEN-LOOP GAIN (V/m/v)
1000
VCC/VEE = ±15 V
RL = 2.0 k
TA = 25°C
107
PHASE SHIFT (DEGREES)
A VOL, OPEN-LOOP GAIN (V/m/v)
108
180°
10 M 100 M
100 k 1.0 M
VCC/VEE = ±15 V
VO = ±10 V
RL = 2.0 k
100
10
1.0
-100
-75
-50
en, EQUIVALENT INPUT NOISE VOLTAGE ( nV/ √ Hz )
Figure 11. Normalized Slew Rate
versus Temperature
1.20
1.10
1.05
1.0
0.95
0.90
0.85
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
1.0
0.5
0.1
50
75
100
125
150
70
VCC/VEE = ±15 V
AV = 10
RS = 100 Ω
TA = 25°C
60
50
40
30
20
10
0
0.01
0.05 0.1
0.5 1.0
f, FREQUENCY (Hz)
VCC/VEE = ±15 V
AV = 1.0
VO = 6.0 V (RMS)
TA = 25°C
0.05
0.01
0.005
0.001
0.1
25
Figure 12. Equivalent Input Noise Voltage
versus Frequency
Figure 13. Total Harmonic Distortion
versus Frequency
THD, TOTAL HARMONIC DISTORTION (%)
NORMALIZED SLEW RATE
1.15
-50
0
TA, AMBIENT TEMPERATURE (°C)
f, FREQUENCY (Hz)
0.80
-75
-25
0.5
1.0
5.0
10
f, FREQUENCY (Hz)
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5
50
100
5.0 10
50 100
TL081C,AC TL082C,AC TL084C,AC
Figure 14. Positive Peak Detector
Figure 15. Voltage Controlled Current Source
R3
Vin
1/2
TL082
Vin
1N914
+
VO
R5
IO
-
R2
+
*
1.0 µF
+
TL081
1/2
TL082
-
R1
R4
If R1 through R4 > > R5 then Iout =
*Polycarbonate or
Polystyrene Capacitor
Reset
Figure 16. Long Interval RC Timer
VR
R4
V1
R3
-
TL081
R2
6
R1 5.1 k
+
Run
+
2.0 V
0
-2.0 V
C*
R5
CC 20 pF
TL081
R6
Clear
in
R5
Figure 17. Isolating Large Capacitive Loads
R2 5.1 k
R1
V
VO
IO
R3 10
RL 5.1 k
CL 0.5 µF
•Overshoot 10%
•ts = 10 µs
•When driving large CL, the VO slew rate is determined by CL
•and IO(max):
*Polycarbonate or
Polystyrene Capacitor
Time (t) = R4 Cn (VR/VR-VI), R3 = R4, R5 = 0.1 R6
If R1 = R2: t = 0.693 R4C
V
I
O O 0.02 V/µs = 0.04 V/µs (with C shown)
L
t
0.5
C
L
Design Example: 100 Second Timer
VR = 10 V C = l.0 mF R3 = R4 = 144 M
R6 = 20 k R5 = 2.0 k
R1 = R2 = 1.0 k
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6
TL081C,AC TL082C,AC TL084C,AC
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
8
5
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–B–
1
4
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
–A–
NOTE 2
L
C
J
–T–
N
SEATING
PLANE
D
M
K
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
G
H
0.13 (0.005)
T A
M
M
B
M
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE S
D
A
8
5
0.25
H
E
1
M
B
M
4
h
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
e
X 45
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
S
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7
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.18
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
7
TL081C,AC TL082C,AC TL084C,AC
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
–T–
SEATING
PLANE
J
K
H
G
D 14 PL
M
0.13 (0.005)
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
--10
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
--10
0.38
1.01
M
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to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products
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and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
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TL081C/D
