TL431

TL431, A, B Series, NCV431A Programmable Precision References The TL431, A, B integrated circuits are three−terminal programmable shunt regulator diodes. These monolithic IC voltage references operate as a low temperature coefficient zener which is programmable from Vref to 36 V with two external resistors. These devices exhibit a wide operating current range of 1.0 mA to 100 mA with a typical dynamic impedance of 0.22 W. The characteristics of these references make them excellent replacements for zener diodes in many applications such as digital voltmeters, power supplies, and op amp circuitry. The 2.5 V reference makes it convenient to obtain a stable reference from 5.0 V logic supplies, and since the TL431, A, B operates as a shunt regulator, it can be used as either a positive or negative voltage reference. Features http://onsemi.com TO−92 (TO−226) LP SUFFIX CASE 29 1 2 3 Pin 1. Reference 2. Anode 3. Cathode 8 1 PDIP−8 P SUFFIX CASE 626 Micro8E DM SUFFIX CASE 846A • • • • • • • • Programmable Output Voltage to 36 V Voltage Reference Tolerance: ±0.4%, Typ @ 25°C (TL431B) Low Dynamic Output Impedance, 0.22 W Typical Sink Current Capability of 1.0 mA to 100 mA Equivalent Full−Range Temperature Coefficient of 50 ppm/°C Typical Temperature Compensated for Operation over Full Rated Operating Temperature Range Low Output Noise Voltage Pb−Free Packages are Available 8 8 1 Cathode 1 N/C 2 N/C 3 N/C 4 (Top View) 8 Reference 7 N/C 6 Anode 5 N/C SOIC−8 D SUFFIX CASE 751 1 Cathode 1 Anode 2 3 N/C 4 (Top View) 8 7 6 5 Reference Anode N/C This is an internally modified SOIC−8 package. Pins 2, 3, 6 and 7 are electrically common to the die attach flag. This internal lead frame modification increases power dissipation capability when appropriately mounted on a printed circuit board. This modified package conforms to all external dimensions of the standard SOIC−8 package. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 15 of this data sheet. © Semiconductor Components Industries, LLC, 2005 1 March, 2005 − Rev. 21 Publication Order Number: TL431/D TL431, A, B Series, NCV431A Symbol Cathode (K) Reference (R) 800 Anode (A) Reference (R) 800 20 pF Representative Schematic Diagram Component values are nominal Cathode (K) Representative Block Diagram Reference (R) Cathode (K) 2.4 k 3.28 k 20 pF 7.2 k 150 4.0 k 10 k + − 2.5 Vref 1.0 k 800 Anode (A) Anode (A) This device contains 12 active transistors. MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.) Rating Cathode to Anode Voltage Cathode Current Range, Continuous Reference Input Current Range, Continuous Operating Junction Temperature Operating Ambient Temperature Range TL431I, TL431AI, TL431BI TL431C, TL431AC, TL431BC NCV431AI, TL431BV Storage Temperature Range Total Power Dissipation @ TA = 25°C Derate above 25°C Ambient Temperature D, LP Suffix Plastic Package P Suffix Plastic Package DM Suffix Plastic Package Total Power Dissipation @ TC = 25°C Derate above 25°C Case Temperature D, LP Suffix Plastic Package P Suffix Plastic Package NOTE: ESD data available upon request. Symbol VKA IK Iref TJ TA −40 to +85 0 to +70 −40 to +125 Tstg PD 0.70 1.10 0.52 PD 1.5 3.0 W −65 to +150 °C W Value 37 −100 to +150 −0.05 to +10 150 Unit V mA mA °C °C RECOMMENDED OPERATING CONDITIONS Condition Cathode to Anode Voltage Cathode Current Symbol VKA IK Min Vref 1.0 Max 36 100 Unit V mA THERMAL CHARACTERISTICS Characteristic Thermal Resistance, Junction−to−Ambient Thermal Resistance, Junction−to−Case Symbol RqJA RqJC D, LP Suffix Package 178 83 P Suffix Package 114 41 DM Suffix Package 240 − Unit °C/W °C/W http://onsemi.com 2 TL431, A, B Series, NCV431A ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.) TL431I Characteristic Reference Input Voltage (Figure 1) VKA = Vref, IK = 10 mA TA = 25°C TA = Tlow to Thigh (Note 1) High Logic Level Supply Current from VCC Reference Input Voltage Deviation Over Temperature Range (Figure 1, Notes 1, 2) VKA= Vref, IK = 10 mA Ratio of Change in Reference Input Voltage to Change in Cathode to Anode Voltage IK = 10 mA (Figure 2), DVKA = 10 V to Vref DVKA = 36 V to 10 V Reference Input Current (Figure 2) IK = 10 mA, R1 = 10 k, R2 = ∞ TA = 25°C TA = Tlow to Thigh (Note 1) Reference Input Current Deviation Over Temperature Range (Figure 2, Note 1, 4) IK = 10 mA, R1 = 10 k, R2 = ∞ Minimum Cathode Current For Regulation VKA = Vref (Figure 1) Off−State Cathode Current (Figure 3) VKA = 36 V, Vref = 0 V Dynamic Impedance (Figure 1, Note 3) VKA = Vref, DIK = 1.0 mA to 100 mA f ≤ 1.0 kHz 1. Tlow Symbol Vref 2.44 2.41 ICCH DVref 60 − 2.495 − − 7.0 2.55 2.58 45 30 2.44 2.423 60 − 2.495 − mA 3.0 2.55 2.567 mA 17 mA mV Min Typ Max Min TL431C Typ Max Unit V DV DV ref − − −1.4 −1.0 −2.7 −2.0 − − −1.4 −1.0 −2.7 −2.0 mV/V KA Iref − − DIref − 1.8 − 0.8 4.0 6.5 2.5 − − − 1.8 − 0.4 4.0 5.2 1.2 mA mA Imin Ioff |ZKA| − − − 0.5 20 0.22 1.0 1000 0.5 − − − 0.5 20 0.22 1.0 1000 0.5 mA nA W = −40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM; = 0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM 2. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies. Vref max DVref = Vref max −Vref min DTA = T2 − T1 Vref min T1 T2 Ambient Temperature DV The average temperature coefficient of the reference input voltage, aVref is defined as: ppm V + ref _C V ref ref @ 25_C DT A X 106 + D V x 10 6 ref D T (V @ 25_C) A ref aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example : DV V ref + 8.0 mV and slope is positive, aV DV ref + 0.008 x 106 + 45.8 ppm _C 70 (2.495) @ 25_C + 2.495 V, DT + 70_C ref A KA 3. The dynamic impedance ZKA is defined as: |Z KA| + . When the device is programmed with two external resistors, R1 and R2, DI K (refer to Figure 2) the total dynamic impedance of the circuit is defined as: |Z KA | [ |Z KA| 1 ) R1 R2 http://onsemi.com 3 TL431, A, B Series, NCV431A ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.) TL431AI / NCV431AI Characteristic Reference Input Voltage (Figure 1) In ut Voltage (Figure 1) VKA = Vref, IK = 10 mA mA TA = 25°C 25 TA = Tlow to Thigh Reference Input Voltage Deviation Over Temperature Range (Figure 1, Notes 4, 5) VKA= Vref, IK = 10 mA Ratio of Change in Reference Input Voltage to Change in Cathode to Anode Voltage IK = 10 mA (Figure 2), DVKA = 10 V to Vref DVKA = 36 V to 10 V Reference Input Current (Figure 2) IK = 10 mA, R1 = 10 k, R2 = ∞ TA = 25°C TA = Tlow to Thigh (Note 4) Reference Input Current Deviation Over Temperature Range (Figure 2, Note 4) IK = 10 mA, R1 = 10 k, R2 = ∞ Minimum Cathode Current For Regulation VKA = Vref (Figure 1) Off−State Cathode Current (Figure 3) VKA = 36 V, Vref = 0 V Dynamic Impedance (Figure 1, Note 6) VKA = Vref, DIK = 1.0 mA to 100 mA f ≤ 1.0 kHz 4. Tlow Symbol Vref 2.47 2 47 2.44 2 44 DVref − 2.495 2 495 − 7.0 2.52 2 52 2.55 2 55 30 2.47 2 47 2.453 2 453 − 2.495 2 495 − 3.0 2.52 2 52 2.537 2 537 17 2.483 2 483 2.475 2 475 − 2.495 2 495 2.495 2 495 3.0 2.507 2 507 2.515 2 515 17 mV Min Typ Max Min TL431AC Typ Max TL431BI / TL431BV Min Typ Max Unit V DV DV ref − − −1.4 −1.0 −2.7 −2.0 − − −1.4 −1.0 −2.7 −2.0 − − −1.4 −1.0 −2.7 −2.0 mV/V KA Iref − − DIref − 1.8 − 0.8 4.0 6.5 2.5 − − − 1.8 − 0.4 4.0 5.2 1.2 − − − 1.1 − 0.8 2.0 4.0 2.5 mA mA Imin Ioff |ZKA| − − − 0.5 20 0.22 1.0 1000 0.5 − − − 0.5 20 0.22 1.0 1000 0.5 − − − 0.5 0.23 0.14 1.0 500 0.3 mA nA W = −40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431BV, TL431AIDM, TL431IDM, TL431BIDM, NCV431AIDMR2, NCV431AIDR2 = 0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM = +125°C TL431BV, NCV431AIDMR2, NCV431AIDR2 5. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies. Vref max DVref = Vref max −Vref min DTA = T2 − T1 Vref min T1 T2 Ambient Temperature DV ppm + V ref _C V ref ref @ 25_C DT A X 106 + The average temperature coefficient of the reference input voltage, aVref is defined as: D V x 10 6 ref D T (V @ 25_C) A ref aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example : DV V ref + 8.0 mV and slope is positive, aV DV ref + 0.008 x 106 + 45.8 ppm _C 70 (2.495) @ 25_C + 2.495 V, DT + 70_C ref A KA 6. The dynamic impedance ZKA is defined as |Z KA| + When the device is programmed with two external resistors, R1 and R2, (refer DI K to Figure 2) the total dynamic impedance of the circuit is defined as: |Z KA | [ |Z KA| 1 ) R1 R2 7. NCV431AIDMR2, NCV431AIDR2 Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and change control. http://onsemi.com 4 TL431, A, B Series, NCV431A Input IK VKA Input R1 Iref IK VKA Input Ioff VKA Vref R2 Vref V KA +V ref 1 ) R1 ) I S R1 ref R2 Figure 1. Test Circuit for VKA = Vref Figure 2. Test Circuit for VKA > Vref Figure 3. Test Circuit for Ioff 150 IK , CATHODE CURRENT (mA) IK , CATHODE CURRENT ( µA) 100 50 0 −50 −100 −2.0 VKA = Vref TA = 25°C Input IK VKA 800 600 Input 400 200 0 VKA = Vref TA = 25°C VKA IK IMin −1.0 0 1.0 2.0 3.0 −200 −1.0 0 1.0 VKA, CATHODE VOLTAGE (V) 2.0 3.0 VKA, CATHODE VOLTAGE (V) Figure 4. Cathode Current versus Cathode Voltage Figure 5. Cathode Current versus Cathode Voltage Vref , REFERENCE INPUT VOLTAGE (mV) 2580 2560 2540 2520 2500 2480 2460 2440 2420 Input Vref Vref Max = 2550 mV Iref , REFERENCE INPUT CURRENT ( µA) 2600 VKA IK VKA = Vref IK = 10 mA 3.0 2.5 2.0 1.5 IK = 10 mA 1.0 0.5 0 −55 −25 0 25 50 75 100 125 Input 10k Iref IK VKA Vref Typ = 2495 mV Vref Min = 2440 mV 2400 −55 −25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 6. Reference Input Voltage versus Ambient Temperature Figure 7. Reference Input Current versus Ambient Temperature http://onsemi.com 5 TL431, A, B Series, NCV431A ∆ Vref , REFERENCE INPUT VOLTAGE (mV) IK = 10 mA TA = 25°C −8.0 Ioff , OFF−STATE CATHODE CURRENT (nA) 0 1.0 k 100 10 1.0 0.1 0.01 −55 VKA = 36 V Vref = 0 V Ioff −16 Input R1 IK Vref VKA Input VKA −24 R2 −32 0 10 20 30 40 −25 0 25 50 75 100 125 VKA, CATHODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (5C) Figure 8. Change in Reference Input Voltage versus Cathode Voltage Figure 9. Off−State Cathode Current versus Ambient Temperature 100 |ZKA|, DYNAMIC IMPEDANCE (Ω ) 1.0 k 50 10 − + Output IK GND |ZKA|, DYNAMIC IMPEDANCE (Ω ) TA = 25°C D IK = 1.0 mA to 100 mA 0.320 0.300 0.280 0.260 0.240 0.220 0.200 −55 −25 0 25 50 75 100 125 VKA = Vref D IK = 1.0 mA to 100 mA f ≤ 1.0 kHz Output 1.0 k IK 50 − + GND 1.0 0.1 1.0 k 10 k 100 k f, FREQUENCY (MHz) 1.0 M 10 M TA, AMBIENT TEMPERATURE (°C) Figure 10. Dynamic Impedance versus Frequency Figure 11. Dynamic Impedance versus Ambient Temperature A VOL, OPEN LOOP VOLTAGE GAIN (dB) 60 50 40 30 20 10 0 −10 1.0 k 10 k 100 k f, FREQUENCY (MHz) 1.0 M 10 M IK = 10 mA TA = 25°C NOISE VOLTAGE (nV/ √Hz) 9.0 mF 15 k 8.25 k GND IK 230 Output 80 60 40 Input 20 VKA = Vref IK = 10 mA TA = 25°C Output IK 0 10 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k Figure 12. Open−Loop Voltage Gain versus Frequency Figure 13. Spectral Noise Density http://onsemi.com 6 TL431, A, B Series, NCV431A 3.0 VOLTAGE SWING (V) 2.0 1.0 0 5.0 0 0 4.0 Input 8.0 t, TIME (ms) 12 16 20 TA = 25°C Output 140 Input Monitor Pulse Generator f = 100 kHz 220 Output 50 GND 120 I K, CATHODE CURRENT (mA) 100 80 60 40 20 0 1.0 nF A 1.0 mF Stable B D B A 10 mF 100 mF Stable Unstable Area A B C D Programmed VKA(V) Vref 5.0 10 15 C TA = 25°C 10 nF 100 nF CL, LOAD CAPACITANCE Figure 14. Pulse Response Figure 15. Stability Boundary Conditions 150 IK V+ CL V+ 150 IK 10 k CL Figure 16. Test Circuit For Curve A of Stability Boundary Conditions Figure 17. Test Circuit For Curves B, C, And D of Stability Boundary Conditions TYPICAL APPLICATIONS V+ R1 Vout V+ R1 Vout R2 R2 V out + 1 ) R1 V R2 ref 1 ) R1 V R2 ref V out + Figure 18. Shunt Regulator Figure 19. High Current Shunt Regulator http://onsemi.com 7 TL431, A, B Series, NCV431A V+ V+ MC7805 Out In Common R1 Vout R1 Vout R2 R2 1 ) R1 V R2 ref ref ) 5.0V V out + 1 ) R1 V R2 ref ref )V be V out + V out min + V V out min + V Figure 20. Output Control for a Three−Terminal Fixed Regulator Figure 21. Series Pass Regulator V+ RCL Iout V+ Isink I V I out + ref R CL Sink V + ref R S RS Figure 22. Constant Current Source Figure 23. Constant Current Sink V+ R1 Vout V+ R1 Vout R2 R2 V out(trip) + 1 ) R1 V R2 ref 1 ) R1 V R2 ref V out(trip) + Figure 24. TRIAC Crowbar Figure 25. SRC Crowbar http://onsemi.com 8 TL431, A, B Series, NCV431A V+ l R1 R3 Vout V+ Vout Vin R2 R4 Vth = Vref Vin < Vref > Vref Vout V+ ≈ 2.0 V L.E.D. indicator is ‘on’ when V+ is between the upper and lower limits. Lower Limit + Upper Limit + 1 ) R1 V R2 ref 1 ) R3 V R4 ref Figure 26. Voltage Monitor Figure 27. Single−Supply Comparator with Temperature−Compensated Threshold 25 V 1N5305 2.0 mA 10 k Calibrate 25 V − LM11 + Tl = 330 to 8.0 W TI 8.0 W 38 V 330 5.0 k 1% 50 k 1% 10 kW V 500 k 1% 5.0 M 1% + 360 k 1.0 mF 470 mF 1.0 kW V RX 100 kW 1.0 MW V V Range Vout * Thermalloy * THM 6024 * Heatsink on * LP Package * 0.05 mF Tone 25 k Volume 47 k −5.0 V W Range R x + V out D V 56 k 10 k Figure 28. Linear Ohmmeter Figure 29. Simple 400 mW Phono Amplifier http://onsemi.com 9 TL431, A, B Series, NCV431A 150 mH @ 2.0 A Vin = 10 V to 20 V 1.0 k 4.7 k MPSA20 2200 mF 4.7 k 0.1 mF 2.2 k 10 51 k 4.7 k 1N5823 0.01mF 100 k 470 mF + TIP115 Vout = 5.0 V Iout = 1.0 A + Figure 30. High Efficiency Step−Down Switching Converter Test Line Regulation Load Regulation Output Ripple Output Ripple Efficiency Conditions Vin = 10 V to 20 V, Io = 1.0 A Vin = 15 V, Io = 0 A to 1.0 A Vin = 10 V, Io = 1.0 A Vin = 20 V, Io = 1.0 A Vin = 15 V, Io = 1.0 A Results 53 mV (1.1%) 25 mV (0.5%) 50 mVpp P.A.R.D. 100 mVpp P.A.R.D. 82% http://onsemi.com 10 TL431, A, B Series, NCV431A APPLICATIONS INFORMATION The TL431 is a programmable precision reference which is used in a variety of ways. It serves as a reference voltage in circuits where a non−standard reference voltage is needed. Other uses include feedback control for driving an optocoupler in power supplies, voltage monitor, constant current source, constant current sink and series pass regulator. In each of these applications, it is critical to maintain stability of the device at various operating currents and load capacitances. In some cases the circuit designer can estimate the stabilization capacitance from the stability boundary conditions curve provided in Figure 15. However, these typical curves only provide stability information at specific cathode voltages and at a specific load condition. Additional information is needed to determine the capacitance needed to optimize phase margin or allow for process variation. A simplified model of the TL431 is shown in Figure 31. When tested for stability boundaries, the load resistance is 150 W. The model reference input consists of an input transistor and a dc emitter resistance connected to the device anode. A dependent current source, Gm, develops a current whose amplitude is determined by the difference between the 1.78 V internal reference voltage source and the input transistor emitter voltage. A portion of Gm flows through compensation capacitance, CP2. The voltage across CP2 drives the output dependent current source, Go, which is connected across the device cathode and anode. Model component values are: Vref = 1.78 V Gm = 0.3 + 2.7 exp (−IC/26 mA) where IC is the device cathode current and Gm is in mhos P2 + 2p R 1 C P2 P2 1 C Z1 P1 + 1 + 60 kHz 2p * 10 M * 0.265 pF 1 + 500 kHz 2p * 15.9 k * 20 pF Z1 + 2p R + In addition, there is an external circuit pole defined by the load: 1 P+ L 2p R C LL Also, the transfer dc voltage gain of the TL431 is: G+G R GoR M GM L Example 1: I + 10 mA, R + 230 W, C + 0. Define the transfer gain. L L C The DC gain is: G+G R GoR + M GM L (2.138)(1.0 M)(1.25 m)(230) + 615 + 56 dB Loop gain + G 8.25 k + 218 + 47 dB 8.25 k ) 15 k The resulting transfer function Bode plot is shown in Figure 32. The asymptotic plot may be expressed as the following equation: 1) Av + 615 1) jf 500 kHz 1) jf 60 kHz Go = 1.25 (Vcp2) mmhos. Resistor and capacitor typical values are shown on the model. Process tolerances are ± 20% for resistors, ±10% for capacitors, and ±40% for transconductances. An examination of the device model reveals the location of circuit poles and zeroes: P1 + 2p R 1 GM C P1 + 1 + 7.96 kHz 2p * 1.0 M * 20 pF jf 8.0 kHz The Bode plot shows a unity gain crossover frequency of approximately 600 kHz. The phase margin, calculated from the equation, would be 55.9 degrees. This model matches the Open−Loop Bode Plot of Figure 12. The total loop would have a unity gain frequency of about 300 kHz with a phase margin of about 44 degrees. http://onsemi.com 11 TL431, A, B Series, NCV431A VCC RL Input 15 k 9.0 mF Ref 1 500 k 8.25 k CL 3 Cathode RP2 10 M + − GM Rref 16 Vref 1.78 V Go 1.0 mmho CP2 0.265 pF RGM 1.0 M CP1 20 pF RZ1 15.9 k Anode 2 Figure 31. Simplified TL431 Device Model TL431 OPEN−LOOP VOLTAGE GAIN VERSUS FREQUENCY 60 Av, OPEN−LOOP VOLTAGE GAIN (dB) 50 40 30 20 10 Av, OPEN−LOOP GAIN (dB) 0 −10 −20 101 102 103 104 105 106 107 f, FREQUENCY (Hz) 60 40 20 0 −20 101 102 103 104 105 106 f, FREQUENCY (Hz) TL431 OPEN−LOOP BODE PLOT WITH LOAD CAP 80 Note that the transfer function now has an extra pole formed by the load capacitance and load resistance. Note that the crossover frequency in this case is about 250 kHz, having a phase margin of about −46 degrees. Therefore, instability of this circuit is likely. Figure 32. Example 1 Circuit Open Loop Gain Plot Example 2. IC = 7.5 mA, RL = 2.2 kW, CL = 0.01 mF. Cathode tied to reference input pin. An examination of the data sheet stability boundary curve (Figure 15) shows that this value of load capacitance and cathode current is on the boundary. Define the transfer gain. The DC gain is: G+G R GoR + M GM L (2.323)(1.0 M)(1.25 m)(2200) + 6389 + 76 dB Figure 33. Example 2 Circuit Open Loop Gain Plot The resulting open loop Bode plot is shown in Figure 33. The asymptotic plot may be expressed as the following equation: 1) Av + 615 1) jf 8.0 kHz jf 500 kHz jf 60 kHz 1) jf 7.2 kHz With three poles, this system is unstable. The only hope for stabilizing this circuit is to add a zero. However, that can only be done by adding a series resistance to the output capacitance, which will reduce its effectiveness as a noise filter. Therefore, practically, in reference voltage applications, the best solution appears to be to use a smaller value of capacitance in low noise applications or a very large value to provide noise filtering and a dominant pole rolloff of the system. 1) http://onsemi.com 12 TL431, A, B Series, NCV431A ORDERING INFORMATION Device TL431ACD TL431ACDG TL431BCD TL431BCDG TL431CD TL431ACDR2 TL431ACDR2G TL431BCDR2 TL431BCDR2G TL431CDR2 TL431CDR2G TL431ACDMR2 TL431BCDMR2 TL431BCDMR2G TL431CDMR2 TL431CDMR2G TL431ACP TL431BCP TL431CP TL431CPG TL431ACLP TL431ACLPG TL431BCLP TL431BCLPG TL431CLP TL431CLPG TL431ACLPRA TL431ACLPRAG TL431BCLPRA TL431BCLPRAG TL431CLPRA TL431CLPRAG TL431ACLPRE TL431ACLPREG TL431BCLPRE PDIP−8 (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) 2000 Units / Tape & Reel 2000 Units / Bag 0°C to 70°C to 70 PDIP−8 50 Units / Rail Operating Temperature Range Package Code SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) Micro8 Micro8 Micro8 (Pb−Free) Micro8 Micro8 (Pb−Free) 2500 Units / Tape & Reel 98 Units / Rail Shipping Information† Tolerance 1.0% 1.0% 0.4% 0.4% 2.2% 1.0% 1.0% 0.4% 0.4% 2.2% 2.2% 1.0% 0.4% 4000 Units / Tape & Reel 0.4% 2.2% 2.2% 1.0% 0.4% 2.2% 2.2% 1.0% 1.0% 0.4% 0.4% 2.2% 2.2% 1.0% 1.0% 0.4% 0.4% 2.2% 2.2% 1.0% 1.0% 0.4% †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 13 TL431, A, B Series, NCV431A ORDERING INFORMATION Device TL431BCLPREG TL431ACLPRP TL431ACLPRPG TL431BCLPRM TL431BCLPRMG TL431CLPRP TL431CLPRPG TL431AID TL431AIDG TL431BID TL431BIDG TL431ID TL431IDG TL431AIDR2 TL431AIDR2G TL431BIDR2 TL431BIDR2G TL431IDR2 TL431IDR2G TL431AIDMR2 TL431BIDMR2 TL431BIDMR2G TL431IDMR2 TL431IDMR2G TL431AIP TL431AIPG TL431BIP TL431IP TL431AILP TL431BILP TL431BILPG TL431ILP TL431ILPG TL431AILPRA TL431AILPRAG −40°C to 85°C −40 to 0°C to 70°C Operating Temperature Range Package Code TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) Micro8 Micro8 Micro8 (Pb−Free) Micro8 Micro8 (Pb−Free) PDIP−8 PDIP−8 (Pb−Free) PDIP−8 PDIP−8 TO−92 (TO−226) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) 2000 Units / Tape & Reel Units Rail 50 Units / Rail 2500 Units / Tape & Reel 98 Units / Rail 2000 Units / Fan−Fold Shipping Information† 2000 Units / Tape & Reel Tolerance 0.4% 1.0% 1.0% 0.4% 0.4% 2.2% 2.2% 1.0% 1.0% 0.4% 0.4% 2.2% 2.2% 1.0% 1.0% 0.4% 0.4% 2.2% 2.2% 1.0% 0.4% 4000 Units / Tape & Reel 0.4% 2.2% 2.2% 1.0% 1.0% 0.4% 2.2% 1.0% 0.4% 2000 Units / Box 0.4% 2.2% 2.2% 1.0% 1.0% †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 14 TL431, A, B Series, NCV431A ORDERING INFORMATION Device TL431BILPRA TL431BILPRAG TL431ILPRA TL431ILPRAG TL431AILPRM TL431AILPRP TL431ILPRP TL431BVD TL431BVDR2 TL431BVDMR2 TL431BVLP TL431BVP NCV431AIDMR2 NCV431AIDR2 −40°C to 125°C SOIC−8 SOIC−8 Micro8 TO−92 (TO−226) PDIP−8 Micro8 SOIC−8 98 Units / Rail Units Rail 4000 Units / Tape & Reel 2000 Units / Box 50 Units / Rail 4000 Units / Tape & Reel 2500 Units / Tape & Reel TO−92 ( (TO−226) ) 2000 Units / Ammo Pack −40°C to 85°C Operating Temperature Range Package Code TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) TO−92 (TO−226) TO−92 (TO−226) (Pb−Free) 2000 Units / Tape & Reel Units Tape Reel Shipping Information† Tolerance 0.4% 0.4% 2.2% 2.2% 1.0% 1.0% 2.2% 0.4% 0.4% 0.4% 0.4% 0.4% 1% 1% †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS SOIC−8 D SUFFIX CASE 751 8 xx ALYW 1 1 Micro8 CASE 846A 8 xx AYW 1 8 xx xx AWL YYWW PDIP−8 CASE 626 TO−92 (TO−226) CASE 29 12 3 xx A WL, L YY, Y WW, W = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week http://onsemi.com 15 TL431, A, B Series, NCV431A PACKAGE DIMENSIONS A R P L SEATING PLANE B TO−92 (TO−226) LP SUFFIX PLASTIC PACKAGE CASE 29−11 ISSUE AL NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 −−− 0.250 −−− 0.080 0.105 −−− 0.100 0.115 −−− 0.135 −−− MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 −−− 6.35 −−− 2.04 2.66 −−− 2.54 2.93 −−− 3.43 −−− K XX G H V 1 D J C SECTION X−X N N DIM A B C D G H J K L N P R V 8 5 PDIP−8 P SUFFIX PLASTIC PACKAGE CASE 626−05 ISSUE L −B− NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040 1 4 F NOTE 2 −A− L C −T− SEATING PLANE J N D K M M H G 0.13 (0.005) TA M B M http://onsemi.com 16 TL431, A, B Series, NCV431A PACKAGE DIMENSIONS Micro8 DM SUFFIX PLASTIC PACKAGE CASE 846A−02 ISSUE F −A− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A−01 OBSOLETE, NEW STANDARD 846A−02. DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 −−− 1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 −−− 0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028 K −B− PIN 1 ID G D 8 PL 0.08 (0.003) M TB S A S −T− PLANE 0.038 (0.0015) H SEATING C J L SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 8X 3.20 0.126 4.24 0.167 5.28 0.208 6X 0.65 0.0256 SCALE 8:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 17 TL431, A, B Series, NCV431A SOIC−8 D SUFFIX PLASTIC PACKAGE CASE 751−07 ISSUE AE −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Micro8 is a trademark of International Rectifier. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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