DATA SHEET
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Programmable
Precision References
TL431A, B Series,
NCV431A, B Series,
SCV431A
Pin 1. Reference
2. Anode
3. Cathode
The TL431A, B integrated circuits are three−terminal
programmable shunt regulator diodes. These monolithic IC voltage
references operate as a low temperature coefficient zener which is
programmable from Vref to 36 V with two external resistors. These
devices exhibit a wide operating current range of 1.0 mA to 100 mA
with a typical dynamic impedance of 0.22 W. The characteristics of
these references make them excellent replacements for zener diodes in
many applications such as digital voltmeters, power supplies, and op
amp circuitry. The 2.5 V reference makes it convenient to obtain
a stable reference from 5.0 V logic supplies, and since the TL431A,
B operates as a shunt regulator, it can be used as either a positive or
negative voltage reference.
3
STRAIGHT LEAD
BULK PACK
•
•
•
TO−92
LPRA, LPRE, LPRM,
LPRP SUFFIX
CASE 29−10
PDIP−8
P SUFFIX
CASE 626
8
Micro8E
DM SUFFIX
CASE 846A
1
Cathode 1
Programmable Output Voltage to 36 V
Voltage Reference Tolerance: ±0.4%, Typ @ 25°C (TL431B)
Low Dynamic Output Impedance, 0.22 W Typical
Sink Current Capability of 1.0 mA to 100 mA
Equivalent Full−Range Temperature Coefficient of 50 ppm/°C Typical
Temperature Compensated for Operation over Full Rated Operating
Temperature Range
Low Output Noise Voltage
NCV/SCV Prefixes for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC−Q100 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
2
3
BENT LEAD
TAPE & REEL
AMMO PACK
TO−92
LP SUFFIX
CASE 29−10
Features
•
•
•
•
•
•
1
12
8 Reference
N/C 2
7 N/C
N/C 3
6 Anode
N/C 4
5 N/C
(Top View)
8
Cathode 1
8
2
7
3
6
N/C 4
5
1
SOIC−8
D SUFFIX
CASE 751
Anode
Reference
Anode
N/C
(Top View)
This is an internally modified SOIC−8 package. Pins 2, 3, 6 and
7 are electrically common to the die attach flag. This internal
lead frame modification increases power dissipation capability
when appropriately mounted on a printed circuit board. This
modified package conforms to all external dimensions of the
standard SOIC−8 package.
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 1995
April, 2022 − Rev. 43
1
Publication Order Number:
TL431/D
TL431A, B Series, NCV431A, B Series, SCV431A
Cathode
(K)
Cathode (K)
Reference
(R)
800
800
Reference
(R)
Anode
(A)
20 pF
Figure 1. Symbol
Reference
(R)
Cathode
(K)
+
150
3.28 k
4.0 k
20 pF
2.4 k
-
10 k
7.2 k
2.5 Vref
1.0 k
Anode (A)
800
Figure 2. Representative Block Diagram
This device contains 12 active transistors.
Anode (A)
Figure 3. Representative Schematic Diagram
Component values are nominal
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.)
Rating
Symbol
Value
Unit
VKA
37
V
Cathode Current Range, Continuous
IK
−100 to +150
mA
Reference Input Current Range, Continuous
Iref
−0.05 to +10
mA
Operating Junction Temperature
TJ
150
°C
Operating Ambient Temperature Range
TA
Cathode to Anode Voltage
TL431I, TL431AI, TL431BI
°C
−40 to +85
TL431C, TL431AC, TL431BC
0 to +70
NCV431AI, NCV431B, TL431BV, SCV431AI
−40 to +125
Storage Temperature Range
Tstg
Total Power Dissipation @ TA = 25°C
PD
−65 to +150
°C
W
Derate above 25°C Ambient Temperature
D, LP Suffix Plastic Package
0.70
P Suffix Plastic Package
1.10
DM Suffix Plastic Package
0.52
Total Power Dissipation @ TC = 25°C
PD
W
Derate above 25°C Case Temperature
D, LP Suffix Plastic Package
1.5
P Suffix Plastic Package
3.0
ESD Rating (Note 1)
Human Body Model per JEDEC JESD22−A114F
Machine Model per JEDEC JESD22−A115C
Charged Device Model per JEDEC JESD22−C101E
V
HBM
MM
CDM
>2000
>200
>500
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch−up protection and exceeds ±100 mA per JEDEC standard JESD78.
RECOMMENDED OPERATING CONDITIONS
Condition
Cathode to Anode Voltage
Cathode Current
Symbol
Min
Max
Unit
VKA
Vref
36
V
IK
1.0
100
mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
TL431A, B Series, NCV431A, B Series, SCV431A
THERMAL CHARACTERISTICS
Symbol
D, LP Suffix
Package
P Suffix
Package
DM Suffix
Package
Unit
Thermal Resistance, Junction−to−Ambient
RqJA
178
114
240
°C/W
Thermal Resistance, Junction−to−Case
RqJC
83
41
−
°C/W
Characteristic
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
TL431I
Characteristic
Min
Symbol
Reference Input Voltage (Figure 1)
VKA = Vref, IK = 10 mA
TA = 25°C
TA = Tlow to Thigh (Note 2)
TL431C
Typ
Max
Min
Typ
Max
Vref
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 3, 4)
VKA= Vref, IK = 10 mA
V
2.44
2.41
2.495
−
2.55
2.58
2.44
2.423
2.495
−
2.55
2.567
−
7.0
30
−
3.0
17
DVref
Ratio of Change in Reference Input Voltage to Change
in Cathode to Anode Voltage
IK = 10 mA (Figure 2),
DVKA = 10 V to Vref
DVKA = 36 V to 10 V
DV
DV
Reference Input Current (Figure 2)
IK = 10 mA, R1 = 10 k, R2 = ∞
TA = 25°C
TA = Tlow to Thigh (Note 2)
Unit
mV
mV/V
ref
KA
−
−
−1.4
−1.0
−2.7
−2.0
−
−
−1.4
−1.0
−2.7
−2.0
Iref
mA
−
−
1.8
−
4.0
6.5
−
−
1.8
−
4.0
5.2
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 3)
IK = 10 mA, R1 = 10 k, R2 = ∞
DIref
−
0.8
2.5
−
0.4
1.2
mA
Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)
Imin
−
0.5
1.0
−
0.5
1.0
mA
Off−State Cathode Current (Figure 3)
VKA = 36 V, Vref = 0 V
Ioff
−
20
1000
−
20
1000
nA
|ZKA|
−
0.22
0.5
−
0.22
0.5
W
Dynamic Impedance (Figure 1, Note 5)
VKA = Vref, DIK = 1.0 mA to 100 mA, f ≤ 1.0 kHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Tlow = −40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM;
= 0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM
Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM,
TL431BCDM
3. Guaranteed by design.
4. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating
ambient temperature range that applies.
Vref max
DVref = Vref max
-Vref min
DTA = T2 - T1
Vref min
T1
Ambient Temperature
T2
The average temperature coefficient of the reference input voltage, aVref is defined as:
ppm
V
+
ref _C
ǒ
Ǔ
DV
V
ref
ref
@ 25_C
DT
A
X 106
+
x 10 6
ref
D T (V @ 25_C)
A ref
DV
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example : DV
V
ref
+ 8.0 mV and slope is positive,
@ 25_C + 2.495 V, DT + 70_C
ref
A
aV
ref
+
0.008 x 106
+ 45.8 ppmń_C
70 (2.495)
DV
KA
5. The dynamic impedance ZKA is defined as: |Z KA| +
. When the device is programmed with two external resistors, R1 and R2,
DI
K
ǒ
(refer to Figure 2) the total dynamic impedance of the circuit is defined as: |Z KAȀ| [ |Z KA| 1 ) R1
R2
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3
Ǔ
TL431A, B Series, NCV431A, B Series, SCV431A
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)
TL431AI /
NCV431AI/
SCV431AI
Characteristic
Symbol
Reference Input Voltage (Figure 1)
VKA = Vref, IK = 10 mA
TA = 25°C
TA = Tlow to Thigh (Note 6)
Min
Typ
TL431BC / TL431BI /
TL431BV /
NCV431BV
TL431AC
Max
Min
Typ
Max
Min
Typ
Max
Vref
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 7, 8)
VKA= Vref, IK = 10 mA
DVref
Ratio of Change in Reference Input Voltage to
Change in Cathode to Anode Voltage
IK = 10 mA (Figure 2),
DVKA = 10 V to Vref
DVKA = 36 V to 10 V
DV
DV
Reference Input Current (Figure 2)
IK = 10 mA, R1 = 10 k, R2 = ∞
TA = 25°C
TA = Tlow to Thigh (Note 6)
V
2.47
2.44
2.495
−
2.52
2.55
2.47
2.453
2.495
−
2.52
2.537
2.485
2.475
2.495
2.495
2.505
2.515
−
7.0
30
−
3.0
17
−
3.0
17
mV
mV/V
ref
KA
Unit
−
−
−1.4
−1.0
−2.7
−2.0
−
−
−1.4
−1.0
−2.7
−2.0
−
−
−1.4
−1.0
−2.7
−2.0
Iref
mA
−
−
1.8
−
4.0
6.5
−
−
1.8
−
4.0
5.2
−
−
1.1
−
2.0
4.0
Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 7)
IK = 10 mA, R1 = 10 k, R2 = ∞
DIref
−
0.8
2.5
−
0.4
1.2
−
0.8
2.5
mA
Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)
Imin
−
0.5
1.0
−
0.5
1.0
−
0.5
1.0
mA
Off−State Cathode Current (Figure 3)
VKA = 36 V, Vref = 0 V
Ioff
−
20
1000
−
20
1000
−
0.23
500
nA
|ZKA|
−
0.22
0.5
−
0.22
0.5
−
0.14
0.3
W
Dynamic Impedance (Figure 1, Note 9)
VKA = Vref, DIK = 1.0 mA to 100 mA
f ≤ 1.0 kHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Tlow = −40°C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431BV, TL431AIDM, TL431IDM,
TL431BIDM, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDR2G, SCV431AIDMR2G
= 0°C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM,
TL431ACDM, TL431BCDM, SCV431AIDMR2G
Thigh = +85°C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM
= +70°C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM,
TL431BCDM
= +125°C TL431BV, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G, SCV431AIDMR2G
7. Guaranteed by design.
8. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating
ambient temperature range that applies.
Vref max
DVref = Vref max
-Vref min
DTA = T2 - T1
Vref min
T1
Ambient Temperature
T2
The average temperature coefficient of the reference input voltage, aVref is defined as:
ppm
V
+
ref _C
ǒ
Ǔ
DV
V
ref
ref
@ 25_C
DT
A
X 106
+
x 10 6
ref
D T (V @ 25_C)
A ref
DV
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.)
Example : DV
V
ref
+ 8.0 mV and slope is positive,
@ 25_C + 2.495 V, DT + 70_C
ref
A
aV
ref
+
0.008 x 106
+ 45.8 ppmń_C
70 (2.495)
DV
KA
9. The dynamic impedance ZKA is defined as |Z KA| +
When the device is programmed with two external resistors, R1 and R2, (refer
DI
K
ǒ
Ǔ
to Figure 2) the total dynamic impedance of the circuit is defined as: |Z KAȀ| [ |Z KA| 1 ) R1
R2
10. NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G, SCV431AIDMR2G Tlow = −40°C, Thigh = +125°C.
NCV prefix is for automotive and other applications requiring unique site and control change requirements.
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4
TL431A, B Series, NCV431A, B Series, SCV431A
Input
Input
VKA
IK
VKA
Iref
R1
Vref
Input
Ioff
IK
R2
V
KA
+V
ǒ
VKA
Ǔ
1 ) R1 ) I SR1
ref
R2
ref
Vref
Figure 1. Test Circuit for VKA = Vref
Figure 2. Test Circuit for VKA > Vref
800
VKA = Vref
TA = 25°C
100
Input
IK
IK , CATHODE CURRENT ( μA)
IK , CATHODE CURRENT (mA)
150
Figure 3. Test Circuit for Ioff
VKA
50
0
-50
-100
-2.0
-1.0
0
1.0
2.0
VKA = Vref
TA = 25°C
600 Input
400
200
0
-200
-1.0
3.0
0
Vref , REFERENCE INPUT VOLTAGE (mV)
VKA
IK VKA = Vref
IK = 10 mA
Input
2560
Vref
Vref Max = 2550 mV
2540
2520
Vref Typ = 2495 mV
2500
2480
2460
2440
Vref Min = 2440 mV
2420
2400
-55
-25
0
25
50
2.0
3.0
Figure 5. Cathode Current versus
Cathode Voltage
Iref , REFERENCE INPUT CURRENT ( μA)
Figure 4. Cathode Current versus
Cathode Voltage
2580
1.0
VKA, CATHODE VOLTAGE (V)
VKA, CATHODE VOLTAGE (V)
2600
IMin
VKA
IK
75
100
125
3.0
2.5
2.0
1.5
IK = 10 mA
1.0
VKA
Input
10k Iref
IK
0.5
0
-55
-25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Reference Input Voltage versus
Ambient Temperature
Figure 7. Reference Input Current versus
Ambient Temperature
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5
125
0
IK = 10 mA
TA = 25°C
-8.0
-16
Input
VKA
IK
R1
-24
-32
R2
Vref
0
10
30
20
1.0 k
Ioff , OFF-STATE CATHODE CURRENT (nA)
Δ Vref , REFERENCE INPUT VOLTAGE (mV)
TL431A, B Series, NCV431A, B Series, SCV431A
100
10
1.0
Input
0.01
-55
40
-25
+
-
GND
1.0
0.1
1.0 k
10 k
100 k
1.0 M
0.280
0.260
75
100
125
0.240
0.220
0.200
-55
10 M
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
Figure 10. Dynamic Impedance
versus Frequency
Figure 11. Dynamic Impedance
versus Ambient Temperature
80
60
50
9.0 mF
40
Output
IK
15k
230
NOISE VOLTAGE (nV/ √Hz)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
50
VKA = Vref
D IK = 1.0 mA to 100 mA
f ≤ 1.0 kHz
Output
1.0k
IK
50 +
GND
0.300
f, FREQUENCY (MHz)
8.25k
GND
30
20
10
25
0.320
TA = 25°C
D IK = 1.0 mA to 100 mA
|ZKA|, DYNAMIC IMPEDANCE (Ω )
|ZKA|, DYNAMIC IMPEDANCE (Ω )
10
0
Figure 9. Off−State Cathode Current
versus Ambient Temperature
100
50
VKA
TA, AMBIENT TEMPERATURE (5C)
Figure 8. Change in Reference Input
Voltage versus Cathode Voltage
Output
IK
Ioff
0.1
VKA, CATHODE VOLTAGE (V)
1.0 k
VKA = 36 V
Vref = 0 V
IK = 10 mA
TA = 25°C
60
VKA = Vref
IK = 10 mA
TA = 25°C
40
Input
20
Output
IK
0
-10
1.0 k
10 k
100 k
1.0 M
0
10
10 M
100
1.0 k
10 k
f, FREQUENCY (Hz)
f, FREQUENCY (MHz)
Figure 12. Open−Loop Voltage Gain
versus Frequency
Figure 13. Spectral Noise Density
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6
100 k
TL431A, B Series, NCV431A, B Series, SCV431A
Input
Monitor
Output
2.0
220 Output
Pulse
Generator
f = 100 kHz
1.0
50
GND
0
5.0
Input
0
0
4.0
12
8.0
16
Unstable
Area
A
B
C
D
120
I K, CATHODE CURRENT (mA)
VOLTAGE SWING (V)
140
TA = 25°C
3.0
100
TA = 25°C
C
80
60
Stable
40
Stable
D
B
B
A
20
0
1.0 nF
20
Programmed
VKA(V)
Vref
5.0
10
15
10 nF
t, TIME (ms)
A
100 nF
1.0 mF
10 mF
100 mF
CL, LOAD CAPACITANCE
Figure 14. Pulse Response
Figure 15. Stability Boundary Conditions
150
150
IK
IK
V+
10 k
V+
CL
Figure 16. Test Circuit For Curve A
of Stability Boundary Conditions
CL
Figure 17. Test Circuit For Curves B, C, And D
of Stability Boundary Conditions
TYPICAL APPLICATIONS
V+
V+
Vout
Vout
R1
R1
R2
R2
ǒ
Ǔ
V out + 1 ) R1 V
R2 ref
ǒ
Ǔ
V out + 1 ) R1 V
R2 ref
Figure 18. Shunt Regulator
Figure 19. High Current Shunt Regulator
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TL431A, B Series, NCV431A, B Series, SCV431A
V+
V+
MC7805
Out
In
Common
Vout
R1
Vout
R1
R2
R2
ǒ
V
out(min)
+V
ref
V
) 5.0V
Figure 20. Output Control for a
Three−Terminal Fixed Regulator
RCL
V+
Ǔ
V out + 1 ) R1 V
R2 ref
V out + ǒ1 ) R1ǓV
R2 ref
in(min)
+ V out ) V
V
+V
out(min)
be
ref
Figure 21. Series Pass Regulator
V+
Iout
Isink
I
V
I out + ref
R
CL
Sink
V
+ ref
R
S
RS
Figure 22. Constant Current Source
V+
Figure 23. Constant Current Sink
V+
Vout
Vout
R1
R1
R2
ǒ
R2
Ǔ
V
+ 1 ) R1 V
out(trip)
R2 ref
V
Figure 24. TRIAC Crowbar
out(trip)
ǒ
Ǔ
+ 1 ) R1 V
R2 ref
Figure 25. SRC Crowbar
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TL431A, B Series, NCV431A, B Series, SCV431A
V+
Vout
l
R1
V+
R3
Vout
Vin
R2
R4
Vin
Vth = Vref
L.E.D. indicator is `on' when V+ is between the
upper and lower limits.
ǒ Ǔ
UpperLimit + ǒ1 ) R3ǓV
R4 ref
LowerLimit + 1 ) R1 V
R2 ref
Figure 26. Voltage Monitor
5.0 k
1%
50 k
1%
10 kW
V
500 k
1%
5.0 M
1%
100 kW
1.0 MW
V
V
Range
1.0 kW
V
RX
V+
> Vref
≈ 2.0 V
Figure 27. Single−Supply Comparator with
Temperature−Compensated Threshold
25 V
1N5305
Vout
< Vref
38 V
2.0 mA
TI
10 k
Calibrate
25 V
LM11
+
330
Tl = 330 to 8.0 W
8.0 W
+
470 mF
360 k
1.0 mF
*
Vout
* Thermalloy
* THM 6024
* Heatsink on
* LP Package
-5.0 V
W
R x + V outD Range
V
Figure 28. Linear Ohmmeter
56 k
10 k
0.05 mF
Tone
25 k
Volume
47 k
Figure 29. Simple 400 mW Phono Amplifier
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TL431A, B Series, NCV431A, B Series, SCV431A
150 mH @ 2.0 A
Vin = 10 V to 20 V
TIP115
Vout = 5.0 V
Iout = 1.0 A
1.0 k
4.7 k
+
4.7 k
MPSA20
2200 mF
1N5823
100 k
0.01mF
470 mF
4.7 k
0.1 mF
2.2 k
10
51 k
Figure 30. High Efficiency Step−Down Switching Converter
Test
Conditions
Results
Line Regulation
Vin = 10 V to 20 V, Io = 1.0 A
53 mV (1.1%)
Load Regulation
Vin = 15 V, Io = 0 A to 1.0 A
25 mV (0.5%)
Output Ripple
Vin = 10 V, Io = 1.0 A
50 mVpp P.A.R.D.
Output Ripple
Vin = 20 V, Io = 1.0 A
100 mVpp P.A.R.D.
Efficiency
Vin = 15 V, Io = 1.0 A
82%
www.onsemi.com
10
+
TL431A, B Series, NCV431A, B Series, SCV431A
APPLICATIONS INFORMATION
The TL431 is a programmable precision reference which
is used in a variety of ways. It serves as a reference voltage
in circuits where a non−standard reference voltage is
needed. Other uses include feedback control for driving an
optocoupler in power supplies, voltage monitor, constant
current source, constant current sink and series pass
regulator. In each of these applications, it is critical to
maintain stability of the device at various operating currents
and load capacitances. In some cases the circuit designer can
estimate the stabilization capacitance from the stability
boundary conditions curve provided in Figure 15. However,
these typical curves only provide stability information at
specific cathode voltages and at a specific load condition.
Additional information is needed to determine the
capacitance needed to optimize phase margin or allow for
process variation.
A simplified model of the TL431 is shown in Figure 31.
When tested for stability boundaries, the load resistance is
150 W. The model reference input consists of an input
transistor and a dc emitter resistance connected to the device
anode. A dependent current source, Gm, develops a current
whose amplitude is determined by the difference between
the 1.78 V internal reference voltage source and the input
transistor emitter voltage. A portion of Gm flows through
compensation capacitance, CP2. The voltage across CP2
drives the output dependent current source, Go, which is
connected across the device cathode and anode.
P2 +
Z1 +
C
P1
+
1
+ 60 kHz
2p * 10 M * 0.265 pF
1
1
+
+ 500 kHz
2p * 15.9 k * 20 pF
C
Z1 P1
Example 1:
G+G R
GoR
M GM
L
I + 10 mA, R + 230 W, C + 0. Define the transfer gain.
L
L
C
The DC gain is:
G+G R
GoR +
M GM
L
(2.138)(1.0 M)(1.25 m)(230) + 615 + 56 dB
Loop gain + G
8.25 k
+ 218 + 47 dB
8.25 k ) 15 k
The resulting transfer function Bode plot is shown in
Figure 32. The asymptotic plot may be expressed as the
following equation:
ǒ1 ) 500jfkHzǓ
Av + 615
ǒ1 ) 8.0jfkHzǓǒ1 ) 60 jfkHzǓ
Resistor and capacitor typical values are shown on the
model. Process tolerances are ± 20% for resistors, ±10% for
capacitors, and ±40% for transconductances.
An examination of the device model reveals the location
of circuit poles and zeroes:
1
2p R
+
Also, the transfer dc voltage gain of the TL431 is:
Go = 1.25 (Vcp2) mmhos.
GM
C
P2 P2
1
P +
L
2p R C
L L
where IC is the device cathode current and Gm is in mhos
2p R
1
In addition, there is an external circuit pole defined by the
load:
Model component values are:
Vref = 1.78 V
Gm = 0.3 + 2.7 exp (−IC/26 mA)
P1 +
2p R
The Bode plot shows a unity gain crossover frequency of
approximately 600 kHz. The phase margin, calculated from
the equation, would be 55.9 degrees. This model matches the
Open−Loop Bode Plot of Figure 12. The total loop would
have a unity gain frequency of about 300 kHz with a phase
margin of about 44 degrees.
1
+ 7.96 kHz
2p * 1.0 M * 20 pF
www.onsemi.com
11
TL431A, B Series, NCV431A, B Series, SCV431A
VCC
RL
CL
Input
3
15 k
Cathode
9.0 mF
Ref
RP2
10 M
Vref
1.78 V
1
500 k
CP1
20 pF
GM
+
-
Rref
RGM
1.0 M
16
RZ1
15.9 k
8.25 k
Anode
Go
1.0 mmho
CP2
0.265 pF
2
Figure 31. Simplified TL431 Device Model
Note that the transfer function now has an extra pole
formed by the load capacitance and load resistance.
Note that the crossover frequency in this case is about
250 kHz, having a phase margin of about −46 degrees.
Therefore, instability of this circuit is likely.
TL431 OPEN-LOOP VOLTAGE GAIN VERSUS FREQUENCY
50
40
30
TL431 OPEN-LOOP BODE PLOT WITH LOAD CAP
20
80
10
Av, OPEN-LOOP GAIN (dB)
Av, OPEN-LOOP VOLTAGE GAIN (dB)
60
0
-10
-20
101
102
103
104
105
106
107
f, FREQUENCY (Hz)
Figure 32. Example 1 Circuit Open Loop Gain Plot
Example 2.
IC = 7.5 mA, RL = 2.2 kW, CL = 0.01 mF. Cathode tied to
reference input pin. An examination of the data sheet
stability boundary curve (Figure 15) shows that this value of
load capacitance and cathode current is on the boundary.
Define the transfer gain.
The DC gain is:
60
40
20
0
-20
101
102
103
104
105
106
f, FREQUENCY (Hz)
Figure 33. Example 2 Circuit Open Loop Gain Plot
With three poles, this system is unstable. The only hope
for stabilizing this circuit is to add a zero. However, that can
only be done by adding a series resistance to the output
capacitance, which will reduce its effectiveness as a noise
filter. Therefore, practically, in reference voltage
applications, the best solution appears to be to use a smaller
value of capacitance in low noise applications or a very
large value to provide noise filtering and a dominant pole
rolloff of the system.
G+G R
GoR +
M GM
L
(2.323)(1.0 M)(1.25 m)(2200) + 6389 + 76 dB
The resulting open loop Bode plot is shown in Figure 33.
The asymptotic plot may be expressed as the following
equation:
ǒ1 ) 500jfkHzǓ
Av + 615
ǒ1 ) 8.0jfkHzǓǒ1 ) 60 jfkHzǓǒ1 ) 7.2jfkHzǓ
www.onsemi.com
12
TL431A, B Series, NCV431A, B Series, SCV431A
ORDERING INFORMATION
Device
Marking
Code
TL431ACDG
AC
TL431BCDG
BC
TL431CDG
AC
TL431BCDR2G
BC
TAC
TL431BCDMR2G
TBC
TL431CDMR2G
T−C
TL431ACPG
ACP
TL431BCPG
BCP
ACLP
TL431BCLPG
BCLP
Tolerance
1.0%
98 Units / Rail
0.4%
2.2%
SOIC−8
(Pb−Free)
1.0%
2500 / Tape & Reel
0.4%
2.2%
Micro8
(Pb−Free)
PDIP−8
(Pb−Free)
CP
TL431ACLPG
TL431CLPG
Shipping Information†
C
TL431ACDMR2G
TL431CPG
Package Code
C
TL431ACDR2G
TL431CDR2G
Operating Temperature Range
1.0%
4000 / Tape & Reel
0.4%
2.2%
1.0%
50 Units / Rail
0.4%
2.2%
1.0%
0°C to 70°C
2000 Units / Bag
0.4%
CLP
2.2%
TL431ACLPRAG
ACLP
1.0%
TL431BCLPRAG
BCLP
0.4%
TL431CLPRAG
CLP
TL431ACLPREG
ACLP
TL431BCLPREG
BCLP
TL431CLPREG
ACLP
TL431BCLPRMG
BCLP
TL431CLPRMG
CLP
TL431CLPRPG
CLP
TL431AIDG
AI
TL431BIDG
BI
AI
TL431BIDR2G
BI
TAI
TL431BIDMR2G
TBI
TL431IDMR2G
T−I
TL431AIPG
AIP
TL431BIPG
BIP
TL431IPG
IP
TL431AILPG
AILP
TL431BILPG
BILP
TL431ILPG
1.0%
2.2%
1.0%
0.4%
2000 / Fan−Fold
2.2%
1.0%
98 Units / Rail
0.4%
2.2%
SOIC−8
(Pb−Free)
1.0%
2500s / Tape & Reel
I
TL431AIDMR2G
2.2%
0.4%
2000 / Tape & Ammo Box
I
TL431AIDR2G
TL431IDR2G
2000 / Tape & Reel
CLP
TL431ACLPRPG
TL431IDG
TO−92
(Pb−Free)
0.4%
2.2%
Micro8
(Pb−Free)
PDIP−8
(Pb−Free)
−40°C to 85°C
1.0%
4000 / Tape & Reel
0.4%
2.2%
1.0%
50 Units / Rail
0.4%
2.2%
1.0%
2000 Units / Bag
0.4%
ILP
2.2%
TL431AILPRAG
AILP
1.0%
TL431BILPRAG
BILP
SC431ILPRAG
ILP
TL431ILPRAG
ILP
TL431AILPRMG
TL431AILPRPG
TL431ILPRPG
TO−92
(Pb−Free)
AILP
2000 / Tape & Reel
2.2%
2000 / Tape & Ammo Box
ILP
0.4%
1.0%
2.2%
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV/SCV Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified
and PPAP Capable.
www.onsemi.com
13
TL431A, B Series, NCV431A, B Series, SCV431A
ORDERING INFORMATION
Device
TL431BVDG
TL431BVDR2G
TL431BVDMR2G
TL431BVLPG
TL431BVLPRAG
TL431BVPG
Marking
Code
TBV
Micro8
(Pb−Free)
BVLP
TO−92
(Pb−Free)
BVP
PDIP−8
(Pb−Free)
50 Units / Rail
Micro8
(Pb−Free)
4000 / Tape & Reel
AV
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NVB
Micro8
(Pb−Free)
4000 / Tape & Reel
BV
SOIC−8
(Pb−Free)
2500 / Tape & Reel
RAN
RAP
NCV431BVDR2G*
Shipping Information†
98 Units / Rail
SOIC−8
(Pb−Free)
SCV431AIDMR2G*
NCV431BVDMR2G*
Package Code
BV
NCV431AIDMR2G*
NCV431AIDR2G*
Operating Temperature Range
−40°C to 125°C
Tolerance
2500 / Tape & Reel
4000 / Tape & Reel
0.4%
2000 Units / Bag
2000 / Tape & Reel
0.4%
1%
0.4%
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV/SCV Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified
and PPAP Capable.
MARKING DIAGRAMS
SOIC−8
D SUFFIX
CASE 751
8
Micro8
CASE 846A
PDIP−8
CASE 626
8
8
431xx
ALYW
G
1
TL431xxx
AWL
YYWWG
xxx
AYWG
G
1
8
TL431
ALYWx
G
1
(Exception for the TL431CD
and TL431ID only)
TO−92 (TO−226)
CASE 29
1
xxxx
= See Specific Marking Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
www.onsemi.com
14
TL431
xxxx
ALYW
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
SCALE 1:1
12
3
STRAIGHT LEAD
1
DATE 05 MAR 2021
2
3
BENT LEAD
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLE 1:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 2:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 6:
PIN 1. GATE
2. SOURCE & SUBSTRATE
3. DRAIN
STYLE 7:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 8:
PIN 1. DRAIN
2. GATE
3. SOURCE & SUBSTRATE
STYLE 9:
PIN 1. BASE 1
2. EMITTER
3. BASE 2
STYLE 10:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 11:
PIN 1. ANODE
2. CATHODE & ANODE
3. CATHODE
STYLE 12:
PIN 1. MAIN TERMINAL 1
2. GATE
3. MAIN TERMINAL 2
STYLE 13:
PIN 1. ANODE 1
2. GATE
3. CATHODE 2
STYLE 14:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
STYLE 15:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
STYLE 16:
PIN 1. ANODE
2. GATE
3. CATHODE
STYLE 17:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
STYLE 18:
PIN 1. ANODE
2. CATHODE
3. NOT CONNECTED
STYLE 19:
PIN 1. GATE
2. ANODE
3. CATHODE
STYLE 20:
PIN 1. NOT CONNECTED
2. CATHODE
3. ANODE
STYLE 21:
PIN 1. COLLECTOR
2. EMITTER
3. BASE
STYLE 22:
PIN 1. SOURCE
2. GATE
3. DRAIN
STYLE 23:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 24:
PIN 1. EMITTER
2. COLLECTOR/ANODE
3. CATHODE
STYLE 25:
PIN 1. MT 1
2. GATE
3. MT 2
STYLE 26:
PIN 1.
2.
3.
STYLE 27:
PIN 1. MT
2. SUBSTRATE
3. MT
STYLE 28:
PIN 1. CATHODE
2. ANODE
3. GATE
STYLE 29:
PIN 1. NOT CONNECTED
2. ANODE
3. CATHODE
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
STYLE 32:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
STYLE 33:
PIN 1. RETURN
2. INPUT
3. OUTPUT
STYLE 34:
PIN 1. INPUT
2. GROUND
3. LOGIC
STYLE 35:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
VCC
GROUND 2
OUTPUT
STYLE 31:
PIN 1. GATE
2. DRAIN
3. SOURCE
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 3 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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