DATA SHEET
www.onsemi.com
Switch mode Pulse Width
Modulation Control Circuit
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
TL494, NCV494
TL494xDG
AWLYWW
1
The TL494 is a fixed frequency, pulse width modulation control
circuit designed primarily for switch mode power supply control.
16
PDIP−16
*
N SUFFIX
CASE 648
1
Features
•
•
•
•
•
•
•
•
•
•
Complete Pulse Width Modulation Control Circuitry
On−Chip Oscillator with Master or Slave Operation
On−Chip Error Amplifiers
On−Chip 5.0 V Reference
Adjustable Deadtime Control
Uncommitted Output Transistors Rated to 500 mA Source or Sink
Output Control for Push−Pull or Single−Ended Operation
Undervoltage Lockout
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
Pb−Free Packages are Available*
x
A
WL
YY, Y
WW, W
G
TL494xN
AWLYYWWG
= B, C or I
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This marking diagram also applies to NCV494.
PIN CONNECTIONS
MAXIMUM RATINGS (Full operating ambient temperature range applies,
unless otherwise noted.)
Rating
Noninv
Input 1
Inv
Input 2
Symbol
Value
Unit
Power Supply Voltage
VCC
42
V
Collector Output Voltage
VC1,
VC2
42
V
Collector Output Current
(Each transistor) (Note 1)
IC1, IC2
500
mA
CT 5
Amplifier Input Voltage Range
VIR
−0.3 to +42
V
RT 6
Power Dissipation @ TA ≤ 45°C
PD
1000
mW
Thermal Resistance, Junction−to−Ambient
Compen/PWN
Comp Input 3
Deadtime
Control 4
+
Error 1
Amp
-
+
2 Error
Amp
VCC
5.0 V
REF
≈ 0.1 V
Noninv
16 Input
Inv
15 Input
14 Vref
Output
13 Contro
l
12 VCC
Oscillator
RqJA
80
°C/W
Operating Junction Temperature
TJ
125
°C
Storage Temperature Range
Tstg
−55 to +125
°C
Operating Ambient Temperature Range
TL494B
TL494C
TL494I
NCV494B
TA
Derating Ambient Temperature
TA
−40 to +125
0 to +70
−40 to +85
−40 to +125
45
11 C2
Q2
Ground 7
C1 8
10 E2
Q1
9 E1
(Top View)
°C
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Maximum thermal limits must be observed.
*For additional information on our Pb−Free strategy and soldering details, please
download the onsemi Soldering and Mounting Techniques Reference Manual,
SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
August, 2021 − Rev. 7
1
Publication Order Number:
TL494/D
TL494, NCV494
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
VCC
7.0
15
40
V
VC1, VC2
−
30
40
V
IC1, IC2
−
−
200
mA
Amplified Input Voltage
Vin
−0.3
−
VCC − 2.0
V
Current Into Feedback Terminal
lfb
−
−
0.3
mA
Power Supply Voltage
Collector Output Voltage
Collector Output Current (Each transistor)
Reference Output Current
lref
−
−
10
mA
Timing Resistor
RT
1.8
30
500
kW
Timing Capacitor
CT
0.0047
0.001
10
mF
Oscillator Frequency
fosc
1.0
40
200
kHz
ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.)
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.
Characteristics
Symbol
Min
Typ
Max
Unit
Vref
4.75
5.0
5.25
V
Line Regulation (VCC = 7.0 V to 40 V)
Regline
−
2.0
25
mV
Load Regulation (IO = 1.0 mA to 10 mA)
Regload
−
3.0
15
mV
Short Circuit Output Current (Vref = 0 V)
ISC
15
35
75
mA
Collector Off−State Current
(VCC = 40 V, VCE = 40 V)
IC(off)
−
2.0
100
mA
Emitter Off−State Current
VCC = 40 V, VC = 40 V, VE = 0 V)
IE(off)
−
−
−100
mA
Vsat(C)
Vsat(E)
−
−
1.1
1.5
1.3
2.5
IOCL
IOCH
−
−
10
0.2
−
3.5
−
−
100
100
200
200
−
−
25
40
100
100
REFERENCE SECTION
Reference Voltage (IO = 1.0 mA)
OUTPUT SECTION
Collector−Emitter Saturation Voltage (Note 2)
Common−Emitter (VE = 0 V, IC = 200 mA)
Emitter−Follower (VC = 15 V, IE = −200 mA)
V
Output Control Pin Current
Low State (VOC v 0.4 V)
High State (VOC = Vref)
Output Voltage Rise Time
Common−Emitter (See Figure 12)
Emitter−Follower (See Figure 13)
tr
Output Voltage Fall Time
Common−Emitter (See Figure 12)
Emitter−Follower (See Figure 13)
tf
mA
mA
ns
ns
2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
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2
TL494, NCV494
ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.)
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.
Characteristics
Symbol
Min
Typ
Max
Unit
ERROR AMPLIFIER SECTION
Input Offset Voltage (VO (Pin 3) = 2.5 V)
VIO
−
2.0
10
mV
Input Offset Current (VO (Pin 3) = 2.5 V)
IIO
−
5.0
250
nA
Input Bias Current (VO (Pin 3) = 2.5 V)
IIB
−
−0.1
−1.0
mA
Input Common Mode Voltage Range (VCC = 40 V, TA = 25°C)
VICR
Open Loop Voltage Gain (DVO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kW)
AVOL
70
95
−
dB
fC−
−
350
−
kHz
Unity−Gain Crossover Frequency (VO = 0.5 V to 3.5 V, RL = 2.0 kW)
−0.3 to VCC−2.0
V
fm
−
65
−
deg.
Common Mode Rejection Ratio (VCC = 40 V)
CMRR
65
90
−
dB
Power Supply Rejection Ratio (DVCC = 33 V, VO = 2.5 V, RL = 2.0 kW)
PSRR
−
100
−
dB
Output Sink Current (VO (Pin 3) = 0.7 V)
IO−
0.3
0.7
−
mA
Output Source Current (VO (Pin 3) = 3.5 V)
IO+
2.0
−4.0
−
mA
VTH
−
2.5
4.5
V
II−
0.3
0.7
−
mA
Input Bias Current (Pin 4) (VPin 4 = 0 V to 5.25 V)
IIB (DT)
−
−2.0
−10
mA
Maximum Duty Cycle, Each Output, Push−Pull Mode
(VPin 4 = 0 V, CT = 0.01 mF, RT = 12 kW)
(VPin 4 = 0 V, CT = 0.001 mF, RT = 30 kW)
DCmax
45
−
48
45
50
50
−
0
2.8
−
3.3
−
fosc
−
40
−
kHz
Phase Margin at Unity−Gain (VO = 0.5 V to 3.5 V, RL = 2.0 kW)
PWM COMPARATOR SECTION (Test Circuit Figure 11)
Input Threshold Voltage (Zero Duty Cycle)
Input Sink Current (V(Pin 3) = 0.7 V)
DEADTIME CONTROL SECTION (Test Circuit Figure 11)
Input Threshold Voltage (Pin 4)
(Zero Duty Cycle)
(Maximum Duty Cycle)
Vth
%
V
OSCILLATOR SECTION
Frequency (CT = 0.001 mF, RT = 30 kW)
sfosc
−
3.0
−
%
Frequency Change with Voltage (VCC = 7.0 V to 40 V, TA = 25°C)
Dfosc (DV)
−
0.1
−
%
Frequency Change with Temperature (DTA = Tlow to Thigh)
(CT = 0.01 mF, RT = 12 kW)
Dfosc (DT)
−
−
12
%
Vth
5.5
6.43
7.0
V
−
−
5.5
7.0
10
15
−
7.0
−
Standard Deviation of Frequency* (CT = 0.001 mF, RT = 30 kW)
UNDERVOLTAGE LOCKOUT SECTION
Turn−On Threshold (VCC increasing, Iref = 1.0 mA)
TOTAL DEVICE
Standby Supply Current (Pin 6 at Vref, All other inputs and outputs open)
(VCC = 15 V)
(VCC = 40 V)
Average Supply Current
(CT = 0.01 mF, RT = 12 kW, V(Pin 4) = 2.0 V)
(VCC = 15 V) (See Figure 12)
ICC
mA
mA
* Standard deviation is a measure of the statistical distribution about the mean as derived from the formula, s
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3
N
S (Xn − X)2
n=1
N−1
TL494, NCV494
ORDERING INFORMATION
Package
Shipping†
TL494BD
SOIC−16
48 Units / Rail
TL494BDG
SOIC−16
(Pb−Free)
48 Units / Rail
TL494BDR2
SOIC−16
2500 Tape & Reel
TL494BDR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
TL494CD
SOIC−16
48 Units / Rail
TL494CDG
SOIC−16
(Pb−Free)
48 Units / Rail
TL494CDR2
SOIC−16
2500 Tape & Reel
TL494CDR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
TL494CN
PDIP−16
25 Units / Rail
TL494CNG
PDIP−16
(Pb−Free)
25 Units / Rail
TL494IN
PDIP−16
25 Units / Rail
TL494ING
PDIP−16
(Pb−Free)
25 Units / Rail
NCV494BDR2*
SOIC−16
2500 Tape & Reel
NCV494BDR2G*
SOIC−16
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV494: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and change
control.
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4
TL494, NCV494
VCC
Output Control
13
8
6
D
Oscillator
RT
CT
5
-
0.12V
Q
Q1
Q
Q2 11
Deadtime
Comparator
Ck
+
4
Deadtime
Control
9
FlipFlop
10
0.7V
-
+
1
2
1
2
Error Amp
1
+
PWM
Comparator
0.7mA
12
-
+
3
UV
Lockout
+
-
3.5V
15
Feedback PWM
Comparator Input
Reference
Regulator
-
+
16
14
Error Amp
2
Ref.
Output
This device contains 46 active transistors.
Figure 1. Representative Block Diagram
Capacitor CT
Feedback/PWM Comp.
Deadtime Control
Flip-Flop
Clock Input
Flip-Flop
Q
Flip-Flop
Q
Output Q1
Emitter
Output Q2
Emitter
Output
Control
Figure 2. Timing Diagram
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5
VCC
4.9V
7
Gnd
TL494, NCV494
APPLICATIONS INFORMATION
Description
common mode input range from −0.3 V to (VCC − 2V), and
may be used to sense power−supply output voltage and
current. The error−amplifier outputs are active high and are
ORed together at the noninverting input of the pulse−width
modulator comparator. With this configuration, the
amplifier that demands minimum output on time, dominates
control of the loop.
When capacitor CT is discharged, a positive pulse is
generated on the output of the deadtime comparator, which
clocks the pulse−steering flip−flop and inhibits the output
transistors, Q1 and Q2. With the output−control connected
to the reference line, the pulse−steering flip−flop directs the
modulated pulses to each of the two output transistors
alternately for push−pull operation. The output frequency is
equal to half that of the oscillator. Output drive can also be
taken from Q1 or Q2, when single−ended operation with a
maximum on−time of less than 50% is required. This is
desirable when the output transformer has a ringback
winding with a catch diode used for snubbing. When higher
output−drive currents are required for single−ended
operation, Q1 and Q2 may be connected in parallel, and the
output−mode pin must be tied to ground to disable the
flip−flop. The output frequency will now be equal to that of
the oscillator.
The TL494 has an internal 5.0 V reference capable of
sourcing up to 10 mA of load current for external bias
circuits. The reference has an internal accuracy of $5.0%
with a typical thermal drift of less than 50 mV over an
operating temperature range of 0° to 70°C.
The TL494 is a fixed−frequency pulse width modulation
control circuit, incorporating the primary building blocks
required for the control of a switching power supply. (See
Figure 1.) An internal−linear sawtooth oscillator is
frequency− programmable by two external components, RT
and CT. The approximate oscillator frequency is determined
by:
fosc ≈
1.1
RT • CT
For more information refer to Figure 3.
Output pulse width modulation is accomplished by
comparison of the positive sawtooth waveform across
capacitor CT to either of two control signals. The NOR gates,
which drive output transistors Q1 and Q2, are enabled only
when the flip−flop clock−input line is in its low state. This
happens only during that portion of time when the sawtooth
voltage is greater than the control signals. Therefore, an
increase in control−signal amplitude causes a corresponding
linear decrease of output pulse width. (Refer to the Timing
Diagram shown in Figure 2.)
The control signals are external inputs that can be fed into
the deadtime control, the error amplifier inputs, or the
feedback input. The deadtime control comparator has an
effective 120 mV input offset which limits the minimum
output deadtime to approximately the first 4% of the
sawtooth−cycle time. This would result in a maximum duty
cycle on a given output of 96% with the output control
grounded, and 48% with it connected to the reference line.
Additional deadtime may be imposed on the output by
setting the deadtime−control input to a fixed voltage,
ranging between 0 V to 3.3 V.
fosc , OSCILLATOR FREQUENCY (Hz)
500 k
Functional Table
Input/Output
Controls
Output Function
fout
fosc =
Grounded
Single−ended PWM @ Q1 and Q2
1.0
Push−pull Operation
0.5
@ Vref
CT = 0.001 mF
100 k
0.01 mF
10 k
0.1 mF
1.0 k
500
1.0 k 2.0 k 5.0 k
The pulse width modulator comparator provides a means
for the error amplifiers to adjust the output pulse width from
the maximum percent on−time, established by the deadtime
control input, down to zero, as the voltage at the feedback
pin varies from 0.5 V to 3.5 V. Both error amplifiers have a
VCC = 15 V
10 k 20 k 50 k
100 k 200 k
RT, TIMING RESISTANCE (W)
500 k 1.0 M
Figure 3. Oscillator Frequency versus
Timing Resistance
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6
VCC = 15 V
DVO = 3.0 V
RL = 2.0 kW
AVOL
10
100
1.0 k
10 k
f, FREQUENCY (Hz)
% DT, PERCENT DEADTIME (EACH OUTPUT)
120
110
100
90
80
70
60
50
40
30
20
10
0
1.0
φ , EXCESS PHASE (DEGREES)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
TL494, NCV494
0
20
40
60
80
φ
100
120
140
160
180
100 k
1.0 M
20
18
16
CT = 0.001 mF
14
12
10
8.0
6.0
0.001 mF
4.0
2.0
0
500 k 1.0 k
50
1.9
1
40
VCC = 15 V
VOC = Vref
1.CT = 0.01 mF
2.RT = 10 kW
2.CT = 0.001 mF
2.RT = 30 kW
2
30
20
10
0
0
1.0
2.0
3.0
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
3.5
0
100
VDT, DEADTIME CONTROL VOLTAGE (IV)
Figure 6. Percent Duty Cycle versus
Deadtime Control Voltage
200
300
IE, EMITTER CURRENT (mA)
400
Figure 7. Emitter−Follower Configuration
Output Saturation Voltage versus
Emitter Current
10
2.0
9.0
I CC , SUPPLY CURRENT (mA)
VCE(sat), SATURATION VOLTAGE (V)
500 k
Figure 5. Percent Deadtime versus
Oscillator Frequency
V CE(sat) , SATURATION VOLTAGE (V)
% DC, PERCENT DUTY CYCLE (EACH OUTPUT)
Figure 4. Open Loop Voltage Gain and
Phase versus Frequency
10 k
100 k
fosc, OSCILLATOR FREQUENCY (Hz)
1.6
1.4
1.2
1.8
1.0
0.8
0.6
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
0.4
0
100
200
300
IC, COLLECTOR CURRENT (mA)
0
400
5.0
10
15
20
25
30
35
VCC, SUPPLY VOLTAGE (V)
Figure 8. Common−Emitter Configuration
Output Saturation Voltage versus
Collector Current
Figure 9. Standby Supply Current
versus Supply Voltage
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7
40
TL494, NCV494
VCC = 15V
+
Vin
Error Amplifier
Under Test
Test
Inputs
Feedback
RT
CT
(+)
(-)
Error
(+)
(-)
Output
Control
Gnd
Feedback
Terminal
(Pin 3)
+
Vref
-
Other Error
Amplifier
50k
Figure 10. Error−Amplifier Characteristics
150
2W
150
2W
VCC
Deadtime
C1
E1
Output 1
C2
E2
Output 2
Ref
Out
Figure 11. Deadtime and Feedback Control Circuit
15V
15V
RL
68
C
Each
Output
Transistor
C
VC
Each
Output
Transistor
CL
15pF
Q
Q
VEE
E
RL
68
E
90%
VEE
90%
90%
90%
CL
15pF
VCC
10%
10%
tr
Gnd
10%
10%
tr
tf
tf
Figure 13. Emitter−Follower Configuration
Test Circuit and Waveform
Figure 12. Common−Emitter Configuration
Test Circuit and Waveform
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TL494, NCV494
VO
Vref
To Output
Voltage of
System
1
Vref
Error
Amp
+
-
R2
2
Error
Amp
3
R1
Negative Output Voltage
2
VO = Vref
Positive Output Voltage
R2
1
+
R1
R1
R2
VO
To Output
Voltage of
System
R1
R2
VO = Vref 1 +
Figure 14. Error−Amplifier Sensing Techniques
Output
Control
R1
Vref
Output
DT
Q
CT
RT
6
4
R2
5
DT
Q
0.001
30k
CS
Vref
Output
4
RS
80
Max. % on Time, each output ≈ 45 1 +
R1
R2
Figure 15. Deadtime Control Circuit
Figure 16. Soft−Start Circuit
C1
C1
QC
Q1
2.4 V ≤ VOC ≤ Vref
Q1
E1
Output
Control
Push-Pull
C2
0 ≤ VOC ≤ 0.4 V
Q2
E2
1.0 mA to
250 mA
Output
Control
1.0 mA to
500 mA
Single-Ended
E1
C2
Q2
QE
Figure 17. Output Connections for Single−Ended and Push−Pull Configurations
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9
E2
1.0 mA to
250 mA
TL494, NCV494
Vref
6
5
RT
RT
VCC
RS
Master
CT
12
Vin > 40V
CT
1N975A
VZ = 39V
5.0V
Ref
Vref
270
6
RT
5
Slave
(Additional
Circuits)
CT
Gnd
7
Figure 18. Slaving Two or More Control Circuits
Figure 19. Operation with Vin > 40 V Using
External Zener
+Vin = 8.0V to 20V
12
1
2
1M
33k
3
0.01 0.01
15
16
47
VCC
+
C1
-
Tip
32
TL494
Comp
-
C2
+
8
T1
OC VREF DT
13
14
4
CT
5
E1
RT Gnd
6
7
9
11
E2
Tip
32
22
k
L1
+
50
35V
4.7k
+
50
25V
47
1.0
1N4934
10
+
4.7k
4.7k
+VO = 28 V
IO = 0.2 A
1N4934
+
50
35V
240
10
10k
15k
0.001
All capacitors in mF
Figure 20. Pulse Width Modulated Push−Pull Converter
Test
Conditions
Results
Line Regulation
Vin = 10 V to 40 V
14 mV 0.28%
Load Regulation
Vin = 28 V, IO = 1.0 mA to 1.0 A
3.0 mV 0.06%
Output Ripple
Vin = 28 V, IO = 1.0 A
65 mV pp P.A.R.D.
Short Circuit Current
Vin = 28 V, RL = 0.1 W
1.6 A
Efficiency
Vin = 28 V, IO = 1.0 A
71%
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10
L1 - 3.5 mH @ 0.3 A
T1 - Primary: 20T C.T. #28 AWG
T1 - Secondary: 12OT C.T. #36 AWG
T1 - Core: Ferroxcube 1408P-L00-3CB
TL494, NCV494
1.0mH @ 2A
+Vin = 10V to 40V
+VO = 5.0 V
Tip 32A
IO = 1.0 A
47
150
12
8
VCC
50
50V
47k
0.1
11
C1
C2
+
TL494
CT
5
3
Comp
-
2
+
1
Vref
D.T. O.C. Gnd E1
6
4
13
7
9
5.1k
5.1k
14
- 15
16
+
RT
1.0M
500
10V
MR850
5.1k
E2
+
10
150
0.001
47k
0.1
Figure 21. Pulse Width Modulated Step−Down Converter
Test
+
Conditions
Results
Line Regulation
Vin = 8.0 V to 40 V
3.0 mV
0.01%
Load Regulation
Vin = 12.6 V, IO = 0.2 mA to 200 mA
5.0 mV
0.02%
Output Ripple
Vin = 12.6 V, IO = 200 mA
Short Circuit Current
Vin = 12.6 V, RL = 0.1 W
Efficiency
Vin = 12.6 V, IO = 200 mA
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11
40 mV pp
P.A.R.D.
250 mA
72%
50
10V
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE V
16
1
SCALE 1:1
D
A
16
9
E
H
E1
1
NOTE 8
b2
8
c
B
TOP VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
A1
C
D1
e
SEATING
PLANE
M
eB
END VIEW
16X b
SIDE VIEW
0.010
M
C A
M
B
M
NOTE 6
DATE 22 APR 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.735 0.775
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
18.67 19.69
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
GENERIC
MARKING DIAGRAM*
16
STYLE 1:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
STYLE 2:
PIN 1. COMMON DRAIN
2. COMMON DRAIN
3. COMMON DRAIN
4. COMMON DRAIN
5. COMMON DRAIN
6. COMMON DRAIN
7. COMMON DRAIN
8. COMMON DRAIN
9. GATE
10. SOURCE
11. GATE
12. SOURCE
13. GATE
14. SOURCE
15. GATE
16. SOURCE
98ASB42431B
PDIP−16
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
COLLECTOR
BASE
EMITTER
NO CONNECTION
EMITTER
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
CATHODE
ANODE
NO CONNECTION
CATHODE
CATHODE
NO CONNECTION
ANODE
CATHODE
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
COLLECTOR, DYE #1
BASE, #1
EMITTER, #1
COLLECTOR, #1
COLLECTOR, #2
BASE, #2
EMITTER, #2
COLLECTOR, #2
COLLECTOR, #3
BASE, #3
EMITTER, #3
COLLECTOR, #3
COLLECTOR, #4
BASE, #4
EMITTER, #4
COLLECTOR, #4
STYLE 4:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
STYLE 5:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
DRAIN, DYE #1
DRAIN, #1
DRAIN, #2
DRAIN, #2
DRAIN, #3
DRAIN, #3
DRAIN, #4
DRAIN, #4
GATE, #4
SOURCE, #4
GATE, #3
SOURCE, #3
GATE, #2
SOURCE, #2
GATE, #1
SOURCE, #1
STYLE 6:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
STYLE 7:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
SOURCE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE P‐CH
SOURCE P‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
GATE N‐CH
COMMON DRAIN (OUTPUT)
COMMON DRAIN (OUTPUT)
SOURCE N‐CH
COLLECTOR, DYE #1
COLLECTOR, #1
COLLECTOR, #2
COLLECTOR, #2
COLLECTOR, #3
COLLECTOR, #3
COLLECTOR, #4
COLLECTOR, #4
BASE, #4
EMITTER, #4
BASE, #3
EMITTER, #3
BASE, #2
EMITTER, #2
BASE, #1
EMITTER, #1
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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