UC2845BD1R2G

UC3844B, UC3845B, UC2844B, UC2845B High Performance Current Mode Controllers The UC3844B, UC3845B series are high performance fixed frequency current mode controllers. They are specifically designed for Off−Line and dc−dc converter applications offering the designer a cost−effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle−by−cycle current limiting, a latch for single pulse metering, and a flip−flop which blanks the output off every other oscillator cycle, allowing output deadtimes to be programmed from 50% to 70%. These devices are available in an 8−pin dual−in−line and surface mount (SOIC−8) plastic package as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14 package has separate power and ground pins for the totem pole output stage. The UCX844B has UVLO thresholds of 16V (on) and 10V (off), ideally suited for off−line converters. The UCX845B is tailored for lower voltage applications having UVLO thresholds of 8.5V (on) and 7.6V (off). Features • • • • • • • • • • • • Trimmed Oscillator for Precise Frequency Control Oscillator Frequency Guaranteed at 250 kHz Current Mode Operation to 500 kHz Output Switching Frequency Output Deadtime Adjustable from 50% to 70% Automatic Feed Forward Compensation Latching PWM for Cycle−By−Cycle Current Limiting Internally Trimmed Reference with Undervoltage Lockout High Current Totem Pole Output Undervoltage Lockout with Hysteresis Low Startup and Operating Current These Devices are Pb−Free and are RoHS Compliant NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable VCC Vref 8(14) 5.0V Reference R R Vref Undervoltage Lockout 8 1 SOIC−14 D SUFFIX CASE 751A 14 1 SOIC−8 D1 SUFFIX CASE 751 8 1 PIN CONNECTIONS Compensation Voltage Feedback Current Sense RT/CT 1 8 2 7 3 6 4 5 (Top View) Compensation NC Voltage Feedback NC Current Sense NC RT/CT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 Vref VCC Output GN D Vref NC VCC VC Output GND Power Ground (Top View) VC 7(11) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. Oscillator 4(7) Latching PWM Voltage Feedback Input Output/ Compensation VCC Undervoltage Lockout PDIP−8 N SUFFIX CASE 626 Output RT/CT 2(3) 7(12) http://onsemi.com 6(10) Power Ground 5(8) Current Sense Input Error Amplifier DEVICE MARKING INFORMATION See general marking information in the device marking section on page 16 of this data sheet. 3(5) 1(1) GND 5(9) Pin numbers in parenthesis are for the D suffix SOIC-14 package. Figure 1. Simplified Block Diagram © Semiconductor Components Industries, LLC, 2013 August, 2013 − Rev. 11 1 Publication Order Number: UC3844B/D UC3844B, UC3845B, UC2844B, UC2845B MAXIMUM RATINGS Rating Symbol Value Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) (Note 1) VCC, VC 36 V Total Power Supply and Zener Current (ICC + IZ) 30 mA Output Current, Source or Sink (Note 2) IO 1.0 A Output Energy (Capacitive Load per Cycle) W 5.0 mJ Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V Error Amp Output Sink Current IO 10 mA PD RqJA 862 145 mW °C/W PD RqJA 702 178 mW °C/W PD RqJA 1.25 100 W °C/W TJ +150 °C TA 0 to +70 −25 to +85 −40 to +105 °C Power Dissipation and Thermal Characteristics D Suffix, Plastic Package, SOIC−14 Case 751A Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air D1 Suffix, Plastic Package, SOIC−8 Case 751 Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air N Suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air Operating Junction Temperature Operating Ambient Temperature UC3844B, UC3845B UC2844B, UC2845B UC3844BV, UC3845BV Unit Storage Temperature Range Tstg − 65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The voltage is clamped by a zener diode (see page 9 Under Voltage Lockout section). Therefore this voltage may be exceeded as long as the total power supply and zener current is not exceeded. 2. Maximum package power dissipation limits must be observed. 3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC Standard JESD22-A114B, Machine Model Method 200 V per JEDEC Standard JESD22-A115-A 4. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78 ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 5], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 6], unless otherwise noted.) UC284xB Characteristic UC384xB, xBV, NCV384xBV Symbol Min Typ Max Min Typ Max Unit Vref 4.95 5.0 5.05 4.9 5.0 5.1 V Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV Temperature Stability TS − 0.2 − − 0.2 − mV/°C Total Output Variation over Line, Load, & Temperature Vref 4.9 − 5.1 4.82 − 5.18 V Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − mV Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV ISC − 30 − 85 −180 − 30 − 85 −180 mA fOSC 49 48 225 52 − 250 55 56 275 49 48 225 52 − 250 55 56 275 kHz Frequency Change with Voltage (VCC = 12 V to 25 V) DfOSC/DV − 0.2 1.0 − 0.2 1.0 % Frequency Change w/ Temperature (TA = Tlow to Thigh) DfOSC/DT − 1.0 − − 0.5 − % VOSC − 1.6 − − 1.6 − V REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = 25°C TA = Tlow to Thigh TJ = 25°C (RT = 6.2 k, CT = 1.0 nF) Oscillator Voltage Swing (Peak−to−Peak) 5. Adjust VCC above the Startup threshold before setting to 15 V. 6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Thigh = + 70°C for UC3844B, UC3845B Tlow = 0°C for UC3844B, UC3845B = − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B = − 40°C for UC384xBV, NCV384xBV =+105°C for UC3844BV, UC3845BV = +125°C for NCV384xBV http://onsemi.com 2 UC3844B, UC3845B, UC2844B, UC2845B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.) UC284xB UC384xB, xBV, NCV384xBV Characteristic Symbol Min Typ Max Min Typ Max Unit Discharge Current (VOSC = 2.0 V) TJ = 25°C TA = Tlow to Thigh (UC284XB, UC384XB) (UC384XBV) Idischg 7.8 7.5 − 8.3 − − 8.8 8.8 − 7.8 7.6 7.2 8.3 − − 8.8 8.8 8.8 mA VFB 2.45 2.5 2.55 2.42 2.5 2.58 V IIB − − 0.1 −1.0 − − 0.1 − 2.0 mA AVOL 65 90 − 65 90 − dB MHz OSCILLATOR SECTION ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) Input Bias Current (VFB = 5.0 V) Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB Output Current − Sink (VO = 1.1 V, VFB = 2.7 V) Output Current − Source (VO = 5.0 V, VFB = 2.3 V) ISink 2.0 − 0.5 12 −1.0 − − 2.0 − 0.5 12 −1.0 − − mA VOH VOL 5.0 6.2 − 5.0 6.2 − − − 0.8 − 1.1 − − − 0.8 0.8 1.1 1.2 2.85 − 3.0 − 3.15 − 2.85 2.85 3.0 3.0 3.15 3.25 0.9 − 1.0 − 1.1 − 0.9 0.85 1.0 1.0 1.1 1.1 PSRR − 70 − − 70 − dB ISource Output Voltage Swing High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to Vref, VFB = 2.7 V) (UC284XB, UC384XB) (UC384XBV) V CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 9 & 10) (UC284XB, UC384XB) (UC384XBV) AV Maximum Current Sense Input Threshold (Note 9) (UC284XB, UC384XB) (UC384XBV) Vth Power Supply Rejection Ratio (VCC = 12 V to 25 V) (Note 9) Input Bias Current Propagation Delay (Current Sense Input to Output) V/V V IIB − − 2.0 −10 − − 2.0 −10 mA tPLH(In/Out) − 150 300 − 150 300 ns VOL − − − 13 − 12 0.1 1.6 − 13.5 − 13.4 0.4 2.2 − − − − − − − 13 12.9 12 0.1 1.6 1.6 13.5 − 13.4 0.4 2.2 2.3 − − − OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) (ISink = 200 mA, UC284XB, UC384XB) (ISink = 200 mA, UC384XBV) High State (ISource = 20 mA, UC284XB, UC384XB) (ISource = 20 mA, UC384XBV) (ISource = 200 mA) V VOH Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) − 0.1 1.1 − 0.1 1.1 V Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns UNDERVOLTAGE LOCKOUT SECTION Startup Threshold UCX844B, BV UCX845B, BV Vth 15 7.8 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 V Minimum Operating Voltage After Turn−On UCX844B, BV UCX845B, BV VCC(min) 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 V 7. Adjust VCC above the Startup threshold before setting to 15 V. 8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Thigh = + 70°C for UC3844B, UC3845B Tlow = 0°C for UC3844B, UC3845B = − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B = − 40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV = +125°C for NCV384xBV 9. This parameter is measured at the latch trip point with VFB = 0 V. 10. Comparator gain is defined as: AV = DV Output/Compensation DV Current Sense Input http://onsemi.com 3 UC3844B, UC3845B, UC2844B, UC2845B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 11], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 12], unless otherwise noted.) UC284xB Characteristic UC384xB, xBV, NCV384xBV Symbol Min Typ Max Min Typ Max DC(max) 47 − − 48 − − 50 − 0 47 46 − 48 48 − 50 50 0 − 0.3 0.5 − 0.3 0.5 − 12 17 − 12 17 30 36 − 30 36 − Unit PWM SECTION Duty Cycle Maximum (UC284XB, UC384XB) Maximum (UC384XBV) Minimum % DC(min) TOTAL DEVICE Power Supply Current Startup (VCC = 6.5 V for UCX845B, Startup (VCC = 14 V for UCX844B, BV) Operating (Note 11) ICC Power Supply Zener Voltage (ICC = 25 mA) VZ mA V 11. Adjust VCC above the Startup threshold before setting to 15 V. 12. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Thigh = + 70°C for UC3844B, UC3845B Tlow = 0°C for UC3844B, UC3845B = − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B = − 40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV =+125°C for NCV384xBV 80 % DT, PERCENT OUTPUT DEADTIME R T, TIMING RESISTOR (k Ω) 75 VCC = 15 V TA = 25°C 50 20 8.0 5.0 2.0 NOTE: Output switches at 1/2 the oscillator frequency 0.8 10 k 20 k 50 k 100 k 200 k 500 k fOSC, OSCILLATOR FREQUENCY (kHz) 70 65 60 ÄÄÄÄÄ ÄÄÄÄÄ ÄÄÄÄÄ ÄÄÄÄÄ ÄÄÄÄÄ ÄÄÄÄÄ 2 4 1 7 55 5 6 50 10 k 1.0 M 3 1.CT = 10 nF 2.CT = 5.0 nF 3.CT = 2.0 nF 4.CT = 1.0 nF 5.CT = 500 pF 6.CT = 200 pF 7.CT = 100 pF 20 k 50 k 100 k 200 k 500 k fOSC, OSCILLATOR FREQUENCY (kHz) 1.0 M For R T u 5 Kf X 1.72 R TC T Figure 2. Timing Resistor versus Oscillator Frequency Figure 3. Output Deadtime versus Oscillator Frequency VCC = 15 V AV = -1.0 TA = 25°C 200 mV/DIV 2.5 V VCC = 15 V AV = -1.0 TA = 25°C 3.0 V 20 mV/DIV 2.55 V 2.5 V 2.0 V 2.45 V 0.5 ms/DIV 1.0 ms/DIV Figure 4. Error Amp Small Signal Transient Response Figure 5. Error Amp Large Signal Transient Response http://onsemi.com 4 φ, EXCESS PHASE (DEGREES) Vth , CURRENT SENSE INPUT THRESHOLD (V) A VOL , OPEN LOOP VOLTAGE GAIN (dB) UC3844B, UC3845B, UC2844B, UC2845B 0 1.2 30 1.0 60 0.8 90 0.6 20 120 0.4 0 150 0.2 180 10 M 0 100 VCC = 15 V VO = 2.0 V to 4.0 V RL = 100 k TA = 25°C 80 Gain 60 40 Phase -20 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M VCC = 15 V TA = 25°C TA = 125°C TA = -55°C 0 0 VCC = 15 V -4.0 -8.0 -12 TA = -55°C TA = 125°C -16 -20 TA = 25°C -24 0 20 40 60 80 100 Iref, REFERENCE SOURCE CURRENT (mA) 120 ÄÄÄÄ ÄÄÄÄ 110 VCC = 15 V RL ≤ 0.1 W 90 70 50 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 Figure 9. Reference Short Circuit Current versus Temperature ΔV , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) Figure 8. Reference Voltage Change versus Source Current VCC = 15 V IO = 1.0 mA to 20 mA TA = 25°C VCC = 12 V to 25 V TA = 25°C O O ΔV , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) 8.0 Figure 7. Current Sense Input Threshold versus Error Amp Output Voltage ISC , REFERENCE SHORT CIRCUIT CURRENT (mA) Δ Vref , REFERENCE VOLTAGE CHANGE (mV) Figure 6. Error Amp Open Loop Gain and Phase versus Frequency 2.0 4.0 6.0 VO, ERROR AMP OUTPUT VOLTAGE (VO) 2.0 ms/DIV 2.0 ms/DIV Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation http://onsemi.com 5 125 0 TA = 25°C -2.0 Source Saturation (Load to Ground) VCC = 15 V 80 ms Pulsed Load 120 Hz Rate VCC = 15 V CL = 1.0 nF TA = 25°C 90 % TA = -55°C 3.0 TA = -55°C 2.0 TA = 25°C Sink Saturation (Load to VCC) GND 200 400 600 IO, OUTPUT LOAD CURRENT (mA) 800 50 ns/DIV Figure 12. Output Saturation Voltage versus Load Current Figure 13. Output Waveform 25 20 15 5 0 0 UCX844B 10 UCX845B 100 mA/DIV ICC, SUPPLY CURRENT VCC = 30 V CL = 15 pF TA = 25°C ICC, SUPPLY CURRENT (mA) 0 10 % 20 V/DIV 1.0 0 ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄ ÄÄÄÄÄÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄ VCC -1.0 V O , OUTPUT VOLTAGE Vsat , OUTPUT SATURATION VOLTAGE (V) UC3844B, UC3845B, UC2844B, UC2845B 10 100 ns/DIV Figure 14. Output Cross Conduction ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ RT = 10 k CT = 3.3 nF VFB = 0 V ISense = 0 V TA = 25°C 20 30 VCC, SUPPLY VOLTAGE (V) 40 Figure 15. Supply Current versus Supply Voltage PIN FUNCTION DESCRIPTION Pin 8−Pin 14−Pin Function 1 1 Compensation 2 3 Voltage Feedback 3 5 Current Sense 4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible. GND This pin is the combined control circuitry and power ground. 6 10 Output 7 12 VCC This pin is the positive supply of the control IC. 8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT. 8 Power Ground 11 VC 9 GND 2,4,6,13 NC 5 Description This pin is the Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. The output switches at one−half the oscillator frequency. This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. This pin is the control circuitry ground return and is connected back to the powersource ground. No connection. These pins are not internally connected. http://onsemi.com 6 UC3844B, UC3845B, UC2844B, UC2845B OPERATING DESCRIPTION Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft−start interval (Figures 21, 22). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (VOH) to reach the comparator’s 1.0 V clamp level: The UC3844B, UC3845B series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off−Line and DC−DC converter applications offering the designer a cost−effective solution with minimal external components. A representative block diagram is shown in Figure 16. Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. An internal flip−flop has been incorporated in the UCX844/5B which blanks the output off every other clock cycle by holding one of the inputs of the NOR gate high. This in combination with the CT discharge period yields output deadtimes programmable from 50% to 70%. Figure 2 shows RT versus Oscillator Frequency and Figure 3, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated to within ±6% at 50 kHz. Also, because of industry trends moving the UC384X into higher and higher frequency applications, the UC384XB is guaranteed to within ±10% at 250 kHz. In many noise−sensitive applications it may be desirable to frequency−lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 18. For reliable locking, the free−running oscillator frequency should be set about 10% less than the clock frequency. A method for multi−unit synchronization is shown in Figure 19. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved to realize output deadtimes of greater than 70%. Rf(min) ≈ 3.0 (1.0 V) + 1.4 V = 8800 W 0.5 mA Current Sense Comparator and PWM Latch The UC3844B, UC3845B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle−by−cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground−referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 1 where: Ipk = V(Pin 1) − 1.4 V 3 RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is: Ipk(max) = 1.0 V RS When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 20. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability (refer to Figure 24). Error Amplifier A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 6). The non−inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is −2.0 mA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 29). The output voltage is offset by two diode drops (≈1.4 V) and divided by three before it connects to the inverting input of the Current Sense http://onsemi.com 7 UC3844B, UC3845B, UC2844B, UC2845B VCC VCC 7(12) 36V Vref Reference Regulator 8(14) R 2.5V RT Vin VCC UVLO Internal Bias R + - 3.6V + - (See Text) VC 7(11) Vref UVLO Output Q1 Oscillator CT 4(7) 6(10) T + 1.0mA S Voltage Feedback Input 2(3) Output/ Compensation 1(1) 2R Q R R Error Amplifier Power Ground PWM Latch 1.0V Current Sense Input Current Sense Comparator GND 5(8) 3(5) 5(9) Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. Pin numbers in parenthesis are for the D suffix SOIC-14 package. = Sink Only Positive True Logic Figure 16. Representative Block Diagram Capacitor CT Latch “Set" Input Output/ Compensation Current Sense Input Latch “Reset" Input Output Small RT/Large CT Large RT/Small CT Figure 17. Timing Diagram http://onsemi.com 8 RS UC3844B, UC3845B, UC2844B, UC2845B Undervoltage Lockout designer added flexibility in tailoring the drive voltage independent of VCC. A Zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater than 20 V. Figure 23 shows proper power and control ground connections in a current−sensing power MOSFET application. Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (Vref) are each monitored by separate comparators. Each has built−in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX844B, and 8.4 V/7.6 V for the UCX845B. The Vref comparator upper and lower thresholds are 3.6 V/3.4 V. The large hysteresis and low startup current of the UCX844B makes it ideally suited in off−line converter applications where efficient bootstrap startup techniques are required (Figure 30). The UCX845B is intended for lower voltage dc−dc converter applications. A 36 V Zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX844B is 11 V and 8.2 V for the UCX845B. Reference The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the UC384XB. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short−circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wire−wrap or plug−in prototype boards. High frequency circuit layout techniques are imperative to prevent pulse−width jitter. This is usually caused by excessive noise pick−up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low−current signal and high−current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 mF) connected directly to VCC, VC, and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise−generating components. Output These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pulldown resistor. The SOIC−14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate VC supply input allows the Vref 8(14) 8(14) R RT R RA Bias Bias R 8 RB 5.0k 6 R 4 3 Osc CT 4(7) 0.01 External Sync Input Osc + 5 2R 47 2(3) EA 5.0k 2 R 5.0k C R Q S 4(7) + 7 2R 2(3) MC1455 EA R 1 1(1) 1(1) 5(9) To Additional UCX84XBs The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground. f + Figure 18. External Clock Synchronization 1.44 (RA ) 2RB)C D(max) + RA RA ) 2RB Figure 19. External Duty Cycle Clamp and Multi−Unit Synchronization http://onsemi.com 9 5(9) UC3844B, UC3845B, UC2844B, UC2845B VCC Vin 7(12) 5.0V Ref 8(14) 5.0V Ref 8(14) R Bias + - Bias R R + - 7(11) + - Osc Q1 4(7) Osc 4(7) T VClamp + R2 R 6(10) Q 2(3) Q R 2R R EA 2(3) 1.0V 1(1) 3(5) 1(1) RS C 1.67 ǒRR21 ) 1Ǔ + 0.33x10 -3 5(9) tSoft-Start ≈ 3600C in mF 5(9) VClamp ≈ EA 1.0M 5(8) R 2R R Comp/Latch 1.0V R1 S 1.0mA S 1.0 mA T + ǒR1R)1R2R2Ǔ Where: 0 ≤ VClamp ≤ 1.0 V V Ipk(max) [ Clamp RS Figure 20. Adjustable Reduction of Clamp Level VCC Figure 21. Soft−Start Circuit Vin VCC Vin VPin5 [ (12) 7(12) RSIpkrDS(on) rDM(on) ) RS If: SENSEFET = MTP10N10M RS = 200 5.0V Ref 5.0V Ref 8(14) R Bias R 7(11) + - + S G Q1 T VClamp T 6(10) 2(3) 1.0V R2 1.67 ǒRR21 ) 1Ǔ ƪ ƫ RS 1/4 W Power Ground: To Input Source Return Control Circuitry Ground: To Pin (9) Where: 0 ≤ VClamp ≤ 1.0 V R1R2 tSoftStart + * In 1 * VC C R1 ) R2 3VClamp (8) (5) RS 5(9) MPSA63 M Comp/Latch Comp/Latch 3(5) VClamp ≈ R 5(8) 1(1) R1 (10) Q Q R 2R R EA K S S 1.0 mA D SENSEFET (11) + - Osc 4(7) Then : VPin5 [ 0.075Ipk + - + - Virtually lossless current sensing can be achieved with the implementation of a SENSEFETt power switch. For proper operation during over-current conditions, a reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 20 and 22. V Ipk(max) [ Clamp RS Figure 23. Current Sensing Power MOSFET Figure 22. Adjustable Buffered Reduction of Clamp Level with Soft−Start http://onsemi.com 10 UC3844B, UC3845B, UC2844B, UC2845B VCC Vin 7(12) 5.0V Ref + 7(11) + - Q1 T The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform. 6(10) S 5(8) Q R 3(5) Comp/Latch R C RS Figure 24. Current Waveform Spike Suppression VCC Vin IB 7(12) + Vin 0 5.0V Ref - + - Base Charge Removal C1 7(11) + - Rg Q1 Q1 6(10) T 6(10) S Q R 5(8) 5(8) Comp/Latch 3(5) 3(5) RS RS Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. The totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1. Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive http://onsemi.com 11 UC3844B, UC3845B, UC2844B, UC2845B Vin VCC 7(12) Isolation Boundary 5.0V Ref + - VGS Waveforms 7(11) + - + Q1 + 0 0 - T 50% DC 6(10) S 5(8) Q V(Pin1) - 1.4 Ipk = R 3 RS R 3(5) Comp/Latch C RS NS 25% DC ǒNNSpǓ NP Figure 27. Isolated MOSFET Drive 8(14) R Bias R Osc 4(7) + 1.0 mA 2(3) 2R R EA 1(1) MCR 101 2N 3905 5(9) 2N 3903 The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. Figure 28. Latched Shutdown 2.5V From VO Rd + 1.0mA Ri 2(3) Cf Rf EA 2.5V From VO + 2R Rp R Cp Ri Rd Cf 1(1) Rf ≥ 8.8k 1.0mA 2R 2(3) Rf EA R 1(1) 5(9) 5(9) Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current. Error Amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current. Figure 29. Error Amplifier Compensation http://onsemi.com 12 UC3844B, UC3845B, UC2844B, UC2845B L1 MBR1635 4.7W + MDA 202 4.7k 250 3300 pF 56k 115 Vac T1 2200 + 1000 + 5.0V RTN MUR110 1N4935 7(12) + 1N4935 68 + 5.0V Ref 8(14) R 4(7) T + 6(10) EA 150k 1N4937 MTP 4N50 1N5819 5(8) 1.0k Comp/Latch 3(5) 1(1) 470pF 0.5 5(9) T1 - Primary: 45 Turns #26 AWG Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound Core: Ferroxcube EC35-3C8 Bobbin: Ferroxcube EC35PCB1 Gap: ≈ 0.10" for a primary inductance of 1.0 mH L1 - 15 mH at 5.0 A, Coilcraft Z7156 L2, L3 - 25 mH at 5.0 A, Coilcraft Z7157 Figure 30. 7 W Off−Line Flyback Regulator Test Line Regulation: Conditions Results Vin = 95 Vac to 130 Vac D = 50 mV or ±0.5% D = 24 mV or ±0.1% Load Regulation: 5.0 V ±12 V Vin = 115 Vac, Iout = 1.0 A to 4.0 A Vin = 115 Vac, Iout = 100 mA to 300 mA D = 300 mV or ±3.0% D = 60 mV or ±0.25% Output Ripple: Vin = 115 Vac 40 mVpp 80 mVpp Vin = 115 Vac 70% Efficiency 5.0 V ±12 V 5.0 V ±12 V All outputs are at nominal load currents unless otherwise noted. http://onsemi.com 13 + 12V/0.3A + -12V/0.3A L3 Q R 4.7k 680pF 2.7k 22 2(3) 100 pF 10 7(11) + - S 18k + MUR110 Osc 1.0nF 1000 Bias 33k 10 ±12V RTN 1N4937 + - R + L2 47 100 0.01 1000 5.0V/4.0A UC3844B, UC3845B, UC2844B, UC2845B Output Load Regulation (Open Loop Configuration) Vin = 15V 7(12) UC3845B + IO (mA) VO (V) 0 2 9 18 36 29.9 28.8 28.3 27.4 24.4 47 34V 8(14) 10k Reference Regulator 2.5V VCC UVLO R Internal Bias R + - 3.6V + - 1N5819 7(11) Vref UVLO 6(10) 15 10 Osc 4(7) 1.0nF 0.5mA 2(3) S 2R R PWM Latch 1.0V R2 47 3(5) Current Sense Comparator 1(1) + Connect to Pin 2 for closed loop operation. 5(8) Q R Error Amplifier VO ≈ 2 (Vin) + T + 1N5819 R1 ǒR2 ) 1Ǔ R1 VO = 2.5 5(9) The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. The converter's output can provide excellent line and load regulation by connecting the R2/R1 resistor divider as shown. Figure 31. Step−Up Charge Pump Converter Output Load Regulation Vin = 15V UC3845B 7(12) + IO (mA) VO (V) 0 2 9 18 32 −14.4 −13.2 −12.5 −11.7 −10.6 47 34V 8(14) 10k Reference Regulator 2.5V R VCC UVLO Internal Bias R + - 3.6V + - Vref UVLO 7(11) 6(10) 15 10 1N5819 VO ≈ -Vin Osc 1.0nF 4(7) T + 0.5mA 2(3) R 5(8) Q R Error Amplifier 1N5819 S 2R 1.0V PWM Latch 3(5) Current Sense Comparator 1(1) 5(9) The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. Figure 32. Voltage−Inverting Charge Pump Converter http://onsemi.com 14 + 47 UC3844B, UC3845B, UC2844B, UC2845B ORDERING INFORMATION Package Shipping† UC384xBDG SOIC−14 (Pb−Free) 55 Units/Rail UC384xBDR2G SOIC−14 (Pb−Free) 2500 Tape & Reel SOIC−8 (Pb−Free) 98 Units/Rail UC384xBD1R2G SOIC−8 (Pb−Free) 2500 Tape & Reel UC384xBNG PDIP−8 (Pb−Free) 50 Units/Rail UC284xBDG SOIC−14 (Pb−Free) 55 Units/Rail UC284xBDR2G SOIC−14 (Pb−Free) 2500 Tape & Reel SOIC−8 (Pb−Free) 98 Units/Rail UC284xBD1R2G SOIC−8 (Pb−Free) 2500 Tape & Reel UC284xBNG PDIP−8 (Pb−Free) 50 Units/Rail UC384xBVDG SOIC−14 (Pb−Free) 55 Units/Rail UC384xBVDR2G SOIC−14 (Pb−Free) 2500 Tape & Reel SOIC−8 (Pb−Free) 98 Units/Rail UC384xBVD1R2G SOIC−8 (Pb−Free) 2500 Tape & Reel UC384xBVNG PDIP−8 (Pb−Free) 50 Units/Rail SOIC−8 (Pb−Free) 2500 Tape & Reel Device UC384xBD1G UC284xBD1G UC384xBVD1G NCV3845BVD1R2G* Operating Temperature Range TA = 0° to +70°C TA = −25° to +85°C TA = −40° to +105°C TA = −40° to +125°C †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. x indicates either a 4 or 5 to define specific device part numbers. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 15 UC3844B, UC3845B, UC2844B, UC2845B MARKING DIAGRAMS PDIP−8 N SUFFIX CASE 626 8 8 UC384xBN AWL YYWWG 8 UC384xBVN AWL YYWWG 1 UC284xBN AWL YYWWG 1 1 SOIC−14 D SUFFIX CASE 751A 14 14 UC384xBDG AWLYWW 1 14 UC384xBVDG AWLYWW UC284xBDG AWLYWW 1 1 SOIC−8 D1 SUFFIX CASE 751 8 8 384xB ALYW G 8 384xB ALYWV G 1 1 x A WL, L YY, Y WW, W G or G 284xB ALYW G 1 = 4 or 5 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package SENSEFET is a trademark of Semiconductor Components Industries, LLC. http://onsemi.com 16 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−8 CASE 626−05 ISSUE P DATE 22 APR 2015 SCALE 1:1 D A E H 8 5 E1 1 4 NOTE 8 b2 c B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L SEATING PLANE A1 C D1 M e 8X SIDE VIEW b 0.010 eB END VIEW M C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.355 0.400 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 9.02 10.16 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° NOTE 6 GENERIC MARKING DIAGRAM* STYLE 1: PIN 1. AC IN 2. DC + IN 3. DC − IN 4. AC IN 5. GROUND 6. OUTPUT 7. AUXILIARY 8. VCC XXXXXXXXX AWL YYWWG XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98ASB42420B PDIP−8 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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