DATA SHEET
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High Performance
Current Mode Controllers
PDIP−8
N SUFFIX
CASE 626
8
UC3842B, UC3843B,
UC2842B, UC2843B
1
The UC3842B, UC3843B series are high performance fixed
frequency current mode controllers. They are specifically designed for
Off−Line and DC−DC converter applications offering the designer
a cost−effective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole
output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, programmable output deadtime, and a latch for single
pulse metering.
These devices are available in an 8−pin dual−in−line and surface
mount (SOIC−8) plastic package as well as the 14−pin plastic surface
mount (SOIC−14). The SOIC−14 package has separate power and
ground pins for the totem pole output stage.
The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX843B is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
Features
•
•
•
•
•
•
•
•
•
•
Trimmed Oscillator for Precise Frequency Control
Oscillator Frequency Guaranteed at 250 kHz
Current Mode Operation to 500 kHz
Automatic Feed Forward Compensation
Latching PWM for Cycle−By−Cycle Current Limiting
Internally Trimmed Reference with Undervoltage Lockout
High Current Totem Pole Output
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
This is a Pb−Free and Halide−Free Device
VCC
Vref
5.0V
Reference
8(14)
R
RT/CT
4(7)
Voltage
Feedback
Input
2(3)
Output
Compensation
1(1)
1
SOIC−8
D1 SUFFIX
CASE 751
8
1
PIN CONNECTIONS
Compensation
Voltage Feedback
Current Sense
RT/CT
1
8
2
7
3
6
4
5
Vref
VCC
Output
GND
(Top View)
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
RT/CT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Vref
NC
VCC
VC
Output
GND
Power Ground
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 19 of this data sheet.
7(12)
VCC
Undervoltage
Lockout
Vref
Undervoltage
Lockout
R
SOIC−14
D SUFFIX
CASE 751A
14
VC
7(11)
Output
Oscillator
6(10)
Power
Ground
5(8)
Latching
PWM
+
-
Error
Amplifier
Current
Sense
3(5) Input
GND
5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2013
August, 2021 − Rev. 18
1
Publication Order Number:
UC3842B/D
UC3842B, UC3843B, UC2842B, UC2843B
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec)
VCC, VC
30
V
Total Power Supply and Zener Current
(ICC + IZ)
30
mA
IO
1.0
A
Output Current, Source or Sink
Output Energy (Capacitive Load per Cycle)
W
5.0
mJ
Current Sense, Voltage Feedback, Vref and Rt/Ct Inputs
Vin
−0.3 to + 5.5
V
Vcomp
−0.3 to + 7.2
V
Output
Vo
−0.3 to VCC or
VC + 0.3
V
Error Amp Output Sink Current
IO
10
mA
PD
RqJA
862
145
mW
°C/W
PD
RqJA
702
178
mW
°C/W
PD
RqJA
1.25
100
W
°C/W
TJ
+150
°C
Compensation
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SOIC−14 Case 751A
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
D1 Suffix, Plastic Package, SOIC−8 Case 751
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
Operating Junction Temperature
Operating Ambient Temperature
UC3842B, UC3843B
UC2842B, UC2843B
UC2843D
UC3842BV, UC3843BV
Storage Temperature Range
TA
Tstg
0 to 70
−25 to + 85
−40 to +85
−40 to +105
−65 to +150
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 4000 V per JEDEC Standard JESD22-A114B
Machine Model Method 200 V per JEDEC Standard JESD22-A115-A
2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78
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2
UC3842B, UC3843B, UC2842B, UC2843B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 3], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.)
UC284XB, UC2843D
Characteristics
UC384XB, XBV
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
REFERENCE SECTION
Vref
4.95
5.0
5.05
4.9
5.0
5.1
V
Line Regulation (VCC = 12 V to 25 V)
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C)
Regline
−
2.0
20
−
2.0
20
mV
Load Regulation (IO = 1.0 mA to 20 mA)
Regload
−
3.0
25
−
3.0
25
mV
Temperature Stability
TS
−
0.2
−
−
0.2
−
mV/°C
Total Output Variation over Line, Load, and Temperature
UC284XB
UC2843D
Vref
4.9
4.82
−
−
5.1
5.18
4.82
−
5.18
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C)
Vn
−
50
−
−
50
−
mV
Long Term Stability (TA = 125°C for 1000 Hours)
S
−
5.0
−
−
5.0
−
mV
ISC
−30
−85
−180
−30
−85
−180
mA
49
48
225
52
−
250
55
56
275
49
48
225
52
−
250
55
56
275
Output Short Circuit Current
V
OSCILLATOR SECTION
Frequency
TJ = 25°C
TA = Tlow to Thigh
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)
fOSC
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V)
DfOSC/DV
−
0.2
1.0
−
0.2
1.0
%
Frequency Change with Temperature, TA = Tlow to Thigh
DfOSC/DT
−
1.0
−
−
0.5
−
%
Oscillator Voltage Swing (Peak−to−Peak)
VOSC
−
1.6
−
−
1.6
−
V
Discharge Current (VOSC = 2.0 V)
TJ = 25°C, TA = Tlow to Thigh
Idischg
7.8
7.5
−
8.3
−
−
8.8
8.8
−
7.8
7.6
7.2
8.3
−
−
8.8
8.8
8.8
2.45
2.42
2.5
2.5
2.55
2.58
2.42
2.5
2.58
UC284XB, UC384XB
UC2843D, UC384XBV
mA
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V)
UC284XB
UC2843D
Input Bias Current (VFB = 5.0 V)
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V)
Unity Gain Bandwidth (TJ = 25°C)
Power Supply Rejection Ratio (VCC = 12 V to 25 V)
Output Current
Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V)
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
UC284XB, UC384XB
UC2843D, UC384XBV
VFB
V
IIB
−
−0.1
−1.0
−
−0.1
−2.0
mA
AVOL
65
90
−
65
90
−
dB
BW
0.7
1.0
−
0.7
1.0
−
MHz
PSRR
60
70
−
60
70
−
ISink
ISource
2.0
−0.5
12
−1.0
−
−
2.0
−0.5
12
−1.0
−
−
VOH
VOL
5.0
6.2
−
5.0
6.2
−
−
−
0.8
−
1.1
−
−
−
0.8
0.8
1.1
1.2
3. Adjust VCC above the Startup threshold before setting to 15 V.
4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BV, UC2843D
Thigh = +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B, UC2843D; +105°C for UC3842BV, UC3843BV
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3
dB
mA
V
UC3842B, UC3843B, UC2842B, UC2843B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)
UC284XB, UC2843D
Characteristics
Symbol
UC384XB, XBV
Min
Typ
Max
Min
Typ
Max
Unit
2.85
−
3.0
−
3.15
−
2.85
2.85
3.0
3.0
3.15
3.25
0.9
−
1.0
−
1.1
−
0.9
0.85
1.0
1.0
1.1
1.1
PSRR
−
70
−
−
70
−
dB
IIB
−
−2.0
−10
−
−2.0
−10
mA
tPLH(In/Out)
−
150
300
−
150
300
ns
VOL
−
−
−
13
−
12
0.1
1.6
−
13.5
−
13.4
0.4
2.2
−
−
−
−
−
−
−
13
12.9
12
0.1
1.6
1.6
13.5
13.5
13.4
0.4
2.2
2.3
−
−
−
VOL(UVLO)
−
0.1
1.1
−
0.1
1.1
V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C)
tr
−
50
150
−
50
150
ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C)
tf
−
50
150
−
50
150
ns
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
94
−
−
96
−
−
−
−
0
94
93
−
96
96
−
−
−
0
−
0.3
0.5
−
0.3
0.5
−
12
17
−
12
17
30
36
−
30
36
−
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 5 and 6)
UC2843D, UC284XB, UC384XB
UC384XBV
AV
Maximum Current Sense Input Threshold (Note 5)
UC2843D, UC284XB, UC384XB
UC384XBV
Vth
Power Supply Rejection Ratio (VCC = 12 V to 25 V, Note 5)
Input Bias Current
Propagation Delay (Current Sense Input to Output)
V/V
V
OUTPUT SECTION
Output Voltage
Low State (ISink = 20 mA)
(ISink = 200 mA)
High State
UC284XB, UC384XB
UC384XBV, UC2843D
UC284XB, UC384XB
UC384XBV, UC2843D
(ISource = 20 mA)
VOH
(ISource = 200 mA)
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA)
V
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC)
Vth
UCX842B, BV
UCX843B, BV, D
Minimum Operating Voltage After Turn−On (VCC)
UCX842B, BV
UCX843B, BV, D
VCC(min)
V
V
PWM SECTION
Duty Cycle
Maximum UC284XB, UC384XB, UC2843D
Maximum UC384XBV
Minimum
DC(max)
DC(min)
%
TOTAL DEVICE
ICC + IC
Power Supply Current
Startup (VCC = 6.5 V for UCX843B, UC2843D
Startup VCC 14 V for UCX842B, BV)
(Note 7)
Power Supply Zener Voltage (ICC = 25 mA)
VZ
5. This parameter is measured at the latch trip point with VFB = 0 V.
6. Comparator gain is defined as: AV DV Output Compensation
DV Current Sense Input
7. Adjust VCC above the Startup threshold before setting to 15 V.
8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BV, UC2843D
Thigh = +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B, UC2843D; +105°C for UC3842BV, UC3843BV
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mA
V
UC3842B, UC3843B, UC2842B, UC2843B
80
100
% DT, PERCENT OUTPUT DEADTIME
20
8.0
5.0
2.0
0.8
10 k
VCC = 15 V
TA = 25°C
20 k
50 k
100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1. CT = 10 nF
50 2. CT = 5.0 nF
3. CT = 2.0 nF
4. CT = 1.0 nF
20 5. CT = 500 pF
6. CT = 200 pF
10 7. CT = 100 pF
D max , MAXIMUM OUTPUT DUTY CYCLE (%)
I dischg , DISCHARGE CURRENT (mA)
VCC = 15 V
VOSC = 2.0 V
8.5
8.0
7.5
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
7
VCC = 15 V
TA = 25°C
2.0
20 k
50 k
100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1.0 M
100
125
100
90
80
60
VCC = 15 V
CT = 3.3 nF
TA = 25°C
50
40
0.8
1.0
2.0
3.0
4.0
RT, TIMING RESISTOR (kW)
5.0 6.0 7.0 8.0
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
VCC = 15 V
AV = -1.0
TA = 25°C
VCC = 15 V
AV = -1.0
TA = 25°C
3.0 V
20 mV/DIV
2.50 V
Idischg = 8.54 mA
70
Figure 4. Oscillator Discharge Current
versus Temperature
2.55 V
6
Figure 3. Output Deadtime
versus Oscillator Frequency
9.0
-25
1
5
Figure 2. Timing Resistor
versus Oscillator Frequency
7.0
-55
3
2
5.0
1.0
10 k
1.0 M
4
20 mV/DIV
R T, TIMING RESISTOR (k Ω)
50
2.5 V
2.45 V
2.0 V
0.5 ms/DIV
1.0 ms/DIV
Figure 6. Error Amp Small Signal
Transient Response
Figure 7. Error Amp Large Signal
Transient Response
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Gain
60
0
30
60
40
90
Phase
20
120
0
150
100
1.0 k
10 k
100 k
180
10 M
1.0 M
0.8
TA = 25°C
0.6
TA = 125°C
0.4
TA = -55°C
0.2
0
0
Figure 8. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 9. Current Sense Input Threshold
versus Error Amp Output Voltage
ÄÄÄÄ
-4.0
-8.0
-12
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
TA = 125°C
-16
-20
ÄÄÄ
ÄÄÄ
TA = -55°C
TA = 25°C
20
40
60
80
100
120
8.0
ÄÄÄ
ÄÄÄ
110
VCC = 15 V
RL ≤ 0.1 W
90
70
50
-55
-25
0
25
50
75
100
Iref, REFERENCE SOURCE CURRENT (mA)
TA, AMBIENT TEMPERATURE (°C)
Figure 10. Reference Voltage Change
versus Source Current
Figure 11. Reference Short Circuit Current
versus Temperature
Δ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
Δ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
VCC = 15 V
1.0
2.0
4.0
6.0
VO, ERROR AMP OUTPUT VOLTAGE (V)
VCC = 15 V
0
1.2
f, FREQUENCY (Hz)
0
-24
Vth, CURRENT SENSE INPUT THRESHOLD (V)
80
-20
10
Δ Vref , REFERENCE VOLTAGE CHANGE (mV)
VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 K
TA = 25°C
φ, EXCESS PHASE (DEGREES)
100
I SC , REFERENCE SHORT CIRCUIT CURRENT (mA)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
UC3842B, UC3843B, UC2842B, UC2843B
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25°C
2.0 ms/DIV
Figure 12. Reference Load Regulation
VCC = 12 V to 25
TA = 25°C
2.0 ms/DIV
Figure 13. Reference Line Regulation
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125
0
-1.0
-2.0
Source Saturation
(Load to Ground)
VCC = 15 V
80 ms Pulsed Load
120 Hz Rate
VCC = 15 V
CL = 1.0 nF
TA = 25°C
90%
TA = -55°C
3.0
TA = -55°C
2.0
TA = 25°C
GND
400
600
200
10%
800
IO, OUTPUT LOAD CURRENT (mA)
50 ns/DIV
Figure 14. Output Saturation Voltage
versus Load Current
Figure 15. Output Waveform
25
20 V/DIV
100 mA/DIV
I CC , SUPPLY CURRENT
20
15
10
5
0
0
10
100 ns/DIV
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
RT = 10 k
CT = 3.3 nF
VFB = 0 V
ISense = 0 V
TA = 25°C
UCX842B
VCC = 30 V
CL = 15 pF
TA = 25°C
UCX843B
0
Sink Saturation
(Load to VCC)
I CC , SUPPLY CURRENT (mA)
1.0
0
ÄÄÄÄÄÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄÄÄÄÄÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄ
ÄÄÄ
ÄÄÄÄ ÄÄÄ
ÄÄÄÄ ÄÄ
VCC
TA = 25°C
V O , OUTPUT VOLTAGE
Vsat, OUTPUT SATURATION VOLTAGE (V)
UC3842B, UC3843B, UC2842B, UC2843B
20
30
40
VCC, SUPPLY VOLTAGE (V)
Figure 16. Output Cross Conduction
Figure 17. Supply Current versus Supply Voltage
PIN FUNCTION DESCRIPTION
8−Pin
14−Pin
Function
1
1
Compensation
2
3
Voltage
Feedback
3
5
Current
Sense
4
7
RT/CT
The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor
RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible.
GND
This pin is the combined control circuitry and power ground.
6
10
Output
7
12
VCC
This pin is the positive supply of the control IC.
8
14
Vref
This is the reference output. It provides charging current for capacitor CT through resistor RT.
8
Power
Ground
11
VC
The Output high state (VOH) is set by the voltage applied to this pin. With a separate power
source connection, it can reduce the effects of switching transient noise on the control circuitry.
9
GND
This pin is the control circuitry ground return and is connected back to the power source ground.
2,4,6,1
3
NC
5
Description
This pin is the Error Amplifier output and is made available for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin.
This pin is a separate power ground return that is connected back to the power source. It is used
to reduce the effects of switching transient noise on the control circuitry.
No connection. These pins are not internally connected.
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UC3842B, UC3843B, UC2842B, UC2843B
OPERATING DESCRIPTION
The UC3842B, UC3843B series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost−effective
solution
with
minimal
external
components.
A representative block diagram is shown in Figure 19.
D max +
ǒ
ǒ
t RTńCT(dischg) + R TC T ln
V RTńCT(peak) * V ref
Ǔ
V
Ǔ
V
*V
ref
RTńCT(valley)
V
*V
ref
RTńCT(peak)
*V
ref
RTńCT(valley)
V
*V
ref
RTńCT(peak)
Clearly, the maximum duty ratio is determined by the
timing resistor RT. Therefore, RT is chosen such as to
achieve a desired maximum duty ratio. Once RT has been
selected, CT can now be chosen to obtain the desired
switching frequency as per Equation 5.
f+
ǒ
R TC T ln
1
V
*V
ref
RTńCT(valley)
V
*V
ref
RTńCT(peak)
Ǔ
R I
)V
*V
T dischg
ref
RTńCT(peak)
I
)V
*V
T dischg
ref
RTńCT(valley)
@R
(eq. 5)
Figure 2 shows the frequency and maximum duty ratio
variation versus RT for given values of CT. Care should be
taken to ensure that the absolute minimum value of RT
should not be less than 542 W. However, considering a 10%
tolerance for the timing resistor, the nearest available
standard resistor of 680 W is the absolute minimum that can
be used to guarantee normal oscillator operation. If a timing
resistor smaller than this value is used, then the charging
current through the RT, CT path will exceed the pulldown
(discharge) current and the oscillator will get permanently
locked/latched to an undefined state.
In many noise-sensitive applications it may be desirable
to frequency-lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 22. For reliable synchronization, the
free-running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi-unit
synchronization is shown in Figure 23. By tailoring the
clock waveform, accurate Output duty ratio clamping can be
achieved.
Vref
(eq. 1)
R TI dischg ) V RTńCT(peak) * V ref
Ǔ
R I
)V
*V
T dischg
ref
RTńCT(peak)
I
)V
*V
T dischg
ref
RTńCT(valley)
@R
(eq. 4)
The oscillator frequency is programmed by the values
chosen for the timing components RT and CT. It must also be
noted that the value of RT uniquely determines the
maximum duty ratio of UC384xx. The oscillator
configuration depicting the connection of the timing
components to the RT/CT pin of the controller is shown in
Figure 18. Capacitor CT gets charged from the Vref source,
through resistor RT to its peak threshold VRT/CT(peak),
typically 2.8 V. Upon reaching this peak threshold volage, an
internal 8.3 mA current source, Idischg, is enabled and the
voltage across CT begins to decrease. Once the voltage
across CT reaches its valley threshold, VRT/CT(valley),
typically 1.2 V, Idischg turns off. This allows capacitor CT to
charge up again from Vref. This entire cycle repeats, and the
resulting waveform on the RT/CT pin has a sawtooth shape.
Typical waveforms are shown in Figure 20.
The oscillator thresholds are temperature compensated to
within ±6% at 50 kHz. Considering the general industry
trend of operating switching controllers at higher
frequencies, the UC384xx is guaranteed to operate within
±10% at 250 kHz. These internal circuit refinements
minimize variations of oscillator frequency and maximum
duty ratio.
The charging and discharging times of the timing
capacitor CT are calculated using Equations 1 and 2. These
equations do not take into account the propagation delays of
the internal comparator. Hence, at higher frequencies, the
calculated value of the oscillator frequency differs from the
actual value.
t RTńCT(chg) + R TC T ln
ǒ
ln
Oscillator
V RTńCT(valley) * V ref
ǒ
ln
RT
Ǔ
2.8 V
RT/CT
1.2 V
R TI dischg ) V RTńCT(valley) * V ref
Enable
(eq. 2)
Idischg
CT
The maximum duty ratio, Dmax is given by Equation 3.
D max +
t RTńCT(chg)
t RTńCT(chg) ) t RTńCT(dischg)
Figure 18. Oscillator Configuration
(eq. 3)
Substituting Equations 1 and 2 into Equation 3, and after
algebraic simplification, we obtain
www.onsemi.com
8
UC3842B, UC3843B, UC2842B, UC2843B
Error Amplifier
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
ground−referenced sense resistor RS in series with the
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared to a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
pin 1 where:
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
DC voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 8). The
non−inverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is −2.0 mA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external
loop compensation (Figure 33). The output voltage is offset
by two diode drops (≈1.4 V) and divided by three before it
connects to the non−inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
the Output (Pin 6) when pin 1 is at its lowest state (VOL).
This occurs when the power supply is operating and the load
is removed, or at the beginning of a soft−start interval
(Figures 25, 26). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (VOH) to reach the
comparator’s 1.0 V clamp level:
Rf(min) ≈
Ipk =
V(Pin 1) − 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) =
1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 24. The two external diodes are used to compensate
the internal diodes, yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 28).
3.0 (1.0 V) + 1.4 V
= 8800 W
0.5 mA
Current Sense Comparator and PWM Latch
The UC3842B, UC3843B operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the peak inductor current on a
cycle−by−cycle basis. The Current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
www.onsemi.com
9
UC3842B, UC3843B, UC2842B, UC2843B
VCC
VCC
7(12)
36V
Vref
Reference
Regulator
8(14)
R
2.5V
RT
Vin
+
-
VCC
UVLO
Internal
Bias
R
+
-
3.6V
(See
Text)
VC
7(11)
Vref
UVLO
Output
Q1
Oscillator
CT
4(7)
6(10)
+ 1.0mA
S
Voltage
Feedback
Input 2(3)
Output/
Compensation 1(1)
2R
Q
R
R
Error
Amplifier
Power Ground
PWM
Latch
1.0V
Current Sense
Comparator
GND
5(8)
Current Sense Input
3(5)
5(9)
Pin numbers adjacent to terminals are for the 8-pin dual-in-line package.
Pin numbers in parenthesis are for the D suffix SOIC-14 package.
= Sink Only Positive True Logic
Figure 19. Representative Block Diagram
Capacitor CT
Latch
“Set" Input
Output/
Compensation
Current Sense
Input
Latch
“Reset" Input
Output
Small RT/Large CT
Large RT/Small CT
Figure 20. Timing Diagram
www.onsemi.com
10
RS
UC3842B, UC3843B, UC2842B, UC2843B
Undervoltage Lockout
Design Considerations
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842B,
and 8.4 V/7.6 V for the UCX843B. The Vref comparator
upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX842B makes
it ideally suited in off−line converter applications where
efficient bootstrap startup techniques are required
(Figure 35). The UCX843B is intended for lower voltage
DC−to−DC converter applications. A 36 V Zener is
connected as a shunt regulator from VCC to ground. Its
purpose is to protect the IC from excessive voltage that can
occur during system startup. The minimum operating
voltage (VCC) for the UCX842B is 11 V and 8.2 V for the
UCX843B.
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull−down resistor.
The SOIC−14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level. The separate VC supply input allows the
designer added flexibility in tailoring the drive voltage
independent of VCC. A Zener clamp is typically connected
to this input when driving power MOSFETs in systems
where VCC is greater than 20 V. Figure 27 shows proper
power and control ground connections in a current−sensing
power MOSFET application.
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise−generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 21A
shows the phenomenon graphically. At t0, switch
conduction begins, causing the inductor current to rise at a
slope of m1. This slope is a function of the input voltage
divided by the inductance. At t1, the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m2, until the next oscillator cycle. The unstable
condition can be shown if a perturbation is added to the
control voltage, resulting in a small DI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turn−on (t2) is increased
by DI + DI m2/m1. The minimum current at the next cycle
(t3) decreases to (DI + DI m2/m1) (m2/m1). This perturbation
is multiplied by m2/m1 on each succeeding cycle, alternately
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m2/m1 is greater than 1, the converter
will be unstable. Figure 21B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the DI perturbation will decrease to zero
on succeeding cycles. This compensating ramp (m3) must
have a slope equal to or slightly greater than m2/2 for
stability. With m2/2 slope compensation, the average
inductor current follows the control voltage, yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 34).
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short−
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
www.onsemi.com
11
UC3842B, UC3843B, UC2842B, UC2843B
(A)
DI
Control Voltage
m2
m1
Inductor
Current
Dl ) Dl m2
m1
Dl ) Dl m2 m2
m1 m1
Vref
8(14)
Oscillator Period
t0
t1
t2
External
Sync
Input
m3
DI
Bias
RT
t3
(B)
Control Voltage
R
R
Osc
4(7)
CT
+
0.01
2R
m1
2(3)
47
m2
Inductor
Current
R
EA
1(1)
5(9)
Oscillator Period
t4
t5
The diode clamp is required if the Sync amplitude is large enough to cause the bottom
side of CT to go more than 300 mV below ground.
t6
Figure 21. Continuous Current Waveforms
Figure 22. External Clock Synchronization
VCC
Vin
7(12)
5.0V Ref
8(14)
8(14)
6
Q1
Osc
5.0k
3
5.0k
2
7(11)
+
-
R
4
4(7)
Osc
R
5
R
Bias
8
+
-
Bias
R
RA
RB
R
4(7)
Q
Q
2R
S
S
1.0 mA
+
7
R
2R
R
EA
2(3)
1.0V
C
5.0k
MC1455
2(3)
EA
6(10)
VClamp
+
R2
5(8)
Comp/Latch
R
3(5)
1(1)
1
R1
5(9)
1(1)
f +
1.44
(RA ) 2RB)C
D(max) +
RB
RA ) 2RB
5(9)
To Additional
UCX84XBs
Figure 23. External Duty Cycle Clamp and
Multi−Unit Synchronization
VClamp ≈
1.67
ǒ
Ǔ
R2
)1
R1
+ 0.33x10-3
ǒR1R)1R2R2Ǔ
Where: 0 ≤ VClamp ≤ 1.0 V
Ipk(max) [
VClamp
RS
Figure 24. Adjustable Reduction of Clamp Level
www.onsemi.com
12
RS
UC3842B, UC3843B, UC2842B, UC2843B
VCC
Vin
7(12)
5.0V Ref
8(14)
+
-
R
Bias
5.0V Ref
8(14)
R
7(11)
+
-
R
Bias
Q1
Osc
R
4(7)
Q
Q
EA
C
1.0V
R1
3(5)
MPSA63
VClamp [
tSoftStart + * In 1 *
Figure 25. Soft−Start Circuit
VCC
1.67
ǒRR21 ) 1Ǔ
ƪ
C
5(9)
Where: 0 ≤ VClamp ≤ 1.0 V
ƫ
R1R2
VC
C
R1 ) R2
3VClamp
Ipk(max) [
VClamp
RS
Figure 26. Adjustable Buffered Reduction of
Clamp Level with Soft−Start
Vin
VPin 5 [
(12)
RS Ipk rDS(on)
rDM(on) ) RS
VCC
If: SENSEFET = MTP10N10M
RS = 200
5.0V Ref
Vin
7(12)
Then : VPin5 [ 0.075Ipk
+
-
5.0V Ref
D
(11)
+
-
RS
5(9)
1(1)
tSoft-Start ≈ 3600C in mF
5(8)
Comp/Latch
1(1)
R
2R
R
1.0V
R2
S
1.0mA
2(3)
R
2R
R
EA
2(3)
+
1.0M
S
1.0 mA
Osc
4(7)
6(10)
VClamp
+
+
-
+
-
SENSEFET
S
K
(10)
7(11)
+
-
G
Q1
M
6(10)
S
Q
R
S
(8)
Q
5(8)
R
Comp/Latch
(5)
RS
1/4 W
Power Ground:
To Input Source
Return
Comp/Latch
3(5)
R
C
RS
Control Circuitry Ground:
To Pin (9)
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over-current conditions, a
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 24 and 26.
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
Figure 27. Current Sensing Power MOSFET
Figure 28. Current Waveform Spike Suppression
www.onsemi.com
13
UC3842B, UC3843B, UC2842B, UC2843B
VCC
Vin
IB
7(12)
Vin
+
0
5.0V Ref
+
-
Base Charge
Removal
7(11)
+
-
C1
Rg
Q1
Q1
6(10)
6(10)
S
Q
R
5(8)
5(8)
Comp/Latch
3(5)
RS
3(5)
RS
Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance in
the gate-source circuit.
The totem pole output can furnish negative base current for enhanced
transistor turn-off, with the addition of capacitor C1.
Figure 29. MOSFET Parasitic Oscillations
Figure 30. Bipolar Transistor Drive
Vin
VCC
8(14)
R
Bias
7(12)
R
Isolation
Boundary
Osc
5.0V Ref
4(7)
+
7(11)
+
-
Q1
+
50% DC
Q
5(8)
Ipk +
R
Comp/Latch
2(3)
0
-
6(10)
25% DC
ǒ Ǔ
V(Pin1) * 1.4 NS
Np
3RS
R
3(5)
C
RS
NS
1.0 mA
2R
+
0
S
+
VGS Waveforms
EA
R
1(1)
MCR
101
2N
3905
5(9)
2N
3903
NP
The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two
transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
Figure 31. Isolated MOSFET Drive
Figure 32. Latched Shutdown
www.onsemi.com
14
UC3842B, UC3843B, UC2842B, UC2843B
From VO
2.5V
+
Ri
1.0mA 2R
2(3)
Cf
Rd
EA
Rf
R
1(1)
Rf ≥ 8.8 k
5(9)
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback
converters operating with continuous inductor current.
From VO
2.5V
+
Rp
Cp
1.0mA
Ri
2(3)
Cf
Rd
2R
R
EA
Rf
1(1)
5(9)
Error Amp compensation circuit for stabilizing current mode boost and flyback
topologies operating with continuous inductor current.
Figure 33. Error Amplifier Compensation
VCC
Vin
7(12)
36V
8(14)
RT
RSlope
CT
Rd
+
+
2(3)
Cf
Rf
1(1)
7(11)
Osc
4(7)
1.0mA
Ri
+
-
Bias
R
MPS3904
From VO
5.0V Ref
R
-m
R
EA
R
1.0V
6(10)
S
2R
Q
m
- 3.0m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
Figure 34. Slope Compensation
www.onsemi.com
15
5(8)
Comp/Latch
3(5)
RS
UC3842B, UC3843B, UC2842B, UC2843B
L1
MBR1635
4.7W
+
MDA
202
4.7k
250
3300
pF
56k
115 Vac
T1
2200
+
1000
+
5.0V RTN
MUR110
1N4935
7(12)
+
1N4935
68
1000
+
1000
8(14)
0.01
R
R
10
+
10
+
-12V/0.3A
+
-
Bias
10k
12V/0.3A
+
±12V RTN
1N4937
5.0V Ref
+ L2
47
100
5.0V/4.0A
MUR110
680pF
L3
7(11)
+
-
2.7k
22
1N4937
Osc
4(7)
4700pF
1N5819
S
2(3)
4.7k
100
pF
MTP
4N50
6(10)
+
18k
Q
R
EA
150k
5(8)
1.0k
Comp/Latch
3(5)
1(1)
0.5
470pF
5(9)
Figure 35. 27 W Off−Line Flyback Regulator
Test
Conditions
Results
Line Regulation: 5.0 V
±12 V
Vin = 95 to 130 Vac
D = 50 mV or ± 0.5%
D = 24 mV or ± 0.1%
Load Regulation: 5.0 V
Vin = 115 Vac,
Iout = 1.0 A to 4.0 A
Vin = 115 Vac,
Iout = 100 mA to 300 mA
D = 300 mV or ± 3.0%
±12 V
Output Ripple:
Efficiency
5.0 V
±12 V
L1 - 15 mH at 5.0 A, Coilcraft Z7156
L2, L3 - 25 mH at 5.0 A, Coilcraft Z7157
D = 60 mV or ± 0.25%
Vin = 115 Vac
40 mVpp
80 mVpp
Vin = 115 Vac
70%
All outputs are at nominal load currents, unless otherwise noted
www.onsemi.com
16
T1 - Primary: 45 Turns #26 AWG
Secondary ±12 V: 9 Turns #30 AWG
(2 Strands) Bifiliar Wound
Secondary 5.0 V: 4 Turns (six strands)
#26 Hexfiliar Wound
Secondary Feedback: 10 Turns
#30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35-3C8
Bobbin: Ferroxcube EC35PCB1
Gap: ≈ 0.10" for a primary inductance
of 1.0 mH
UC3842B, UC3843B, UC2842B, UC2843B
ORDERING INFORMATION
Operating Temperature Range
Package
Shipping†
TA = −25° to +85°C
SOIC−14
(Pb−Free)
55 Units/Rail
UC2842BD1G
SOIC−8
(Pb−Free)
98 Units/Rail
UC2842BD1R2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
UC2842BNG
PDIP−8
(Pb−Free)
1000 Units/Rail
PDIP−8
(Pb−Free)
1000 Units/Rail
UC3842BDG
SOIC−14
(Pb−Free)
55 Units/Rail
UC3842BDR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
UC3842BD1G
SOIC−8
(Pb−Free)
98 Units/Rail
UC3842BD1R2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
SOIC−14
(Pb−Free)
2500 Tape & Reel
UC3842BVD1G
SOIC−8
(Pb−Free)
98 Units/Rail
UC3842BVD1R2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
SOIC−14
(Pb−Free)
55 Units/Rail
UC2843BDR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
UC2843BD1G
SOIC−8
(Pb−Free)
98 Units/Rail
SOIC−8
(Pb−Free)
2500 Tape & Reel
PDIP−8
(Pb−Free)
1000 Units/Rail
SOIC−8
(Pb−Free)
2500 Tape & Reel
SOIC−8
(Pb−Free)
2500 Tape & Reel
Device
UC2842BDG
UC3842BNG
UC3842BVDR2G
UC2843BDG
UC2843BD1R2G
TA = 0° to +70°C
TA = −40° to +105°C
TA = −25° to +85°C
TA = −25° to +85°C
UC2843BNG
UC2843DD1R2G
TA = −40° to +85°C
UC2843DDR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
17
UC3842B, UC3843B, UC2842B, UC2843B
ORDERING INFORMATION
Operating Temperature Range
Package
Shipping†
TA = 0° to +70°C
SOIC−14
(Pb−Free)
55 Units/Rail
UC3843BDR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
UC3843BD1G
SOIC−8
(Pb−Free)
98 Units/Rail
UC3843BD1R2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
UC3843BDR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
UC3843BNG
PDIP−8
(Pb−Free)
1000 Units/Rail
SOIC−14
(Pb−Free)
55 Units/Rail
UC3843BVDR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
UC3843BVD1G
SOIC−8
(Pb−Free)
98 Units/Rail
UC3843BVD1R2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
UC3843BVNG
PDIP−8
(Pb−Free)
1000 Units/Rail
Device
UC3843BDG
UC3843BVDG
TA = −40° to +105°C
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
18
UC3842B, UC3843B, UC2842B, UC2843B
MARKING DIAGRAMS
PDIP−8
N SUFFIX
CASE 626
8
8
UC384xBN
AWL
YYWWG
8
UC3843BVN
AWL
YYWWG
1
UC284xBN
AWL
YYWWG
1
1
SOIC−14
D SUFFIX
CASE 751A
14
14
UC384xBDG
AWLYWW
14
UC384xBVDG
AWLYWW
1
14
UC284xBDG
AWLYWW
1
UC2843DDG
AWLYWW
1
1
SOIC−8
D1 SUFFIX
CASE 751
8
8
384xB
ALYW
G
1
8
384xB
ALYWV
G
8
284xB
ALYW
G
1
1
x
A
WL, L
YY, Y
WW, W
G or G
2843D
ALYW
G
1
= 2 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
SENSEFET is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
www.onsemi.com
19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
14X
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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