DATA SHEET
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Silicon Carbide (SiC) Combo
JFET – EliteSiC, Power
N-Channel, TO247-4, 1200 V,
8.8 mohm
www.onsemi.com
TO247-4
CASE 340AN
UG3SC120009K4S
MARKING DIAGRAM
Description
onsemi’s UG3SC120009K4S “Combo-FET” integrates both
a 1200 V SiC JFET and a Low Voltage Si MOSFET into a single
TO247-4 package. This innovative approach allows users to create
circuitry that would enable a normally-off switch while leveraging the
benefits of a normally-on SiC JFET. These benefits include ultra-low
on-resistance (RDS(on)) to minimize conduction losses and the
exceptional robustness characteristic of a simplified JFET device
structure, making it capable of handling the high-energy switching
required in circuit protection applications. For switch-mode power
conversion application, this device provides separate access to the
JFET and MOSFET gates for improved speed control and ease of
paralleling multiple devices.
Features
•
•
•
•
•
•
•
•
•
Single Digit RDS(on)
Normally-off Capability
Improved Speed Control
Improved Parallel Device Operation (3+ FETs)
Operating Temperature: 175 °C (Max)
High Pulse Current Capability
Excellent Device Robustness
Silver-sintered Die Attach for Excellent Thermal Resistance
This Device is Pb-Free, Halogen Free and is RoHS Compliant
1
UG3SC120009K4S
A
YY
WW
ZZZ
4
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Lot ID
PIN CONNECTIONS
D (1)
JG (4)
Typical Applications
•
•
•
•
•
•
UG3SC120009K4S
AYYWW ZZZ
Solid State / Semiconductor Circuit Breaker
Solid State / Semiconductor Relay
Battery Disconnects
Surge Protection
Inrush Current Control
High Power Switch Mode Converters (>25 kW)
G (3)
S (2)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9
of this data sheet.
© Semiconductor Components Industries, LLC, 2024
June, 2025 − Rev. 3
1
Publication Order Number:
UG3SC120009K4S/D
UG3SC120009K4S
MAXIMUM RATINGS
Parameter
Symbol
Drain-source Voltage
VDS
JFET Gate (JG) to Source Voltage
VJGS
MOSFET Gate (G) to Source Voltage
VGS
Test Conditions
Value
Unit
1200
V
DC
−30 to +3
V
AC (Note 1)
−30 to +30
V
DC
−20 to +20
V
AC (f > 1 Hz)
−25 to +25
V
ID
TC < 112 °C
120
A
Pulsed Drain Current (Note 3)
IDM
TC = 25 °C
550
A
Single Pulsed Avalanche Energy (Note 4)
EAS
L = 15 mH, IAS = 8.6 A
555
mJ
Power Dissipation
Ptot
TC = 25 °C
789
W
TJ,max
175
°C
TJ, TSTG
−55 to 175
°C
TL
250
°C
Continuous Drain Current (Note 2)
Maximum Junction Temperature
Operating and Storage Temperature
Max. Lead Temperature for Soldering,
1/8” from Case for 5 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. +30 V ac rating applies for turn-on pulses 1 .
2. Limited by bondwires
3. Pulse width tp limited by TJ,max
4. Starting TJ = 25 °C
THERMAL CHARACTERISTICS
Parameter
Thermal Resistance, Junction-to-Case
Symbol
Test Conditions
RJC
Min
Typ
Max
Unit
−
0.15
0.19
°C/W
Min
Typ
Max
Unit
1200
−
−
V
A
ELECTRICAL CHARACTERISTICS (TJ = +25 °C and VJGS = 0 V unless otherwise specified)
Parameter
Symbol
Test Conditions
TYPICAL PERFORMANCE − STATIC
Drain-source Breakdown Voltage
BVDS
ID = 1 mA, VGS = 0 V
Total Drain Leakage Current
IDSS
VDS = 1200 V, TJ = 25 °C,
VGS = 0 V
−
6
600
VDS = 1200 V, TJ = 175 °C,
VGS = 0 V
−
65
−
Total JFET Gate Leakage Current
IJGSS
VJGS = −20 V, VGS = 12 V
−
15
300
A
Total MOSFET Gate Leakage Current
IGSS
VGS = −20 V / +20 V
−
5
20
A
VJGS = 2 V,
TJ = 25 °C
−
7.6
−
m
TJ = 25 °C
−
8.8
11
TJ = 125 °C
−
13.7
−
TJ = 175 °C
−
18.5
−
−9.3
−7
−4.7
V
Drain-source On-resistance
RDS(on)
VGS = 12 V,
ID = 100 A
JFET Gate Threshold Voltage
VJG(th)
VDS = 5 V, VGS = 12 V, ID = 320 mA
MOSFET Gate Threshold Voltage
VG(th)
VDS = 5 V, VJGS = 0 V, ID = 10 mA
4
4.7
6
V
JFET Gate Resistance
RJG
f = 1 MHz, open drain
−
0.54
−
MOSFET Gate Resistance
RG
f = 1 MHz, open drain
−
3.5
6
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UG3SC120009K4S
ELECTRICAL CHARACTERISTICS (TJ = +25 °C and VJGS = 0 V unless otherwise specified) (continued)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
TYPICAL PERFORMANCE − REVERSE DIODE
Diode Continuous Forward Current (Note 5)
Diode Pulse Current (Note 6)
Forward Voltage
IS
TC < 112 °C
−
−
120
A
IS,pulse
TC = 25 °C
−
−
550
A
VGS = 0 V, IS = 100 A, TJ = 25 °C
−
1.65
2
V
VGS = 0 V, IS = 100 A, TJ = 175 °C
−
2.4
−
VDS = 800 V, IS = 100 A,
VGS = VJGS = 0 V, RJG = 0.7 ,
di/dt = 1200 A/s, TJ = 25 °C
−
785
−
nC
−
119
−
ns
VDS = 800 V, IS = 100 A,
VGS = VJGS = 0 V, RJG = 0.7 ,
di/dt = 1200 A/s, TJ = 150 °C
−
815
−
nC
−
124
−
ns
−
8157
−
pF
−
351
−
−
2
−
−
394
−
pF
−
920
−
pF
VFSD
Reverse Recovery Charge
Qrr
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Time
trr
TYPICAL PERFORMANCE − DYNAMIC WITH MOSFET GATE AS CONTROL TERMINAL AND VJGS = 0 V
MOSFET Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Effective Output Capacitance, Energy Related
Coss(er)
Effective Output Capacitance, Time Related
Coss(tr)
VDS = 800 V, VGS = 0 V,
f = 100 kHz
VDS = 0 V to 800 V, VGS = 0 V
Eoss
VDS = 800 V, VGS = 0 V
−
125
−
J
Total Gate Charge
QG
196
−
nC
QGD
VDS = 800 V, ID = 100 A,
VGS = 0 V to 15 V
−
Gate-drain Charge
−
41
−
Gate-source Charge
QGS
−
41
−
Turn-on Delay Time
td(on)
−
160
−
−
73
−
−
210
−
−
59
−
−
11.5
−
−
2.5
−
−
14
−
−
158
−
−
79
−
−
53
−
−
212
−
−
12.3
−
−
2.8
−
−
15.1
−
−
8110
−
−
368
−
COSS Stored Energy
Rise Time
Turn-off Delay Time
Fall Time
Turn-on Energy
Turn-off Energy
Total Switching Energy
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Turn-on Energy
Turn-off Energy
Total Switching Energy
tr
td(off)
tf
EON
EOFF
Notes 7 and 8
VDS = 800 V, ID = 100 A,
VGS = 0 V to +15 V, RG_ON = 1 ,
RG_OFF = 2 , RJG_ON = 0.7 ,
RJG_OFF = 3.3 , Inductive Load,
FWD: same device with VGS = 0 V,
VJGS = 0 V, RG = 2 ,
RJG_ON = 0.7 , TJ = 25 °C
ETOTAL
td(on)
tr
td(off)
tf
EON
EOFF
Notes 7 and 8
VDS = 800 V, ID = 100 A,
VGS = 0 V to +15 V, RG_ON = 1 ,
RG_OFF = 2 , RJG_ON = 0.7 ,
RJG_OFF = 3.3 , Inductive Load,
FWD: same device with VGS = 0 V,
RG = 2 , VJGS = 0 V,
RJG_ON = 0.7 , TJ = 150 °C
ETOTAL
ns
mJ
ns
mJ
TYPICAL PERFORMANCE − DYNAMIC WITH JFET GATE AS CONTROL TERMINAL AND VGS = +12 V
JFET Input Capacitance
CJiss
JFET Output Capacitance
CJoss
JFET Reverse Transfer Capacitance
CJrss
−
358
−
JFET Total Gate Charge
QJG
−
830
−
JFET Gate-drain Charge
QJGD
−
520
−
JFET Gate-source Charge
QJGS
−
120
−
VDS = 800 V, VJGS = −20 V,
f = 100 kHz
VDS = 800 V, ID = 100 A,
VJGS = −18 V to 0 V
pF
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Limited by bondwires.
6. Pulse width tp limited by TJ,max.
7. Measured with the half-bridge mode switching test circuit in Figure 23.
8. Driven with the ClampDRIVE method as described in the section “Recommended Gate Drive Approach: ClampDRIVE Method”.
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UG3SC120009K4S
300
300
250
250
ID, Drain Current (A)
ID, Drain Current (A)
TYPICAL PERFORMANCE DIAGRAMS − MOSFET GATE AS CONTROL TERMINAL AND VJGS = 0 V
200
Vgs = 15 V
Vgs = 8 V
Vgs = 7 V
Vgs = 6.75 V
Vgs = 6.5 V
Vgs = 6.25 V
150
100
50
200
Vgs = 15 V
Vgs = 10 V
Vgs = 8 V
Vgs = 7 V
Vgs = 6.5 V
Vgs = 6 V
150
100
50
0
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
VDS, Drain-Source Voltage (V)
5
6
7
8
9
10
Figure 2. Typical Output Characteristics at TJ = 25 5C,
tp < 250 ms
2.5
RDS_ON, On Resistance (P.U.)
300
250
ID, Drain Current (A)
4
VDS, Drain-Source Voltage (V)
Figure 1. Typical Output Characteristics at TJ = −55 5C,
tp < 250 ms
200
150
Vgs = 15 V
Vgs = 8 V
Vgs = 7 V
Vgs = 6.5 V
Vgs = 6 V
Vgs = 5.5 V
100
50
0
0
1
2
3
4
5
6
7
8
9
2.0
1.5
1.0
0.5
0.0
−75 −50 −25
10
VDS, Drain-Source Voltage (V)
30
250
50
75 100 125 150 175
Tj = −55 °C
Tj = 25 °C
Tj = 175 °C
200
ID, Drain Current (A)
20
25
Figure 4. Normalized On-Resistance vs.
Temperature at VGS = 12 V and ID = 100 A
Tj = 175 °C
Tj = 125 °C
Tj = 25 °C
Tj = −55 °C
25
0
TJ, Junction Temperature (°C)
Figure 3. Typical Output Characteristics at TJ = 175 5C,
tp < 250 ms
RDS(on), On-Resistance (m)
3
15
10
150
100
50
5
0
0
0
50
100
150
200
250
300
0
ID, Drain Current (A)
1
2
3
4
5
6
7
8
9
10
VGS, MOSFET Gate-Source Voltage (V)
Figure 5. Typical Drain-Source On-Resistances at
VGS = 12 V
Figure 6. Typical Transfer Characteristics at VDS = 5 V
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TYPICAL PERFORMANCE DIAGRAMS − MOSFET GATE AS CONTROL TERMINAL AND VJGS = 0 V
6
20
VGS, Gate-Source Voltage (V)
Vth, MOSFET Threshold Voltage (V)
(CONTINUED)
5
4
3
2
1
0
−100
15
10
5
0
−50
0
50
100
150
200
0
50
TJ, Junction Temperature (°C)
0
Vgs = −5 V
Vgs = 0 V
Vgs = 5 V
Vgs = 8 V
−100
−150
−200
−4
−3
−2
−1
−50
−100
−150
−200
−4
0
−3
−1
0
Figure 10. 3rd Quadrant Characteristics at TJ = 25 5C
300
Vgs = −5 V
Vgs = 0 V
Vgs = 5 V
Vgs = 8 V
250
200
EOSS (J)
ID, Drain Current (A)
−2
VDS, Drain-Source Voltage (V)
Figure 9. 3rd Quadrant Characteristics at TJ = −55 5C
−50
250
Vgs = −5 V
Vgs = 0 V
Vgs = 5 V
Vgs = 8 V
VDS, Drain-Source Voltage (V)
0
200
Figure 8. Typical MOSFET Gate Charge at
VDS = 800 V and ID = 100 A
ID, Drain Current (A)
ID, Drain Current (A)
−50
150
QG, MOSFET Gate Charge (nC)
Figure 7. MOSFET Threshold Voltage vs. Junction
Temperature at VDS = 5 V and ID = 10 mA
0
100
−100
150
100
−150
50
−200
−4
0
−3
−2
−1
0
0
VDS, Drain-Source Voltage (V)
200
400
600
800
1000
1200
VDS, Drain-Source Voltage (V)
Figure 11. 3rd Quadrant Characteristics at TJ = 175 5C
Figure 12. Typical Stored Energy in COSS at VGS = 0 V
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TYPICAL PERFORMANCE DIAGRAMS − MOSFET GATE AS CONTROL TERMINAL AND VJGS = 0 V
(CONTINUED)
1.E+05
140
1.E+03
ID, DC Drain Current (A)
C, Capacitance (pF)
120
Ciss
1.E+04
Coss
1.E+02
1.E+01
1.E+00
200
400
600
800
80
60
40
20
Crss
0
100
1000
0
−75 −50 −25
1200
VDS, Drain-Source Voltage (V)
0
25
50
75
100 125 150 175
TC, Case Temperature (°C)
Figure 13. Typical Capacitances at f = 100 kHz and
VGS = 0 V
Figure 14. DC Drain Current Derating
ZJC, Thermal Impedance (°C/W)
900
Ptot, Power Dissipation (W)
800
1.E−01
700
600
D = 0.5
D = 0.3
D = 0.1
D = 0.05
D = 0.02
D = 0.01
Single Pulse
1.E−02
500
400
300
1.E−03
200
100
0
−75 −50 −25
0
25
50
Symbol
3.100E−03
C1
2.200E−03
R2
3.250E−02
C2
1.050E−02
R3
1.090E−01
C3
4.800E−02
R4
4.540E−02
C4
3.000E+00
1.E−04
1.E−06 1.E−05 1.E−04 1.E−03 1.E−02 1.E−01 1.E+00
75 100 125 150 175
TC, Case Temperature (°C)
tp, Pulse Time (s)
Figure 15. Total Power Dissipation
Figure 16. Maximum Transient Thermal Impedance
1000
900
800
1 s
700
100
600
10 s
10
100 s
1
1 ms
10 ms
DC
Qrr (nC)
ID, Drain Current (A)
Foster Model Parameters
Value (K/W) Symbol Value (Ws/K)
R1
500
400
300
200
VDS = 800 V, IS = 100 A,
di/dt = 1200 A/s, VGS = 0 V,
VJGS = 0 V, RG =2 , RJG = 0.7
100
0
0.1
1
10
100
0
1000
VDS, Drain-Source Voltage (V)
25
50
75
100
125
150
175
TJ, Junction Temperature (°C)
Figure 17. Safe Operation Area at TC = 25 5C, D = 0,
Parameter tp
Figure 18. Reverse Recovery Charge Qrr vs.
Junction Temperature
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TYPICAL PERFORMANCE DIAGRAMS − MOSFET GATE AS CONTROL TERMINAL AND VJGS = 0 V
(CONTINUED)
9
VDS = 800 V, VGS = 0 V/15 V, VJGS = 0 V,
RG_ON = 1 , RG_OFF = 2
RJG_ON = 0.7 , RJG_OFF = 3.3 ,
FWD: same device with VGS = 0 V,
RG = 2 , VJGS = 0 V, RJG = 0.7
15
10
EOFF, Turn-Off Energy (mJ)
Switching Energy (mJ)
20
Etot
Eon
Eoff
5
VGS = 0 V/15 V, VJGS = 0 V, RG_ON = 1 ,
RG_OFF = 2 , FWD: same device with
VGS = 0 V, RG = 2 , VJGS = 0 V, RJG = 0.7
8
7
6
5
4
3
2
1
0
0
0
25
50
75
100
0
125
2
ID, Drain Current (A)
16
14
14
Switching Energy (mJ)
EON, Turn-On Energy (mJ)
16
12
10
8
VGS = 0 V/15 V, VJGS = 0 V, RG_ON = 1 ,
RG_OFF = 2 , FWD: same device with
VGS = 0 V, RG = 2 VJGS = 0 V,
RJG_OFF = 3.3
2
8
10
Figure 20. Clamped Inductive Turn-Off Energy vs.
JFET Gate Resistor RJG_OFF at VDS = 800 V,
ID = 100 A, and TJ = 25 5C
18
4
6
RJG_OFF, JFET Turn-off Resistor ()
Figure 19. Clamped Inductive Switching Energy vs.
Drain Current at TJ = 25 5C
6
4
12
10
Etot
Eon
Eoff
8
6
VGS = 0 V/15 V, VJGS = 0 V
RG_ON = 1 , RG_OFF = 2
RJG_ON = 0.7 , RJG_OFF = 3.3
FWD: same device with VGS = 0 V,
RG = 2 , VJGS = 0 V, RJG = 0.7
4
2
0
0
0
0.5
1
1.5
2
0
25
50
75
100
125
150
175
TJ, Junction Temperature (°C)
RJG_ON, JFET Turn-on Resistor ()
Figure 22. Clamped Inductive Switching Energy vs.
Junction Temperature at VDS = 800 V and ID = 100 A
Figure 21. Clamped Inductive Switching Turn-On
Energy vs. JFET Gate Resistor RJG_ON at VDS = 800 V,
ID = 100 A, and TJ = 25 5C
Figure 23. Schematic of the Half-bridge Mode Switching Test Circuit with ClampDRIVE Method
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300
300
250
250
200
ID, Drain Current (A)
ID, Drain Current (A)
TYPICAL PERFORMANCE DIAGRAMS − JFET GATE AS CONTROL TERMINAL AND VGS = +12 V
VJGS = 2 V
VJGS = 0 V
VJGS = −1 V
VJGS = −2 V
VJGS = −3 V
VJGS = −4 V
VJGS = −5 V
150
100
50
200
VJGS = 2 V
VJGS = 0 V
VJGS = −1 V
VJGS = −2 V
VJGS = −3 V
VJGS = −4 V
VJGS = −5 V
150
100
50
0
0
0
1
2
3
4
5
6
7
8
9
10
0
VDS, Drain-Source Voltage (V)
3
4
5
6
7
8
9
10
Figure 25. Typical Output Characteristics with JFET
Gate as Control at TJ = 25 5C, tp < 250 ms
300
VJGS, Gate-Source Voltage (V)
3
250
ID, Drain Current (A)
2
VDS, Drain-Source Voltage (V)
Figure 24. Typical Output Characteristics with JFET
Gate as Control at TJ = −55 5C, tp < 250 ms
200
VJGS = 2 V
VJGS = 0 V
VJGS = −1 V
VJGS = −2 V
VJGS = −3 V
VJGS = −4 V
VJGS = −5 V
VJGS = −6 V
150
100
50
0
0
−3
−6
−9
−12
−15
−18
0
1
2
3
4
5
6
7
8
9
10
0
VDS, Drain-Source Voltage (V)
200
400
600
800
1000
QJG, JFET Gate Charge (nC)
Figure 26. Typical Output Characteristics with JFET
Gate as Control at TJ = 175 5C, tp < 250 ms
C, JFET Capacitance (pF)
1
Figure 27. Typical JFET Gate Charge at VDS = 800 V
and ID = 100 A
Cjiss
10,000
1,000
Cjoss
Cjrss
100
0
200
400
600
800
1000
1200
VDS, Drain-Source Voltage (V)
Figure 28. Typical JFET Capacitances at f = 100 kHz
and VJGS = −20 V
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RECOMMENDED GATE DRIVE APPROACH: CLAMPDRIVE METHOD
In the on-state, CLAMPDRV is low which turns the
MOSFET M2 off, thus, the effective JFET gate resistance is
RJG_OFF. During the turn-off transient, CLAMPDRV is kept
low until the device is fully off. This means the JFET gate
resistance is RJG_OFF during the turn-off process, and
RGJ_OFF can be used to effectively control turn-off speed.
After the device is fully off, CLAMPDRV is changed to high
level, which turns the MOSFET M2 on.
In the off-state, CLAMPDRV is high and the clamp
MOSFET M2 is in on-state. The effective JFET gate
resistance is equal to the parallel combination of RJG_OFF
and RJG_ON. RJG_ON can be selected small enough to
prevent the reverse recovery issue. During the turn-on
transient, the JFET gate current may flow from the cascode
source through the body diode of the MOSFET M2 and
RJG_ON into the JFET gate, so, the turn-on process is also
determined by RJG_ON.
In summary, the optimum switching performance of the
SiC cascode FETs can be realized with the ClampDRIVE
method by selecting proper JFET gate resistors RJG_ON and
RJG_OFF.
Since both JFET gate and MOSFET gate are accessible,
more parameters and approaches can be used to control the
switching behaviors of the device and make the device
suitable for a wide range applications from solid state circuit
breakers requiring ultra-high current turn-off capability to
motor drives requiring fast switching speed. The
recommended gate drive approach is the ClampDRIVE
method, with which the desired turn-on speed, turn-off
speed and reverse recovery performance can be achieved at
the same time. The main idea of this method is to
dynamically tune the JFET gate resistor value RJG such that,
in the off-state, RJG is small enough not to cause a reverse
recovery issue, and during turn-off transient, RJG is set to
a higher value for the desired turn-off performance. This
method can be easily implemented using a commercial
off-the-shelf gate driver with miller clamp pre-driver output,
as illustrated in Figure 29. VIN is the gate driver input signal.
VO is the gate driver output and CLAMPDRV is the gate
driver miller clamp pre-driver output. M2 is the clamp
MOSFET used to control the JFET gate resistance. The
MOSFET M2 is directly controlled by the CLAMPDRV
signal.
Figure 29. Circuit Schematic and Timing Diagram of the ClampDRIVE Method
ORDERING INFORMATION
Part Number
UG3SC120009K4S
Marking
Package
Shipping†
UG3SC120009K4S
TO247-4 15.90x20.96x5.03, 5.44P
(Pb-Free, Halogen Free)
600 / Tube
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REVISION HISTORY
Revision
Description of Changes
Date
C
Acquired the original Qorvo JFET Division Data Sheet and updated the main document title to
comply with onsemi standards for SiC products.
1/15/2025
3
Converted the Data Sheet to onsemi format.
6/3/2025
www.onsemi.com
10
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PACKAGE DIMENSIONS
TO247−4 15.90x20.96x5.03, 5.44P
CASE 340AN
ISSUE E
DOCUMENT NUMBER:
DESCRIPTION:
98AON86067F
DATE 20 JUN 2025
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
TO247−4 15.90x20.96x5.03, 5.44P
PAGE 1 OF 2
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© Semiconductor Components Industries, LLC, 2025
www.onsemi.com
TO247−4 15.90x20.96x5.03, 5.44P
CASE 340AN
ISSUE E
DOCUMENT NUMBER:
DESCRIPTION:
98AON86067F
DATE 20 JUN 2025
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
TO247−4 15.90x20.96x5.03, 5.44P
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
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purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2025
www.onsemi.com
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