F-51852GNFJ-SLW-AEN

First Edition Mar 4, 2005 LCD Module Technical Specification Final Revision ****** Type No. F-51852GNFJ-SLW-AEN Approved by (Quality Assurance Division) ) Checked by (ACI Engineering Division) ) T.Yuchi Prepared by (ACI Engineering Division) Table of Contents 1. General Specifications .................................................................................................................................. 2 2. Electrical Specifications ............................................................................................................................... 3 3. Optical Specifications ................................................................................................................................. 13 4. I/O Terminal .................................................................................................................................................... 15 5. Test ................................................................................................................................................................... 17 6. Appearance Standards ................................................................................................................................ 18 7. Code System of Production Lot ............................................................................................................... 21 8. Type Number.................................................................................................................................................. 21 9. Applying Precautions .................................................................................................................................. 21 10. Precautions Relating Product Handling................................................................................................ 22 11. Warranty ........................................................................................................................................................ 23 Revision History Rev. Date Page Comment F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 1/23 1. General Specifications Operating Temp. : min. -20°C ~max. 70°C Storage Temp. : min. -30°C ~max. 80°C Dot Pixels : 128 (W) × 64 (H) dots Dot Size : 0.484 (W) × 0.484 (H) mm Dot Pitch : 0.499 (W) × 0.499 (H) mm Viewing Area : 69.0 (W) × 36.5 (H) mm Outline Dimensions : 89.7 (W) × 49.8* (H) × 11.8 (D) mm * Without Flat Cable and LED Cable Weight : 41.2g max. LCD Type : NSD-22662 ( F-STN / Black &White-mode / Transflective ) Viewing Angle : 6:00 Data Transfer : 8-bit parallel data transfer Serial data transfer Backlight : LED Backlight / White Additional Spec. : Winter White Display (Highly Reflective Type Transflective Display) Drawing : Dimensional Outline RoHS regulation : To our best knowledge, this product satisfies material requirement of RoHS regulation. Our company is doing the best efforts to obtain the equivalent certificate from our suppliers. F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 UE-312414 OPTREX CORPORATION Page 2/23 2. Electrical Specifications 2.1. Absolute Maximum Ratings VSS=0V Parameter Supply Voltage (Logic) Supply Voltage (Booster Circuit) Symbol VDD-VSS Conditions - Min. -0.3 Max. 7.0 Units V VSS2 With Double *1 With Triple *1 With Quad *1 *1 -7.0 -6.0 -4.5 -18.0 +0.3 +0.3 +0.3 +0.3 V *1 V5 +0.3 V - -0.3 VDD +0.3 V - -0.3 VDD +0.3 V Supply Voltage 1 V5, VOUT (LCD Drive) Supply Voltage 2 V1, V 2, V 3, V (LCD Drive) 4 Input Voltage VIN Output Voltage VO V *1 Relative to VDD. The relation of VDD ≥V1≥V2≥V3≥V4≥V5>VOUT ;VDD >VSS≥VOUT must be maintained. In case of inputting external LCD driving voltage, LCD drive voltage should start supplying toNJU6676 at the mean time of turning on VDD power supply or after turned on VDD. In use of the voltage boost circuit, the condition that the supply voltage : 18V≥ VDD-VOUT is necessary. Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the voltage converter. 2.2. DC Characteristics Ta=25°C, VSS=0V Parameter Symbol Conditions Min. Typ. Max. Units - 2.2 - 5.5 V Supply Voltage VDD-VSS (Logic) *1 Supply Voltage (Booster Circuit) VSS2 *2 -6.0 - -2.5 V Supply Voltage V5 *2 -18.0 - -6.0 V (LCD Drive) Supply Voltage V1, V 2 *2 0.4×V5 - VDD V V 3, V 4 *2 V5 - 0.6×V5 V VSS2 With Triple *2 -6.0 - -2.5 V With Quad *2 -4.5 - -2.5 VOUT *2 -18.0 - - V VOUT2 Voltage converter off External power supply -18.0 - -6.0 V V5 Voltage regulator off External power supply -18.0 - -6.0 V - - 3.0 % (Booster Circuit) Booster Output Voltage Voltage Regulator Operating Voltage Voltage Follower Operating Voltage Base Voltage VREG% VDD =3.0V "High" Level Input Voltage VIH - 0.8×VDD - VDD V "Low" Level Input Voltage VIL - VSS - 0.2×VDD V F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 3/23 "High" Level Output Voltage VOH IOH =-0.5mA 0.8×VDD - VDD V "Low" Level Output Voltage VOL IOL=0.5mA VSS - 0.2×VDD V Supply Current IDD VDD -V SS=5.0V - 1.06 1.60 mA *1 Although the NJU6676 can operate in wide range of the operation voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with MPU. *2 Relative to VDD. F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 4/23 2.3. AC Characteristics 2.3.1. Read/Write Operation Sequence (80 series CPU) VDD =4.5~5.5V Parameter Address Hold Time Address Setup Time System Cycle Time Control Low Pulse Width(Write) Control Low Pulse Width(Read) Control High Pulse Width(Write) Control High Pulse Width(Read) Data Setup Time Data Hold Time RD Access Time Output Disable Time Input Signal Rise/Fall Time Symbol Min. Max. Units tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 tr, tf 0 - ns 0 - ns 166 - ns 30 - ns 70 - ns 30 - ns 30 - ns 30 - ns 10 - ns - 70 ns 10 50 ns - 15 ns VDD =2.7~4.5V Parameter Address Hold Time Address Setup Time System Cycle Time Control Low Pulse Width(Write) Control Low Pulse Width(Read) Control High Pulse Width(Write) Control High Pulse Width(Read) Data Setup Time Data Hold Time RD Access Time Output Disable Time Input Signal Rise/Fall Time Symbol Min. Max. Units tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 tr, tf 0 - ns 0 - ns 300 - ns 60 - ns 120 - ns 60 - ns 60 - ns 40 - ns 15 - ns - 140 ns 10 100 ns - 15 ns VDD =2.2~2.7V Parameter Address Hold Time Address Setup Time System Cycle Time Control Low Pulse Width(Write) Control Low Pulse Width(Read) Control High Pulse Width(Write) Control High Pulse Width(Read) Data Setup Time F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 Symbol Min. Max. Units tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 0 - ns 0 - ns 1000 - ns 120 - ns 240 - ns 120 - ns 120 - ns 80 - ns OPTREX CORPORATION Page 5/23 tDH8 tACC8 tOH8 tr, tf Data Hold Time RD Access Time Output Disable Time Input Signal Rise/Fall Time 30 - ns - 280 ns 10 200 ns - 15 ns tCYC 8 A0, CS1 t AW 8 t AH8 tCCL WR, RD tCCH tD S8 D0∼D7 (WRITE) tf t DH8 tr tACC8 t OH8 D0∼D7 (READ) F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 6/23 2.3.2. Read/Write Operation Sequence (68 series CPU) VDD =4.5~5.5V Parameter Address Hold Time Address Setup Time System Cycle Time Enable High Pulse Width (Read) Enable High Pulse Width (Write) Enable Low Pulse Width (Read) Enable Low Pulse Width (Write) Data Setup Time Data Hold Time Access Time (CL=100pF) Output Disable Time Input Signal Rise/Fall Time Symbol Min. Max. Units tAH6 tAW6 tCYC6 tEWHR tEWHW tEWLR tEWLW tDS6 tDH6 tACC6 tOH6 tr, tf 0 - ns 0 - ns 166 - ns 70 - ns 30 - ns 30 - ns 30 - ns 30 - ns 10 - ns - 70 ns 10 50 ns - 15 ns VDD =2.7~4.5V Parameter Address Hold Time Address Setup Time System Cycle Time Enable High Pulse Width (Read) Enable High Pulse Width (Write) Enable Low Pulse Width (Read) Enable Low Pulse Width (Write) Data Setup Time Data Hold Time Access Time (CL=100pF) Output Disable Time Input Signal Rise/Fall Time Symbol Min. Max. Units tAH6 tAW6 tCYC6 tEWHR tEWHW tEWLR tEWLW tDS6 tDH6 tACC6 tOH6 tr, tf 0 - ns 0 - ns 300 - ns 120 - ns 60 - ns 60 - ns 60 - ns 40 - ns 15 - ns - 140 ns 10 100 ns - 15 ns VDD =2.2~2.7V Parameter Address Hold Time Address Setup Time System Cycle Time Enable High Pulse Width (Read) Enable High Pulse Width (Write) Enable Low Pulse Width (Read) Enable Low Pulse Width (Write) Data Setup Time F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 Symbol Min. Max. Units tAH6 tAW6 tCYC6 tEWHR tEWHW tEWLR tEWLW tDS6 0 - ns 0 - ns 1000 - ns 240 - ns 120 - ns 120 - ns 120 - ns 80 - ns OPTREX CORPORATION Page 7/23 tDH6 tACC6 tOH6 tr, tf Data Hold Time Access Time (CL=100pF) Output Disable Time Input Signal Rise/Fall Time 30 - ns - 280 ns 10 200 ns - 15 ns tCYC6 RD (E) t EW L tEW H t AW 6 WR (R/W) tr tf t AH6 A0, CS1 t DS6 tDH6 D0∼ D7 (WRITE) tACC6 tOH6 D0∼ D7 (READ) F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 8/23 2.3.3. Serial Interface Sequence VDD =4.5~5.5V Parameter Serial Clock Cycle Serial Clock High Pulse Width Serial Clock Low Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CS-SCL Time Input Signal Rise/Fall Time Symbol Min. Max. Units tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH tr, tf 200 - ns 75 - ns 75 - ns 50 - ns 100 - ns 50 - ns 50 - ns 100 - ns 100 - ns - 15 ns VDD =2.7~4.5V Parameter Serial Clock Cycle Serial Clock High Pulse Width Serial Clock Low Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CS-SCL Time Input Signal Rise/Fall Time Symbol Min. Max. Units tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH tr, tf 250 - ns 100 - ns 100 - ns 150 - ns 150 - ns 100 - ns 100 - ns 150 - ns 150 - ns - 15 ns VDD =2.2~2.7V Parameter Serial Clock Cycle Serial Clock High Pulse Width Serial Clock Low Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CS-SCL Time Input Signal Rise/Fall Time Symbol Min. Max. Units tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH tr, tf 400 - ns 150 - ns 150 - ns 250 - ns 250 - ns 150 - ns 150 - ns 250 - ns 250 - ns - 15 ns Each timing is specified based on 0.2×VDD and 0.8×VDD. F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 9/23 t CSS t CSH CS1 tSAS t SAH A0 t SCYC t SLW D6(SCL) tSHW tSDS D7(SI) tf F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 t SDH tr OPTREX CORPORATION Page 10/23 2.3.4. Display Control Timing Characteristics Reset Input Timing Parameter Reset time Reset ”L” Pulse Width VDD =4.5∼5.5V Symbol Min. Typ. Max. tR - - 0.5 tRW 0.5 - - Reset Input Timing Parameter Reset time Reset ”L” Pulse Width Reset time Reset ”L” Pulse Width µs VDD =4.5∼5.5V Symbol Min. Typ. Max. tR - - 1 tRW 1 - - Reset Input Timing Parameter Units Units µs VDD =4.5∼5.5V Symbol Min. Typ. Max. tR - - 1.5 tRW 1.5 - - Units µs Each timing is specified based on 0.2×VDD and 0.8×VDD. RES tRW Internal states F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 tR During reset Reset complete OPTREX CORPORATION Page 11/23 2.4. Lighting Specifications 2.4.1. Absolute Maximum Ratings Ta=25°C Parameter Symbol Conditions Min. Typ. Max. Units Foward Current IF Note 1 - - 120 mA Reverse Voltage VR - - - 5 V LED Power Dissipation PD - - - 480 mW Note 1 : Refer to the foward current derating curve. IF (mA) 120 48 -20 25 70 Ta ( °C) 2.4.2. Operating Characteristics Parameter Foward Voltage Luminance of Symbol Conditions Min. Typ. Max. Units VF IF =60mA - 3.5 4.0 V L IF =60mA 28 48 - cd/m2 Module Surface F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 12/23 3. Optical Specifications 3.1. LCD Driving Voltage Parameter Symbol Recommended LCD Driving Voltage VDD -V 5 Note 1 Conditions Min. Typ. Max. Units Ta= -20°C - - 13.9 V Ta=25°C 12.2 13.2 14.1 V Ta=70°C 11.8 - - V Note 1 : Voltage (Applied actual waveform to LCD Module) for the best contrast. The range of minimum and maximum shows tolerance of the operating voltage. The specified contrast ratio and response time are not guaranteed over the entire range. 3.2. Optical Characteristics Ta=25°C, 1/65 Duty, 1/9 Bias, VOD =13.2V (Note 4), θ= 0°, φ=-° Parameter Contrast Ratio Note 1 Symbol Conditions Min. Typ. Max. CR θ= 0°C , φ=-° - 4.5 - Viewing Angle Response Time Units Shown in 3.3 Rise Note 2 TON - - 150 230 ms Decay Note 3 TOFF - - 200 300 ms Note 1 :Contrast ratio is definded as follows. (CR = LON / LOFF) LON : Luminance of the ON segments LOFF: Luminance of the OFF segments Measuring Spot : 3.0mmφ Note 2 :The time that the luminance level reaches 90% of the saturation level from 0% when ON signal is applied. Note 3 :The time that the luminance level reaches 10% of the saturation level from 100% when OFF signal is applied. Note 4 :Definition of Driving Voltage VOD VOD =VCC -V ADJ-V BE Assuming that the typical driving waveforms shown below are applied to the LCD Panel at 1/A Duty - 1/B Bias (A: Duty Number, B: Bias Number). Driving voltage VOD is definded as follows. VOD = (Vth1+Vth2) / 2 Vth1: The voltage VO-P that should provide 70% of the saturation level in the luminance at the segment which the ON signal is applied to. Vth2: The voltage VO-P that should provide 20% of the saturation level in the luminance at the segment which the OFF signal is applied to. Vo-p ( B-2 ) ×Vo-p/B 1/( f F× A ) ( ON SIGNAL ) F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 1 /f F ( OFF SIGNAL ) OPTREX CORPORATION Page 13/23 3.3. Definition of Viewing Angle and Optimum Viewing Area *Point • shows the point where contrast ratio is measured. : θ= 0°, φ=-° *Driving condition: 1/65 Duty, 1/9 Bias, VOD =13.2V, fF =84.6Hz 90° 45° 135° θ φ 180° 10 20 30 40 50 90° ( φ = 0° ) θ φ 180° 225° 0° 315° 270° 270° *Area   shows typ. CR≥2(Measuring Spot : 3.0mmφ) 3.4. System Block Diagram Temperature Chamber Rotation Table ( θ,φ ) Photometer #1980A WB φ LCD Optical Fiber θ Computer Control Unit & Waveform Generator Halogen bulb F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 14/23 4. I/O Terminal 4.1. Pin Assignment CN1 No. Symbol Function 1 CS1 Chip Select Signal L : Active 2 RES Reset Signal L : Reset 3 A0 H : D0~D7 are Display Data L : D0~D7 are Instructions 4 WR 80 family CPU : Write Signal L : Active 5 RD 80 family CPU : Read Signal L : Active 6 D0 Display Data 7 D1 Display Data 8 D2 Display Data 9 D3 Display Data 10 D4 Display Data 11 D5 Display Data 12 D6(SCL) 13 D7(SI) 14 VDD Power Supply for Logic 15 VSS Power Supply ( 0V, GND ) 16 VOUT DC/DC Voltage Converter Output 17 C3- DC/DC Voltage Converter Negative Connection 18 C1+ DC/DC Voltage Converter Positive Connection 19 C1- DC/DC Voltage Converter Negative Connection 20 C2- DC/DC Voltage Converter Negative Connection 21 C2+ DC/DC Voltage Converter Positive Connection 22 V1 Power Supply for LCD Drive V1 = 1/9⋅V5 23 V2 Power Supply for LCD Drive V2 = 2/9⋅V5 24 V3 Power Supply for LCD Drive V3 = 7/9⋅V5 25 V4 Power Supply for LCD Drive V4 = 8/9⋅V5 26 V5 Power Supply for LCD Drive V5, VOUT 27 VR Voltage Adjustment Pin Display Data(Serial Data Clock Signal Input) Display Data(Serial Data Input) Applies voltage between VCC and V5 using a resistive divider. 28 C86 Interface Mode Select Signal H : 68 series L : 80 series 29 P/S Parallel/Serial Data Select Signal H : Parallel L : Serial 30 NC Non-connection CN2 No. Symbol Function 1 LED A LED Anode Terminal 2 LED K LED Cathode Terminal F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 15/23 4.2. Block Diagram CS1 RES A0 WR RD D0∼D7 8 VDD VSS COM 64 VOUT C3- LCDP Control LSI 128 × 64 dots C1+ C1- NJU6676 SEG 128 C2C2+ V1 V2 V3 V4 V5 VR C86 P/S LED A LED Backlight LED K F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 16/23 5. Test No change on display and in operation under the following test condition. Conditions: No. Unless otherwise specified, tests will be conducted under the following condition. Temperature: 20±5°C Humidity : 65±5%RH tests will be not conducted under functioning state. Parameter Conditions Notes 1 High Temperature Operating 70°C±2°C, 96hrs (operation state) 2 Low Temperature Operating -20°C±2°C, 96hrs (operation state) 1 3 High Temperature Storage 80°C±2°C, 96hrs 2 4 Low Temperature Storage -30°C±2°C, 96hrs 1,2 5 Damp Proof Test 40°C±2°C,90~95%RH, 96hrs 1,2 6 Vibration Test Total fixed amplitude : 1.5mm 3 Vibration Frequency : 10~55Hz One cycle 60 seconds to 3 directions of X, Y, Z for each 15 minutes 7 Shock Test To be measured after dropping from 60cm high on the concrete surface in packing state. Dropping method corner dropping F E G B D A corner : once Edge dropping C A 60cm B,C,D edge : once Face dropping E,F,G face : once Concrete Surface Note 1 :No dew condensation to be observed. Note 2 :The function test shall be conducted after 4 hours storage at the normal Temperature and humidity after removed from the test chamber. Note 3 :Vibration test will be conducted to the product itself without putting it in a container. F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 17/23 6. Appearance Standards 6.1. Inspection conditions The LCD shall be inspected under 40W white fluorescent light. The distance between the eyes and the sample shall be more than 30cm. All directions for inspecting the sample should be within 45°against perpendicular line. 45° 6.2. Definition of applicable Zones X X X A Zone B Zone X C Zone X : Maximum Seal Line A Zone : Active display area B Zone : Out of active display area ~ Maximum seal line C Zone : Rest parts A Zone + B Zone = Validity viewing area F-51852GNFJ-SLW-AEN (AE) No. 2005-0268 OPTREX CORPORATION Page 18/23 6.3. Standards(middle scale, LED) D = ( Long + Short ) / 2 No. 1 Parameter The Shape of Dot * : Disregard Units : mm Criteria (1) Pin Hole Dimension Acceptable Number D ≤ 0.10 0.10 < D ≤ 0.20 * 1 pc / dot or less 5 pcs / cell or less (2) Breakage or Chips / Deformation 1.Dot Type Dimension A Acceptable Number A≤0.10 * (Should not be connected to next dot) 1 pc / dot(only segment)or less B 0.10