TVL-55682D101U-LW-I-AAN 数据手册
Document Title
TVL-55682D101U-LW-I-AAN Product Specification
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Issue Date 2013/02/21 Revision
Product
00
Information
To:
Product Name:
TVL-55682D101U-LW-I-AAN
Document Issue Date: 2013/02/21
Note: 1. Please contact Kyocera Display before designing your product based on this product.
2. The information contained herein is presented merely to indicate the characteristics and
performance of our products. No responsibility is assumed by KYOCERA DISPLAY for any
intellectual property claims or other problems that may result from application based on the
module described herein.
________________________________________________________________________
KYOCERA DISPLAY CORPORATION
5-7-18,Higashi Nippori,
Arakawa-ku, Tokyo, Japan 116-0014
Tel: +81-3-5811-8780
Fax:+81-3-5811-8782
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FQ-7-30-0-009-02C
Revision
Date
Page
Old Description
New Description
00
2011/05/10
All
--
First issued
Remark
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KYOCERA DISPLAY CORPORATION
5-7-18,Higashi Nippori,
Arakawa-ku, Tokyo, Japan 116-0014
Tel: +81-3-5811-8780
Fax:+81-3-5811-8782
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Contents
1
GENERAL DESCRIPTIONS ············································································································································ 4
2
ABSOLUTE MAXIMUM RATINGS ··································································································································· 7
3
ELECTRICAL SPECIFICATION······································································································································· 8
4
OPTICAL CHARACTERISTICS ····································································································································· 17
5
MECHANICAL CHARACTERISTICS····························································································································· 21
6
PACKAGE SPECIFICATION·········································································································································· 24
7
LOT MARK····································································································································································· 25
8
GENERAL PRECAUTION ············································································································································· 26
9
EDID DATA STRUCTURE ············································································································································· 29
________________________________________________________________________
KYOCERA DISPLAY CORPORATION
5-7-18,Higashi Nippori,
Arakawa-ku, Tokyo, Japan 116-0014
Tel: +81-3-5811-8780
Fax:+81-3-5811-8782
Page 3 of 33
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General Descriptions
1.1 Introduction
The TVL-55682AAN is a Color Active Matrix Thin Film Transistor (TFT) Liquid Crystal
Display (LCD) module, which uses amorphous Silicon TFT as a switching device. It is
composed of a TFT LCD panel, a timing controller, voltage reference, common voltage, column
driver, and row driver circuit. This TFT LCD has a 10.1-inch (diagonally measured) active
display area with WSVGA resolution (1,024 vertical by 600 horizontal pixel array).
1.2 Features
■ 10.1” TFT LCD Panel
■ LED Light-bar Backlight System
■ Supports WSVGA (V:1,024 lines, H:600 pixels) Resolution
■ Compatible with RoHS Standard
1.3 Product Summary
Items
Specifications
Unit
Screen Diagonal
10.1
inch
Active Area
222.72(H) x 125.28(V)
mm
Pixels(H x V)
1,024 (x3) x 600
-
Pixel Pitch
0.2175(H) x 0.2088(V)
mm
Pixel Arrangement
R.G.B. Vertical Stripe
-
Display Mode
TN Mode, Normally White
-
White Luminance
200 (Typ.)
cd/ m
Contrast Ratio
500 (Typ.)
-
Response Time
8 (Typ.)
ms
View Angle(L/R/U/D)
45/45/15/35 (Typ.)
-
Input Voltage
+3.3 (Typ.)
V
Power Consumption
2.4
Watt
Module Weight
190 (Max.)
g
Outline Dimension(H x V x D)
235.5(H) x 143.5(V) x 5.2(D) (Max.)
mm
Electrical Interface (Logic)
LVDS
-
Support Color
262 K
-
NTSC
45 (Typ.)
%
Optimum Viewing Direction
6 o’clock
-
Surface Treatment
Anti-Glare
-
2
Remark
5 Points Average,
20mA per LED
Black Pattern
________________________________________________________________________
KYOCERA DISPLAY CORPORATION
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Arakawa-ku, Tokyo, Japan 116-0014
Tel: +81-3-5811-8780
Fax:+81-3-5811-8782
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1.4 Functional Block Diagram
Figure 1 shows the functional block diagram of the LCD module.
Figure 1 Block Diagram
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1.5 Pixel Format Image
Figure 2 shows the relationship of the input signals and LCD pixel format image.
Figure 2 Pixel Format
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Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to
the LCD module.
Table 1
Item
Symbol
Min.
Max.
Unit
VDD
-0.3
4.0
V
-
V_LED
5
21
V
-
-
-0.3
2.7
V
LVDS Signals
Operating Temperature
TOP
0
50
℃
Note(3)
Operating Humidity
HOP
10
80
%RH
Note(3)
Storage Temperature
TST
-20
60
℃
Note(3)
Storage Humidity
HST
10
90
%RH
Note(3)
Level
-
1.5
G
Bandwidth
-
10~500Hz
Hz
Shock
Level
-
220
G
LED Current
I_LED
-
20.5
mA
Supply Voltage
Supply V_LED Voltage
Input Signal
Vibration
Conditions
30min. for X, Y, Z axis
Half Sine Waveform, 2ms
Per LED
Note
(1)Maximum Wet-Bulb should be 39℃ and No condensation.
(2)When you apply the LCD module for OA system, please make sure to keep the
temperature of LCD module under 60 ℃.
(3)Storage /Operating temperature & humidity:
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KYOCERA DISPLAY CORPORATION
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Arakawa-ku, Tokyo, Japan 116-0014
Tel: +81-3-5811-8780
Fax:+81-3-5811-8782
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Electrical Specification
3.1
Electrical Characteristics
Table 2 Electrical Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Units
Condition
VDD
Logic/LCD Drive Voltage
3
3.3
3.6
V
Note (1)
IDD
VDD Current
-
160
-
mA
Black Pattern, 60Hz
PDD
VDD Power
-
-
0.53
W
Black Pattern, 60Hz
Irush
Rush Current
-
-
2
A
Note (2)
-
-
300
mVp-p
-
VDDrp
Allowable Logic/LCD Drive
Ripple Voltage
V_LED
LED Input
5
12
21
V
-
VF
LED Forward Voltage
2.95
3.3
3.4
V
-
IF
LED Forward Current
19.5
20
20.5
mA
-
PLED
LED Power Consumption
-
-
1.87
W
Note(3)
LT
LED Life Time
10,000
-
-
Hours
Note(4)
VPWM_EN
FPWM
V_LED_EN
PWM
PWM Signal
High
2
3.3
3.6
V
Voltage
Low
0
-
0.5
V
Output PWM Frequency
-
200
1K
Hz
LED Enable
High
2
3.3
3.6
V
Voltage
Low
0
-
0.5
V
5
-
100
%
PWM Duty Ratio
-
Note: (1)VDD Power Dip Condition
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Figure 3 VDD Power Dip
If VTH<VDD≤Vmin and td≤10ms, our panel must revive automatically when the voltage
returns to normal.
(2)Measure Condition
Figure 4 VDD rising time
(3) PLED is calculation value for reference. PLED =24 x VF (Normal Distribution) x IF
(Normal Distribution) / Efficiency
(4) The lifetime of LED is defined as the time when LED packages continue to operate
under the conditions at Ta = 25℃ and IF= 20 mA (per chip) until the brightness
becomes≦50% of its original value.
(5)All values are measured at condition of V_LED =12V and Ta=25℃.
________________________________________________________________________
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Arakawa-ku, Tokyo, Japan 116-0014
Tel: +81-3-5811-8780
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Interface Connector
Table 3 Connector Name / Designation
Manufacturer
I-PEX (or equivalent)
Mating Receptacle/Part Number
20453-040T(I-PEX)
Table 4 Signal Pin Assignment
Pin #
Signal Name
Description
1
GND
Ground
2
VDD
Power Supply 3.3V (Typ.)
3
VDD
Power Supply 3.3V (Typ.)
4
VEDID
EDID +3.3V Power
5
NC
Not Connected(Reserve)
6
CLK_EDID
EDID Clock Input
7
DAT_EDID
EDID Data Input
8
RXin0-
-LVDS
Differential Data Input(R0-R5,G0)
9
RXin0+
+LVDS
Differential Data Input(R0-R5,G0)
10
GND
Ground
11
RXin1-
-LVDS
Differential Data Input(G1-G5,B0-B1)
12
RXin1+
+LVDS
Differential Data Input(G1-G5,B0-B1)
13
GND
Ground
14
RXin2-
-LVDS
Differential Data Input(B2-B5,HS,VS,DE)
15
RXin2+
+LVDS
Differential Data Input(B2-B5,HS,VS,DE)
16
GND
Ground
17
CLKN-
-LVDS
Differential Clock Input
18
CLKN+
+LVDS
Differential Clock Input
19
NC
Not Connected(Reserve)
20
NC
Not Connected(Reserve)
21
NC
Not Connected(Reserve)
22
GND
Ground-Shield
23
NC
Not Connected(Reserve)
24
NC
Not Connected(Reserve)
25
GND
Ground-Shield
26
NC
Not Connected(Reserve)
Remarks
LCD panel self test enable
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Tel: +81-3-5811-8780
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27
NC
Not Connected(Reserve)
28
GND
Ground-Shield
29
NC
Not Connected(Reserve)
30
NC
Not Connected(Reserve)
31
V_LED_GND
LED Ground
32
V_LED_GND
LED Ground
33
V_LED_GND
LED Ground
34
NC
Not Connected(Reserve)
35
VPWM_EN
System PWM Logic Input Level
36
V_LED_EN
LED Enable Input Level(+3.3V)
37
NC
Not Connected(Reserve)
38
V_LED
LED Power Supply 5-21V
39
V_LED
LED Power Supply 5-21V
40
V_LED
LED Power Supply 5-21V
00
Note: All input signals shall be at low or Hi-Z state when VDD is off.
3.3
LVDS Receiver
3.3.1 Signal Electrical Characteristics For LVDS Receiver
The built-in LVDS receiver is compatible with (ANSI/TIA/TIA-644 ) standard.
Table 5 LVDS Receiver Electrical Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Differential Input High Threshold
Vth
-
-
+100
mV
Vcm=+1.2V
Differential Input Low Threshold
Vtl
-100
-
-
mV
Vcm=+1.2V
Magnitude Differential Input Voltage
|Vid|
100
-
600
mV
Common Mode Voltage
Vcm
|Vid/2|+0.6
1.2
1.8-|Vid/2|
V
∆Vcm
-
-
50
mV
Common Mode Voltage Offset
Conditions
Vcm=+1.2V
Note:
(1)Input signals shall be at low or Hi-Z state when VDD is off.
(2)All electrical characteristics for LVDS signal are defined and shall be measured at the
interface connector of LCD.
(3)All values are measured at condition of VDD =3.3V and Ta=25℃.
________________________________________________________________________
KYOCERA DISPLAY CORPORATION
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Tel: +81-3-5811-8780
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Figure 5 Voltage Definitions
Figure 6 Measurement System
Figure 7 Data mapping
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3.3.2 LVDS Receiver Internal Circuit
Figure 8 LVDS Receiver Internal Circuit shows the internal block diagram of the LVDS
receiver. This LCD module equips termination resistors for LVDS link.
Figure 8 LVDS Receiver Internal Circuit
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3.4 Interface Timings
Table 6 Interface Timings
Parameter
Symbol
Unit
Min.
Typ.
Max.
LVDS Clock Frequency(single)
Fdck
MHz
44.4
50.4
65.2
H Total Time
Htotal
Clocks 1,320
1,344
1,362
H Active Time
Hac
Clocks 1,024
1,024
1,024
V Total Time
Vtotal
Lines
612
625
638
V Active Time
Vac
Lines
600
600
600
Vsync
Hz
55
60
65
Frame Rate
Figure 9 Timing Characteristics
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Note: TES is data enable signal setup time.
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3.5 Power ON/OFF Sequence
VDD power, interface signals, and lamp on/off sequence are showing on Figure 10.
Signals shall be Hi-Z state or low level when VDD is off.
Figure 10
Table 7 Power Sequencing Requirements
Parameter
Symbol
Min.
Typ.
Max.
Unit
VDD Rising Time
T1
0.5
-
10
ms
VDD Good to Signal Valid
T2
30
-
90
ms
Signal Valid to Backlight on
T3
200
-
-
ms
Backlight Power on Time
T4
0.5
-
-
ms
Backlight VDD Good to System PWM on
T5
10
-
-
ms
System PWM on to Backlight Enable on
T6
10
-
-
ms
Backlight Enable off to System PWM off
T7
0
-
-
ms
System PWM off to B/L Power Disable
T8
10
-
-
ms
Backlight Power off Time
T9
-
10
30
ms
Backlight off to Signal Disable
T10
200
-
-
ms
Signal Disable to Power Down
T11
0
-
50
ms
VDD Falling Time
T12
-
10
30
ms
Power off
T13
500
-
-
ms
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Optical Characteristics
The optical characteristics are measured under stable conditions as following notes.
Table 8 Optical Characteristics
Item
Specification
Conditions
Min.
Typ.
Max.
Unit
Left
40
45
-
Deg.
[degrees]
Right
40
45
-
Deg.
K=Contrast
Up
10
15
-
Deg.
Down
30
35
-
Deg.
Center
400
500
-
-
Rising
-
3
-
ms
Falling
-
5
-
ms
Rising + Falling
-
8
16
ms
(1),(4)
Viewing Angle
Horizontal
Vertical
Ratio>10
Contrast Ratio
Response Time
Note
(1),(2)
(1),(3)
Red
x
0.579
-
(1)
Red
y
0.346
-
(1)
Green
x
Typ.
0.336
Typ.
-
(1)
Green
y
-0.03
0.560
+0.03
-
(1)
Blue
x
0.156
-
(1)
Blue
y
0.123
-
(1)
White
x
0.283
0.313
0.343
-
(1)
White
y
0.299
0.329
0.359
-
(1)
I_LED =20.0mA
180
200
-
cd/m
Luminance
I_LED =20mA, 13points
62.5
-
-
Uniformity [%]
I_LED =20mA, 5points
80.0
-
-
Color
Chromaticity
(CIE1931)
White
Luminance
2
(1), (5)
[cd/m^2]
-
(1), (6)
Note: (1)Measurement Setup
The LCD module should be stabilized at 25℃ for 15 minutes to avoid abrupt
temperature change during measuring. In order to stabilize the luminance, the
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measurement should be executed after lighting backlight for 15 minutes in a windless
room.
Figure 11 Measurement Setup
LCD Module
LCD Panel
Photo meter (DMS 1140)
Center of the Screen
Light Shield Room
44 mm
*Ambient Luminance