PAM8408DR

A PRODUCT LINE OF DIODES INCORPORATED PAM8408 2x3W STEREO DIFFERENTIAL INPUT CLASS D AUDIO AMPLIFIER WITH MEMORY UP/DOWN VOLUME Description Pin Assignments The PAM8408 is a filter-less Class-D amplifier with high SNR and SO-16L differential input that helps eliminate noise. Advanced 32-step Up/Down volume control minimizes external components and allows NEW PRODUCT shutdown mode. The PAM8408 supports 2.5V to 6V operation make it idea for up to 4 cells alkaline battery applications. Features like greater than 87% efficiency and small PCB area make the PAM8408 Class-D amplifier ideal for portable applications. The output uses a filter-less architecture minimizing the number of 1 2 PAM8408 XX XY W WLL RINP RINN SD UP DOWN GND LINN LINP speaker volume control. The gain will held when the chip is in 3 4 5 6 7 8 16 VDD 15 ROUTP 14 ROUTN 13 GND 12 GND 11 LOUTN 10 LOUTP 9 VDD external components and PCB area whilst providing a high performance, simple and lower cost system. The PAM8408 built in auto recovery SCP (short circuit protection) and thermal shutdown. The PAM8408 is available in SO-16L package. Features • Applications • PC Speaker • Wireless Speaker • Home Sound Systems • Active Speakers • Docking Stations 3W Output at 10% THD with a 4Ω Load and 5V Supply • 2.4W Output at 1% THD with a 4Ω Load and 5V Supply • 2.5V to 6.0V VDD Operating • Fully Differential Input • Filter-less, Low Quiescent Current and Low EMI • Low THD+N • 32-Step Memory Up/Down Volume Control from -80dB to 24dB • Superior Low Noise: 60uV • Minimize Pop/Clip Noise • Auto Recovery Short Circuit Protection • Thermal Shutdown • Pb-Free SO-16L Package Typical Applications Circuit RINP RINN C5 0. 1uF C6 0. 1uF ON SHDN 1 RINP VDD 16 2 RINN ROUTP 15 3 SD ROUTN 14 4 UP 5 DOWN 6 GND C7 LINN LINP 0. 1uF C8 0. 1uF PAM8408 Document number: DS36992 Rev. 1 - 2 7 LINN 8 LINP PAM8408 V DD C2 1uF 4Ω GND 13 GND 12 LOUTN 11 LOUTP 10 VDD 9 1 of 11 www.diodes.com 4Ω C2 1uF V DD June 2014 © Diodes Incorporated A PRODUCT LINE OF DIODES INCORPORATED PAM8408 NEW PRODUCT Pin Descriptions Pin Number 1 2 3 4 5 Pin Name RINP RINN SD UP DOWN Function Positive Input of Right Channel Power Amplifier Negative Input of Right Channel Power Amplifier Full Chip Shutdown Control Input (active low) Volume UP Control (active low)Ground Connection Volume down Control (active low) 6,12,13 7 8 9,16 10 11 14 GND LINN LINP VDD LOUTP LOUTN ROUTN Ground Negative Input of Left Channel Power Amplifier Positive Input of Left Channel Power Amplifier Power Supply Positive Output of Left Channel Power Amplifier Negative Output of Left Channel Power Amplifier Negative Output of Right Channel Power Amplifier 15 ROUTP Positive Output of Right Channel Power Amplifier Functional Block Diagram GN D VDD R IN P + R IN N - R OU T N VD D DOWN Thermal Protection A tte n u a ti o n D e c o d e r VD D I n t e rf a c e C o n t r o l UP R OU T P DRIVER MODULATOR INTERNAL OSCI LLATOR VD D BIAS AND REFERENCES SD OSC Current Protection LI N N + LI N P - MODULATOR LO U T N D R IVER LO U T P VDD G ND Absolute Maximum Ratings (@TA = +25°C, unless otherwise specified.) Parameter Supply Voltage (VDD) Pins Input Voltage (SD, UP, Down, IN) Rating 6.5 -0.3 to VDD+0.3 V -65 to 150 °C 150 40 °C °C/W Storage Temperature Maximum Junction Temperature Junction to ambient thermal resistance PAM8408 Document number: DS36992 Rev. 1 - 2 Unit V 2 of 11 www.diodes.com June 2014 © Diodes Incorporated A PRODUCT LINE OF DIODES INCORPORATED PAM8408 NEW PRODUCT Recommended Operating Conditions (@TA = +25°C, unless otherwise specified.) Symbol Parameter Min Max Unit VDD Supply Voltage 2.5 6.0 V TA Operating Ambient Temperature Range -40 85 °C TJ Junction Temperature Range -40 125 °C Electrical Characteristics (@TA = +25°C, VDD = 5V, Gain = 24dB, RL = 8Ω (33μH)+R+L(33μH), unless otherwise noted.) Parameter Supply Voltage Range Quiescent Current Output Offset Voltage Drain-Source On-State Resistance Output Power Symbol IQ No Load No Load RDS(ON) PO THD+N Power Supply Ripple Rejection PSRR Channel Separation CS Oscillator Frequency fOSC Noise η Vn IDS = 0.5A THD+N = 1%, f = 1kHz Units 6.0 V mA mV P MOSFET N MOSFET 0.3 0.2 RL= 8Ω 1.4 RL= 4Ω 2.4 RL = 8Ω，PO=0.85W,f=1KHz 0.08 RL = 4Ω，PO=1.75W,f=1KHz 0.08 Ω W % Input AC-GND, f=1KHz, Vpp=200mV 70 dB PO=1W, f=1KHz -95 dB 200 250 300 kHz PO = 1.1W, f = 1kHz, RL = 8Ω 87 % PO = 2.4W, f = 1kHz, RL = 4Ω 83 % A-weighting No A-weighting Input AC-GND F = 20 - 20kHz, THD = 1% VDD = 5V Mute Current IMUTE MUTE = VDD Shutdown Current ISD VSD = 0V Logic Input High VIH Include SD,UP,DOWN Logic Input Low VIL Include SD,UP,DOWN Document number: DS36992 Rev. 1 - 2 Max 8 SNR Ton PAM8408 Typ 10 Signal Noise Ratio Turn-on Time Over Temperature Protection Over Temperature Hysteresis Min 2.5 VOS Total Harmonic Distortion Plus Noise Efficiency Conditions VDD OTP OTH 60 80 95 0.65 4 dB S 10 mA 5 µA 0.6 V 1.4 V 150 40 3 of 11 www.diodes.com uV °C °C June 2014 © Diodes Incorporated A PRODUCT LINE OF DIODES INCORPORATED PAM8408 Performance Characteristics (@TA = +25°C, VDD = 5V, Gain = 24dB, RL = 8Ω (33μH)+R+L(33μH), unless otherwise noted.) THD+N Vs. Output Power (RL=8Ω) THD+N Vs. Output Power (RL=4Ω) 20 NEW PRODUCT 10 5 40 20 f=100Hz/1kHz/10kHz (Red/Pink/Blue) 10 5 f=100Hz/1kHz/10kHz (Red/Pink/Blue) 2 2 1 1 0.5 % % 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.01 1m 0.02 2m 5m 10m 20m 50m 100m 200m 500m 1 2 0.01 1m 3 2m 5m 10m 20m 50m 100m THD+N Vs. Frequency (RL=8Ω) 500m 1 2 5 THD+N Vs. Frequency (RL=4Ω) 10 10 5 2 200m W W 5 PO=0.3W/0.5W/1W (Red/Pink/Blue) PO=0.5W/1W/2W (Red/Pink/Blue) 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.008 20 50 100 200 500 1k 2k 5k 10k 0.01 20 20k 50 100 200 500 1k 2k 5k 10k 20k Hz Hz PSRR Vs. Frequency Crosstalk Vs Frequency +0 +0 -5 -10 -10 T -20 -15 -30 -20 -40 -25 -50 -30 -60 -35 d B d B -40 -45 -70 L to R -80 -50 -90 -55 -100 -60 -110 -65 -120 -70 -75 -80 20 R to L -130 50 100 200 500 1k 2k 5k 10k 20k Hz PAM8408 Document number: DS36992 Rev. 1 - 2 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz 4 of 11 www.diodes.com June 2014 © Diodes Incorporated A PRODUCT LINE OF DIODES INCORPORATED PAM8408 Performance Characteristics (cont.) (@TA = +25°C, VDD = 5V, Gain = 24dB, RL = 8Ω (33μH)+R+L(33μH), unless otherwise noted.) NEW PRODUCT Frequency Response Noise Floor +16 +14 +0 CIN = 1µF CIN = 0.47µF -10 -20 -30 +12 -40 -50 +10 d B g +8 CIN = 0.1µF A d B r -60 A -80 +6 -70 -90 -100 +4 -110 -120 +2 -130 +0 20 50 100 200 500 1k 2k 5k 10k -140 20 20k Efficiency vs. Output Power (RL = 8Ω) 200 500 1k 2k 5k 10k 20k VDD = 5V Output Power vs. Supply Voltage (RL = 8Ω, THD = 10%) Document number: DS36992 Rev. 1 - 2 100 Efficiency vs. Output Power (RL = 4Ω) VDD = 5V PAM8408 50 Hz Hz Output Power vs. Supply Voltage (RL = 4Ω,THD = 10%) 5 of 11 www.diodes.com June 2014 © Diodes Incorporated A PRODUCT LINE OF DIODES INCORPORATED PAM8408 Performance Characteristics (cont.) (@TA = +25°C, VDD = 5V, Gain = 24dB, RL = 8Ω (33μH)+R+L(33μH), unless otherwise noted.) OSC Frequency vs. Supply Voltage NEW PRODUCT Quiescent Current vs. Supply Voltage Rdson vs. Output Current NMOS PAM8408 Document number: DS36992 Rev. 1 - 2 Up/Down Volume Control (dB) PMOS STEP Gain STEP 1 24 12 2 22.5 13 3 21 14 4 19.5 15 5 18 16 6 16.5 17 7 15 18 8 13.5 19 9 12* 20 10 10.36 21 11 9 22 *Default Gain = 12dB 6 of 11 www.diodes.com Gain 7.5 6 4.5 3 1.5 0 -1.5 -3 -4.5 -6 -8 STEP 23 24 25 26 27 28 29 30 31 32 - Gain -10 -12 -14 -16 -18 -20 -22 -24 -26 -80 - June 2014 © Diodes Incorporated A PRODUCT LINE OF DIODES INCORPORATED PAM8408 Application Information Maximum Gain As shown in block diagram, the PAM8408 has two internal amplifiers stage. The first stage's gain is externally con-figurable, while the second stage's is internally fixed in a fixed-gain, inverting configuration. The closed-loop gain of the first stage is set by selecting the ratio of Rf to Ri while NEW PRODUCT the second stage's gain is fixed at 2x. Consequently, the differential gain for the IC is AVD=20*log [2*(Rf/Ri)] The PAM8408 sets maximum Rf=218kΩ and minimum Ri=27kΩ, thus the maximum closed-gain is 24dB. UP/DOWN Volume Control (DVC) The PAM8408 features a UP/DOWN volume control which consists of the UP and DOWN pins. An internal clock is used where the clock frequency value is determined from the following formula: 13 fCLK = fOSC / 2 The oscillator frequency fOSC value is 250kHz typical with ±20% tolerance. The DVC’s clock frequency is 30Hz (cycle time 33ms) typical. Volume changes are then effected by toggling either the UP or DOWN pins with a logic low. After a period of 1 cycle pulses with either the UP or DOWN pins held low, the volume will change to the next specified step, either UP or DOWN, and followed by a short delay. This delay decreases the longer the line is held low, eventually reaching a delay of zero. The delay allows the user to pull the UP or DOWN terminal low once for one volume change, or hold down to ramp several volume changes. The delay is optimally configured for push button volume control. If either the UP or DOWN pin remains low after the first volume transition the volume will change again, but this time after 10 cycles. The followed transition occurs at 4 cycles for each volume transition. This is intended to provide the user with a volume control that pauses briefly after initial application, and then slowly increases the rate of volume change as it is continuously applied. This cycle is shown in the timing diagram shown in figure 1. There are 32 discrete gain settings ranging from +24dB as maximum to -80dB as minimum. Upon device power on, the amplifier's gain is set to a default value of 12dB, and the gain will remain when applied a logic low to the SD pin, Volume levels for each step vary and are specified in Gain Setting table on page 7. If both the UP and DOWN pins are held high, no volume change will occur. Trigger points for the UP and DOWN pins are at 70% of VDD minimum for a logic high, and 20% of VDD maximum for a logic low. It is recommended, however, to toggle UP and DOWN between VDD and GND for best performance. U P/D N VOL U ME L EVEL 1 c y c le 4 c y c le s 1 0 c y c le s 4 c y c le s Figure 1 Timming Diagram Shutdown Operation In order to reduce power consumption while not in use, the PAM8408 contains shutdown circuitry that is used to turn off the amplifier's bias circuitry. This shutdown feature turns the amplifier off when logic low is placed on the SD pin. By switching the SD pin connected to GND, the PAM8408 supply current draw will be minimized in idle mode. The SD pin cannot be left floating due to the pull-down internal. Power Supply decoupling The PAM8408 is a high performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output THD and PSRR are as low as possible. Power supply decoupling is affecting low frequency response. Optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1.0µF, placed as close as possible to the device VDD terminal works best. For filtering lower-frequency noise signals, a larger capacitor of 10µF (ceramic) or greater placed near the audio power amplifier is recommended. PAM8408 Document number: DS36992 Rev. 1 - 2 7 of 11 www.diodes.com June 2014 © Diodes Incorporated A PRODUCT LINE OF DIODES INCORPORATED PAM8408 Application Information (cont.) Input Capacitor (Ci) Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized capacitor is needed to couple in low frequencies without severe attenu-ation. But in many cases the speakers used in portable systems, whether internal or external, have little ability NEW PRODUCT to reproduce signals below 100Hz to 150Hz. Thus, using a large input capacitor may not increase actual system perfor-mance. In this case, input capacitor (Ci) and input resistance (Ri) of the amplifier form a high-pass filter with the corner frequency determined equation below, fC= 1 2πRiCi In addition to system cost and size, click and pop perfor-mance is affected by the size of the input coupling capacitor, Ci. A larger input coupling capacitor requires more charge to reach its quiescent DC voltage (nominally 1/2 VDD). This charge comes from the internal circuit via the feedback and is apt to create pops upon device enable. Thus, by minimizing the capacitor size based on necessary low frequency response, turnon pops can be minimized. Under Voltage Lock-Out (UVLO) The PAM8408 incorporates circuitry designed to detect when the supply voltage is low. When the supply voltage drops to 2.4V or below, the PAM8408 outputs are disable, and the device comes out of this state and starts to normal functional when the supply voltage increases. Short Circuit Protection (SCP) The PAM8408 has short circuit protection circuitry on the outputs that prevents damage to the device during output-to-output and output-to-GND short. When a short circuit is detected on the outputs, the outputs are disable immediately. If the short was removed, the device activates again. Over Temperature Protection Thermal protection on the PAM8408 prevents damage to the device when the internal die temperature exceeds 150°C. There is a 15 degree tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 60°C. This large hysteresis will prevent motor boating sound well and the device begins normal operation at this point with no external system interaction. How to Reduce EMI (Electro Magnetic Interference) A simple solution is to put an additional capacitor 1000µF at power supply terminal for power line coupling if the traces from amplifier to speakers are short (