PI7C9X7954BFDE

PI7C9X7954 PCI Express® Quad UART Datasheet Revision 2 October 2017 1545 Barber Lane Milpitas, CA 95035 Telephone: 408-232-9100 FAX: 408-435-1100 Internet: http://www.diodes.com Document Number DS40138 Rev 2-2 PI7C9X7954 IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. 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Copyright © 2016, Diodes Incorporated www.diodes.com PI7C9X7954 Document Number DS40138 Rev 2-2 Page 2 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 REVISION HISTORY Date 10/31/07 Revision Number 0.1 12/20/2007 0.2 04/22/08 0.3 08/13/08 0.4 11/25/08 1.0 03/06/09 1.1 04/21/09 09/24/09 1.2 1.3 06/04/14 1.4 01/09/15 05/11/15 1.5 1.6 08/30/17 1.7 10/06/17 2 PI7C9X7954 Document Number DS40138 Rev 2-2 Description Preliminary Datasheet Fixed the diagrams Corrected Section 4.2 Pin Description (RREF, GPIO[7]) Updated Section 6 PCI Express Registers(6.2.42 [3], 6.2.36 UART Driver Setting, 6.2.41 GPIO Control Register ) Revised Section 7.1 Registers in I/O Mode Updated Section 11 Ordering Info Updated Section 4 Pin Assignment (description for shared pins added, MODE_SEL changed to DRIVER_SEL) Updated Section 6 PCI Express Register Description Updated Section 7 UART Register Description Updated Section 8 EEPROM Interface Updated Section 1 Features (Clock prescaler, Data frame size, Power Dissipation) Corrected Section 3 General Description Updated Section 4 Pin Assignment (description for shared pins added, MODE_SEL changed to DRIVER_SEL, VAUX changed to VDDCAUX, WAKEUP_L, CLKINP, CLKINN) Added 5.2.4 Mode Selection, 5.2.5 450/550 Mode, 5.2.6 Enhanced 550 Mode, 5.2.7 Enhanced 950 Mode Corrected 5.2.8 Transmit and Receive FIFOs, 5.2.9 Automated Flow Control Modified 5.2.12 Baud Rate Generation Updated Section 6 PCI Express Register Description (6.2.36, 6.2.42) Updated Format (6.2.20, 6.2.36, 6.2.54, 6.2.55, 6.2.57) Updated Section 7 UART Register Description (7.1.6 LCR Bit[5:0], 7.1.7 MCR Bit[5] and Bit[7], 7.1.9 MSR Bit[3:0], 7.2.6 LCR Bit[5:0], 7.2.7 MCR Bit[5] and Bit[7], 7.2.9 MSR Bit[3:0], 7.2.11 DLL, 7.2.12 DLH, 7.2.13 EFR, 7.2.18 ACR Bit[7:2], 7.2.23 CPRM) Updated Chapter 8.3 EEPROM Space Address Map And Description (00h, 0Ah, 40h) Added Section 9 Electrical Specification Corrected Section 9.2 DC Specification Updated Section 9.3 AC Specification Added Section 10 Clock Scheme Updated Section 1 Features (added Industrial Temperature Range) Updated 9.1 Absolute Maximum Ratings: Ambient Temperature with power applied Updated 7.1.13 Sample Clock Register and 7.2.27 Sample Clock Register Updated Chapter 12 Ordering Information Removed “Preliminary” and “Confidential” references Corrected Figure 3-1 PI7C9X7954 Block Diagram (SYN_UART_CLK removed) Corrected Section 4.2.1 UART Interface (SYNCLK_IN_EN and SYN_UART_CLK removed) Corrected Figure 5-2 Internal Loopback in PI7C7954 Corrected Figure 5-3 Crystal Oscillator as the Clock Source (14.7456 MHz) Corrected Section 7.1.7 Modem Control Register (Bit[5]), 7.1.10 Special Function Register (Bit[4]), 7.2.7 Modem Control Register (Bit[5]), 7.2.10 Special Function Register (Bit[4]), 7.2.29 Receive FIFO Data Registers, 7.2.30 Transmit FIFO Data Register, 7.2.31 Updated Section 4 Pin Description Updated Figure 5-3 Crystal Oscillator as the Clock Source Updated Section 6.2.24 Message Signaled Interrupt (MSI) Next Item Pointer 8Ch Added Section 6.2.25 Message Address Register – Offset 90h Added Section 6.2.26 Message Upper Address Register – Offset 94h Added Section 6.2.27 Message Data Register – Offset 98h Updated Section 4.1 Pin List (SR_DO and SR_DI) Updated Section 4.2.5 EEPROM Interface (SR_DO and SR_DI) Created for IC Revision B Updated Section 12 Ordering Information Added Section 6.2.25 Message Control Register – OFFSET 8Ch Updated Section 11 Package Information Updated Table 5-2 Baud Rate Generator Setting Updated Section 7.2.23 Clock Prescale Register –Offset 14h Updated Section 4.1.PIN LIST OF 128-PIN LQFP Updated Section 4.2.1 UART Interface Updated Table 9.1 Absolute Maximum Ratings Updated Table 9.2 DC Electrical Characteristics Updated Section 12 Ordering Information Revision numbering system changed to whole number Page 3 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 Table of Contents 1. FEATURES ..............................................................................................................................................9 2. APPLICATIONS .....................................................................................................................................9 3. GENERAL DESCRIPTION .................................................................................................................10 4. PIN ASSIGNMENT............................................................................................................................... 11 4.1. PIN LIST OF 128-PIN LQFP........................................................................................................... 11 4.2. PIN DESCRIPTION ........................................................................................................................12 4.2.1. UART INTERFACE ..................................................................................................................12 4.2.2. PCI EXPRESS INTERFACE ....................................................................................................13 4.2.3. SYSTEM INTERFACE .............................................................................................................14 4.2.4. TEST SIGNALS ........................................................................................................................14 4.2.5. EEPROM INTERFACE ............................................................................................................15 4.2.6. POWER PINS ..........................................................................................................................15 5. FUNCTIONAL DESCRIPTION ..........................................................................................................16 5.1. CONFIGURATION SPACE ............................................................................................................16 5.1.1. PCI Express Configuration Space ...........................................................................................16 5.1.2. UART Configuration Space .....................................................................................................16 5.2. DEVICE OPERATION....................................................................................................................17 5.2.1. Configuration Access ...............................................................................................................17 5.2.2. I/O Reads/Writes ......................................................................................................................17 5.2.3. Memory Reads/Writes ..............................................................................................................17 5.2.4. Mode Selection ........................................................................................................................18 5.2.5. 450/550 Mode ..........................................................................................................................18 5.2.6. Enhanced 550 Mode ................................................................................................................18 5.2.7. Enhanced 950 Mode ................................................................................................................18 5.2.8. Transmit and Receive FIFOs ...................................................................................................18 5.2.9. Automated Flow Control .........................................................................................................20 5.2.10. Internal Loopback....................................................................................................................21 5.2.11. Crystal Oscillator ....................................................................................................................22 5.2.12. Baud Rate Generation .............................................................................................................23 5.2.13. Power Management .................................................................................................................23 6. PCI EXPRESS REGISTER DESCRIPTION .....................................................................................24 6.1. REGISTER TYPES .........................................................................................................................24 6.2. CONFIGURATION REGISTERS ...................................................................................................24 6.2.1. VENDOR ID REGISTER – OFFSET 00h ................................................................................25 6.2.2. DEVICE ID REGISTER – OFFSET 00h .................................................................................25 6.2.3. COMMAND REGISTER – OFFSET 04h .................................................................................25 6.2.4. STATUS REGISTER – OFFSET 04h .......................................................................................26 6.2.5. REVISION ID REGISTER – OFFSET 08h ..............................................................................26 6.2.6. CLASS CODE REGISTER – OFFSET 08h ..............................................................................26 6.2.7. CACHE LINE REGISTER – OFFSET 0Ch .............................................................................27 6.2.8. MASTER LATENCY TIMER REGISTER – OFFSET 0Ch .......................................................27 6.2.9. HEADER TYPE REGISTER – OFFSET 0Ch ..........................................................................27 6.2.10. BASE ADDRESS REGISTER 0 – OFFSET 10h.......................................................................27 6.2.11. BASE ADDRESS REGISTER 1 – OFFSET 14h.......................................................................27 6.2.12. SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch ..............................................................27 6.2.13. SUBSYSTEM ID REGISTER – OFFSET 2Ch .........................................................................27 6.2.14. CAPABILITIES POINTER REGISTER – OFFSET 34h ...........................................................28 PI7C9X7954 Document Number DS40138 Rev 2-2 Page 4 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6.2.15. 6.2.16. 6.2.17. 6.2.18. 6.2.19. 6.2.20. 6.2.21. 6.2.22. 6.2.23. 6.2.24. 6.2.25. 6.2.26. 6.2.27. 6.2.28. 6.2.29. 6.2.30. 6.2.31. 6.2.32. 6.2.33. 6.2.34. 6.2.35. 6.2.36. 6.2.37. 6.2.38. 6.2.39. 6.2.40. 6.2.41. 6.2.42. 6.2.43. 6.2.44. 6.2.45. 6.2.46. 6.2.47. 6.2.48. 6.2.49. 6.2.50. 6.2.51. 6.2.52. 6.2.53. 6.2.54. 6.2.55. 6.2.56. 6.2.57. 100h 6.2.58. 6.2.59. 6.2.60. 6.2.61. 6.2.62. 6.2.63. 6.2.64. 6.2.65. 6.2.66. 7. INTERRUPT LINE REGISTER – OFFSET 3Ch......................................................................28 INTERRUPT PIN REGISTER – OFFSET 3Ch ........................................................................28 POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h.................................28 NEXT ITEM POINTER REGISTER – OFFSET 80h................................................................28 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h ..................................28 POWER MANAGEMENT DATA REGISTER – OFFSET 84h .................................................29 PPB SUPPORT EXTENSIONS – OFFSET 84h ......................................................................29 PM DATA REGISTER – OFFSET 84h.....................................................................................29 MESSAGE SIGNALED INTERRUPTS (MSI) Capability ID Register 8Ch .............................29 MESSAGE SIGNALED INTERRUPTS (MSI) NEXT ITEM POINTER 8Ch ............................29 MESSAGE CONTROL REGISTER – OFFSET 8Ch ................................................................30 MESSAGE ADDRESS REGISTER – OFFSET 90h .................................................................30 MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h ....................................................30 MESSAGE DATA REGISTER – OFFSET 98h .........................................................................30 VPD CAPABILITY ID REGISTER – OFFSET 9Ch .................................................................30 NEXT ITEM POINTER REGISTER – OFFSET 9Ch ...............................................................30 VPD REGISTER – OFFSET 9Ch ............................................................................................30 VPD DATA REGISTER – OFFSET A0h ..................................................................................31 VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h .......................................31 NEXT ITEM POINTER REGISTER – OFFSET A4h ...............................................................31 LENGTH REGISTER – OFFSET A4h .....................................................................................31 XPIP CSR0 – OFFSET A8h (Test Purpose Only) ....................................................................31 XPIP CSR1 – OFFSET ACh (Test Purpose Only) ...................................................................31 REPLAY TIME-OUT COUNTER – OFFSET B0h ...................................................................32 ACKNOWLEDGE LATENCY TIMER – OFFSET B0h ............................................................32 UART DRIVER SETTING – OFFSET B4h ..............................................................................32 POWER MANAGEMENT CONTROL PARAMETER – OFFSET B8h.....................................33 DEBUG REGISTER 1 – OFFSET BCh (Test Purpose Only) ..................................................33 DEBUG REGISTER 2 – OFFSET C0h (Test Purpose Only) ...................................................33 DEBUG REGISTER 3 – OFFSET C4h (Test Purpose Only) ...................................................33 DEBUG REGISTER 4 – OFFSET C8h (Test Purpose Only) ...................................................33 GPIO CONTROL REGISTER – OFFSET D8h........................................................................33 EEPROM CONTROL REGISTER – OFFSET DCh.................................................................34 PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h ..................................................34 NEXT ITEM POINTER REGISTER – OFFSET E0h ...............................................................34 PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h ...................................................34 DEVICE CAPABILITIES REGISTER – OFFSET E4h.............................................................35 DEVICE CONTROL REGISTER – OFFSET E8h ...................................................................35 DEVICE STATUS REGISTER – OFFSET E8h ........................................................................36 LINK CAPABILITIES REGISTER – OFFSET ECh .................................................................36 LINK CONTROL REGISTER – OFFSET F0h .........................................................................37 LINK STATUS REGISTER – OFFSET F0h .............................................................................37 PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 38 CAPABILITY VERSION – OFFSET 100h ................................................................................38 NEXT ITEM POINTER REGISTER – OFFSET 100h..............................................................38 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h.......................................38 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .........................................39 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ..................................40 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h ............................................41 CORRECTABLE ERROR MASK REGISTER – OFFSET 114h ...............................................41 ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h...............41 HEADER LOG REGISTER – OFFSET From 11Ch to 128h ...................................................42 UART REGISTER DESCRIPTION ....................................................................................................43 PI7C9X7954 Document Number DS40138 Rev 2-2 Page 5 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 7.1. REGISTERS IN I/O MODE ............................................................................................................43 7.1.1. RECEIVE HOLDING REGISTER – OFFSET 00h ..................................................................44 7.1.2. TRANSMIT HOLDING REGISTER – OFFSET 00h ................................................................44 7.1.3. INTERRUPT ENABLE REGISTER – OFFSET 01h ................................................................44 7.1.4. INTERRUPT STATUS REGISTER – OFFSET 02h..................................................................45 7.1.5. FIFO CONTROL REGISTER – OFFSET 02h .........................................................................45 7.1.6. LINE CONTROL REGISTER – OFFSET 03h .........................................................................46 7.1.7. MODEM CONTROL REGISTER – OFFSET 04h ...................................................................46 7.1.8. LINE STATUS REGISTER – OFFSET 05h ..............................................................................47 7.1.9. MODEM STATUS REGISTER – OFFSET 06h ........................................................................48 7.1.10. SPECIAL FUNCTION REGISTER – OFFSET 07h .................................................................48 7.1.11. DIVISOR LATCH LOW REGISTER – OFFSET 00h, LCR[7] = 1 ..........................................49 7.1.12. DIVISOR LATCH HIGH REGISTER – OFFSET 01h, LCR[7] = 1 ........................................49 7.1.13. SAMPLE CLOCK REGISTER – OFFSET 02h, LCR[7] = 1 ...................................................49 7.2. REGISTERS IN MEMORY-MAPPING MODE .............................................................................50 7.2.1. RECEIVE HOLDING REGISTER – OFFSET 00h ..................................................................51 7.2.2. TRANSMIT HOLDING REGISTER – OFFSET 00h ................................................................52 7.2.3. INTERRUPT ENABLE REGISTER – OFFSET 01h ................................................................52 7.2.4. INTERRUPT STATUS REGISTER – OFFSET 02h..................................................................52 7.2.5. FIFO CONTROL REGISTER – OFFSET 02h .........................................................................53 7.2.6. LINE CONTROL REGISTER – OFFSET 03h .........................................................................53 7.2.7. MODEM CONTROL REGISTER – OFFSET 04h ...................................................................54 7.2.8. LINE STATUS REGISTER – OFFSET 05h ..............................................................................54 7.2.9. MODEM STATUS REGISTER – OFFSET 06h ........................................................................55 7.2.10. SPECIAL FUNCTION REGISTER – OFFSET 07h .................................................................56 7.2.11. DIVISOR LATCH LOW REGISTER – OFFSET 08h ...............................................................56 7.2.12. DIVISOR LATCH HIGH REGISTER – OFFSET 09h .............................................................56 7.2.13. ENHANCED FUNCTION REGISTER – OFFSET 0Ah ...........................................................56 7.2.14. XON SPECIAL CHARACTER 1 – OFFSET 0Bh.....................................................................57 7.2.15. XON SPECIAL CHARACTER 2 – OFFSET 0Ch ....................................................................58 7.2.16. XOFF SPECIAL CHARACTER 1 – OFFSET 0Dh ..................................................................58 7.2.17. XOFF SPECIAL CHARACTER 2 – OFFSET 0Eh ..................................................................58 7.2.18. ADVANCE CONTROL REGISTER – OFFSET 0Fh ................................................................58 7.2.19. TRANSMIT INTERRUPT TRIGGER LEVEL – OFFSET 10h .................................................59 7.2.20. RECEIVE INTERRUPT TRIGGER LEVEL – OFFSET 11h ....................................................59 7.2.21. FLOW CONTROL LOW TRIGGER LEVEL – OFFSET 12h ...................................................59 7.2.22. FLOW CONTROL HIGH TRIGGER LEVEL – OFFSET 13h .................................................59 7.2.23. CLOCK PRESCALE REGISTER – OFFSET 14h ....................................................................59 7.2.24. RECEIVE FIFO DATA COUNTER – OFFSET 15h, SFR[6] = 0 ............................................59 7.2.25. LINE STATUS REGISTER COUNTER – OFFSET 15h, SFR[6] = 1 ......................................60 7.2.26. TRANSMIT FIFO DATA COUNTER – OFFSET 16h, SFR[7] = 1 .........................................60 7.2.27. SAMPLE CLOCK REGISTER – OFFSET 16h, SFR[7] = 0 ...................................................60 7.2.28. GLOBAL LINE STATUS REGISTER – OFFSET 17h ..............................................................60 7.2.29. RECEIVE FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh ................................................61 7.2.30. TRANSMIT FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh .............................................61 7.2.31. LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh ....................................................61 8. EEPROM INTERFACE .......................................................................................................................62 8.1. 8.2. 8.3. 9. AUTO MODE EERPOM ACCESS .................................................................................................62 EEPROM MODE AT RESET ..........................................................................................................62 EEPROM SPACE ADDRESS MAP AND DESCRIPTION ............................................................62 ELECTRICAL SPECIFICATION.......................................................................................................64 9.1. ABSOLUTE MAXIMUM RATINGS .............................................................................................64 PI7C9X7954 Document Number DS40138 Rev 2-2 Page 6 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 9.2. 9.3. DC SPECIFICATIONS....................................................................................................................64 AC SPECIFICATIONS....................................................................................................................64 10. CLOCK SCHEME ............................................................................................................................67 11. PACKAGE INFORMATION ...........................................................................................................68 12. ORDER INFORMATION ................................................................................................................69 PI7C9X7954 Document Number DS40138 Rev 2-2 Page 7 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 Table of Tables TABLE 4-1 PIN-LIST OF 128-PIN LQFP ............................................................................................................ 11 TABLE 5-1 MODE SELECTION ...........................................................................................................................18 TABLE 5-2 BAUD RATE GENERATOR SETTING ..................................................................................................23 TABLE 5-3 SAMPLE BAUD RATE SETTING.........................................................................................................23 TABLE 7-1 UART BASE ADDRESS IN I/O MODE ...............................................................................................43 TABLE 7-2 REGISTERS IN I/O MODE .................................................................................................................44 TABLE 7-3 UART BASE ADDRESS IN MEMORY MODE .....................................................................................50 TABLE 7-4 MEMORY-MAP MODE .....................................................................................................................51 TABLE 9-1 ABSOLUTE MAXIMUM RATINGS ......................................................................................................64 TABLE 9-2 DC ELECTRICAL CHARACTERISTICS ...............................................................................................64 TABLE 9-3 TRANSMITTER CHARACTERISTICS...................................................................................................64 TABLE 9-4 RECEIVER CHARACTERISTICS .........................................................................................................65 TABLE 10-1 INPUT CLOCK REQUIREMENTS ......................................................................................................67 List of Figures FIGURE 3-1 PI7C9X7954 BLOCK DIAGRAM ....................................................................................................10 FIGURE 5-1 TRANSMIT AND RECEIVE FIFOS ....................................................................................................19 FIGURE 5-2 INTERNAL LOOPBACK IN PI7C9X7954 ..........................................................................................21 FIGURE 5-3 CRYSTAL OSCILLATOR AS THE CLOCK SOURCE .............................................................................22 FIGURE 5-4 EXTERNAL CLOCK SOURCE AS THE CLOCK SOURCE......................................................................22 FIGURE 7-1 UART REGISTER BLOCK ARRANGEMENT IN I/O MODE ................................................................43 FIGURE 7-2 UART REGISTER BLOCK ARRANGEMENT IN MEMORY MODE .......................................................50 FIGURE 11-1 PACKAGE OUTLINE DRAWING......................................................................................................68 PI7C9X7954 Document Number DS40138 Rev 2-2 Page 8 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 1. FEATURES                      x1 PCI Express link host interface Four high performance 950-class UARTs Compliant with PCI Express Base Specification 1.1 Compliant with PCI Express CEM Specification 1.1 Compliant with PCI Power Management 1.2 Fully 16C550 software compatible UARTs 128-byte FIFO for each transmitter and receiver Baud rate up to 15 Mbps in asynchronous mode Flexible clock prescaler from 4 to 46 Automated in-band flow control using programmable Xon/Xoff in both directions Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR# Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and out-of-band flow control Global Interrupt Status and readable FIFO levels to facilitate implementation of efficient device drivers Detection of bad data in the receiver FIFO Data framing size including 5, 6, 7, 8 and 9 bits Hardware reconfiguration through Microwire compatible EEPROM Operations via I/O or memory mapping Dual power operation (1.8V for PCIe I/O and core, 3.3V for UART I/O) Power dissipation: 0.8 W typical in normal mode Industrial Temperature Range -40o to 85o 128-pin LQFP, Pb-free and 100% Green 2. APPLICATIONS            Remote Access Servers Network / Storage Management Factory Automation and Process Control Instrumentation Multi-port RS-232/ RS-422/ RS-485 Cards Point-of-Sale Systems (PoS) Industrial PC (IPC) Industrial Control Gaming Machines Building Automation Embedded Systems PI7C9X7954 Document Number DS40138 Rev 2-2 Page 9 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 3. GENERAL DESCRIPTION The PI7C9X7954 is a PCI Express Quad UART (Universal Asynchronous Receiver-Transmitters) I/O Bridge. It is specifically designed to meet the latest system requirements of high performance and lead (Pb) -free. The bridge can be used in a wide range of applications such as Remote Access Servers, Automation, Process Control, Instrumentation, POS, ATM and Multi-port RS232/ RS422/ RS485 Cards. The PI7C9X7954 provides one x1 PCIe (dual simplex 2.5 Gbps) uplink port, and it is fully compliant with PCI express 1.1 and PCI power management 1.2 specifications. The bridge supports four high performance UARTs, each of which supports Baud rate up to 15 Mbps in asynchronous mode. The UARTs support in-band and out-band auto flow control, arbitrary trigger level, I/O mapping and memory mapping. The PI7C9X7954 is fully software compatible with 16C550 type device drivers and can be configured to fit the requirements of RS232, RS422 and RS485 applications. The EEPROM interface is provided for system implementation convenience. Some registers can be pre-programmed via hardware pin settings to facilitate system initialization. For programming flexibility, all of the default configuration registers can be overwritten by EEPROM data, such as sub-vendor and sub-system ID. TXP, TXN RXP, RXN CLKINP, CLKINN SOUT[3:0] PCI Express Interface Interrupt Interface SIN[3:0] DCD[3:0] DTR[3:0] RTS[3:0] SR_DI SR_CS SR_DO EEPROM Interface SR_CLK_O XTLO XTLI Internal Data / Command Bus RREF Reference Clock CTS[3:0] Quad UART Interface DSR[3:0] RI[3:0] MOD_SEL0[3:0] MOD_SEL1[3:0] MOD_SEL2[3:0] MOD_SEL3[3:0] Baud Rate Generator Figure 3-1 PI7C9X7954 Block Diagram PI7C9X7954 Document Number DS40138 Rev 2-2 Page 10 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 4. PIN ASSIGNMENT 4.1. PIN LIST OF 128-PIN LQFP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME VDDR VDDR VSS VSS SCAN_EN XTLI XTLO SR_CLK_O SR_DI SR_DO SR_CS VDDC VSS WAKEUP_L VSS CLKINP VDDA CLKINN VSS VDDC VTT TXN TXP VSS VDDCAUX RXP VSS RXN RREF VDDA VSS VDDA PIN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME VDDC VDDCAUX VSS PERST_L TEST GPIO[0]/DEQ[1] GPIO[1]/DEQ[2] VDDR VDDR VSS GPIO[2]/DEQ[3] GPIO[3]/TXTERMADJ[0] GPIO[4]/TXTERMADJ[1] GPIO[5]/RXTERMADJ[0] GPIO[6]/RXTERMADJ[1] GPIO[7]/SR_ORG DRIVER_SEL0[0]/HI_DRV DRIVER_SEL0[1]/PHY_TM DRIVER_SEL0[2]/LO_DRV DRIVER_SEL0[3]/DTX[0] VDDC VSS DRIVER_SEL1[0]/DTX[1] DRIVER_SEL1[1]/DTX[2] DRIVER_SEL1[2]/DTX[3] DRIVER_SEL1[3]/DEQ[0] DRIVER_SEL2[0] DRIVER_SEL2[1] DRIVER_SEL2[2] DRIVER_SEL2[3] VDDR VSS PIN 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NAME DRIVER_SEL3[0] DRIVER_SEL3[1] DRIVER_SEL3[2] DRIVER_SEL3[3] VDDC VSS SOUT[0] RTS[0]/EEPROM_BYPASS DTR[0]/TEST2 SIN[0] CTS[0] DSR[0] RI[0] DCD[0] SOUT[1]/DEBUG_PIN RTS[1]/UART_TEST_MODE DTR[1] SIN[1] CTS[1] DSR[1] RI[1] DCD[1] SOUT[2] RTS[2] DTR[2] SIN[2] CTS[2] DSR[2] RI[2] DCD[2] VDDR VSS PIN 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 NAME NC VDDC VDDC VSS VSS NC NC NC NC JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TDO JTAG_TRST_L NC NC NC NC VDDR VDDR VSS VSS SOUT[3] RTS[3] DTR[3] SIN[3] CTS[3] DSR[3] RI[3] DCD[3] VDDC VDDC Table 4-1 Pin-List of 128-Pin LQFP PI7C9X7954 Document Number DS40138 Rev 2-2 Page 11 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 4.2. PIN DESCRIPTION 4.2.1. UART INTERFACE PIN NO. 119, 87, *79, 71 122, 90, 82, 74 126, 94, 86, 78 121, 89, 81, *73 120, 88, *80, *72 NAME SOUT [3:0] TYPE O SIN [3:0] I DCD [3:0] I DTR [3:0] O RTS [3:0] O DESCRIPTION UART Serial Data Outputs: The output pins transmit serial data packets with start and end bits. SOUT[0] and SOUT[1] are output signals with weak internal pull-down resistors. DEBUG_PIN: During system initialization, SOUT[1] acts as the DEBUG_IN pin, and it is used to internal debugging used only. In normal operation, it should be low. By default, it is set to ‘0’ without pin strapped. UART Serial Data Inputs: The input pins receive serial data packets with start and end bits. The pins are idle high. Modem Data-Carrier-Detect Input and General Purpose Input (Active Low) Modem Data-Terminal-Ready Output (Active LOW): If automated DTR# flow control is enabled, the DTR# pin is asserted and deasserted if the receiver FIFO reaches or falls below the programmed thresholds, respectively. DTR[0] and DTR[1] are output signals with weak internal pull-down resistors. TEST2: During system initialization, DTR[0] acts as the TEST pin, and it is used for internal debugging used only. In normal operation, it should be low. By default, it is set to ‘0’ without pin strapped. Modem Request-To-Send Output (Active LOW): If automated RTS# flow control is enabled, the RTS# pin is deasserted and reasserted whenever the receiver FIFO reaches or falls below the programmed thresholds, respectively. RTS[0] and RTS[1] are output signals with weak internal pull-down resistors. UART_TEST_MODE: During system initialization, RTS[1] acts as the UART_TEST_MODE pin, and it is used for internal debugging used only. In normal operation, it should be low. By default, it is set to ‘0’ without pin strapped. 123, 91, 83, 75 CTS [3:0] I 124, 92, 84, 76 DSR [3:0] I 125, 93, 85, 77 7 6 RI [3:0] I XTLO XTLI O I PI7C9X7954 Document Number DS40138 Rev 2-2 EEPROM Bypass: During system initialization, RTS[0] acts as the EEPROM Bypass pin, and it is used to bypass EEPROM pre-loading. The pin is active-high. When it is asserted at start-up, the EEPROM pre-loading is bypassed, and no configuration data is loaded from the EEPRPOM. Otherwise, configuration data is loaded from the EEPROM. Modem Clear-To-Send Input (Active LOW): If automated CTS# flow control is enabled, upon deassertion of the CTS# pin, the transmitter will complete the current character and enter the idle mode until the CTS# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the CTS# pin. Modem Data-Set-Ready Input (Active LOW): If automated DSR# flow control is enabled, upon deassertion of the DSR# pin, the transmitter will complete the current character and enter the idle mode until the DSR# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the DSR# pin. Modem Ring-Indicator Input (Active LOW) Crystal Oscillator Output Crystal Oscillator Input Or External Clock Pin: The maximum frequency supported by this device is 60MHz. Page 12 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 PIN NO. *52, *51, *50, *49 NAME DRIVER_SEL0 [3:0] TYPE O DESCRIPTION DRIVER_SEL0: Used to select RS-232/ RS-424/ 4-Wire RS-485/ 2-Wire RS-458 Serial Port Mode for UART 0. DRIVER_SEL0 [3:0] are output signals with weak internal pull-down resistors. Driver Current Level Control (DTX[0]): During system initialization, DRIVER_SEL0[3] acts as the DTX[0] pin, and it is used to control the driver current level. By default, it is set to ‘0’ without pin strapped. Low Driver Control (LO_DRV): During system initialization, DRIVER_SEL0[2] acts as the LO_DRV pin, and it is used to decrease the nominal value of the PCI Express lane’s driver current level. By default, it is set to ‘0’ without pin strapped. PHY_TM: During system initialization, DRIVER_SEL0[1] acts as the PHY_TM pin, and it is used for internal debugging used only. In normal operation, it should be low. By default, it is set to ‘0’ without pin strapped. *58, *57, *56, *55 DRIVER_SEL1 [3:0] O High Driver Control (HI_DRV): During system initialization, DRIVER_SEL0[0] acts as the HI_DRV pin, and it is used to increase the nominal value of the PCI Express lane’s driver current level. By default, it is set ‘0’ without pin strapped. DRIVER_SEL1: Used to select RS-232/ RS-424/ 4-Wire RS-485/ 2-Wire RS-458 Serial Port Mode for UART 1. DRIVER_SEL1 [3:0] are output signals with weak internal pull-down resistors. Driver Equalization Level Control (DEQ[0]): During system initialization, DRIVER_SEL1[3] acts as the DEQ[0] pin, and it is used to control the driver current level. By default, it is set to ‘0’ without pin strapped. 4.2.2. 62, 61, 60, 59 DRIVER_SEL2 [3:0] O 68, 67, 66, 65 DRIVER_SEL3 [3:0] O Driver Current Level Control (DTX[3:1]): During system initialization, DRIVER_SEL1[2:0] acts as the DTX[3:1] pins, and they are used to control the driver current level. By default, they are set to ‘000’ without pin strapped. DRIVER_SEL2: Used to select RS-232/ RS-424/ 4-Wire RS-485/ 2-Wire RS-458 Serial Port Mode for UART 2. DRIVER_SEL2[3] is an output signal with a weak internal pull-up resistor, and other DRIVER_SEL2 signals are output signals with internal pull-down resistors. DRIVER_SEL3: Used to select RS-232/ RS-424/ 4-Wire RS-485/ 2-Wire RS-458 Serial Port Mode for UART 3. DRIVER_SEL3 [3:0] are output signals with weak internal pull-up resistors. PCI EXPRESS INTERFACE PIN NO. 23, 22 NAME TXP, TXN TYPE O 26, 28 RXP, RXN I 16, 18 CLKINP, CLKINN I 29 RREF PI7C9X7954 Document Number DS40138 Rev 2-2 I DESCRIPTION PCI Express Serial Output Signal: Differential PCI Express output signals. PCI Express Serial Input Signal: Differential PCI Express input signals. Reference Input Clock: Connects to external 100MHz differential clock The input clock signals must be delivered to the clock buffer cell through an AC-coupled interface so that only the AC information of the clock is received, converted, and buffered. It is recommended that a 0.1uF be used in the AC-coupling. Reference Resistor: To accurately set internal bias references, a precision resistor must be connected between Rref and Vss. The resistor should have a nominal value of 2.1 KΩ and accuracy of +/1% Page 13 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 4.2.3. SYSTEM INTERFACE PIN NO. 36 *48, *47, *46, *45, *44, *43, *39, *38 NAME PEREST_L GPIO [7:0] TYPE I I/O DESCRIPTION System Reset Input General-Purpose Bi-Direction Signals / SR_ORG: These eight general-purpose pins are programmed as either input-only or bi-directional pins by writing the GPIO output enable control register. GPIO[2] is a bi-directional signal with a weak internal pull-up resistor, and other GPIO pins are bi-directional signals with weak internal pull-down resistors. EEPROM Organization Pin (SR_ORG): During system initialization, GPIO[7] acts as the SR_ORG pin, and it is used to select the organization structure of the EEPROM. The pin is active-high. When it is asserted at start-up, the EEPROM configuration data is organized in 16-bit structure. Otherwise, 8-bit structure is used. Receiver Termination Adjustment (RXTERMADJ[1:0]): During system initialization, GPIO[6:5] acts as the RXTERMADJ[1:0] pins, and they are used to adjust the receive termination resistor value. By default, they are set to ‘00’ without pin strapped. Transmit Termination Adjustment (TXTERMADJ[1:0]): During system initialization, GPIO[4:3] acts as the TXTERMADJ[1:0] pins, and they are used to adjust the transmit termination resistor value. By default, they are set to “00” without pin strapped. 14 4.2.4. WAKEUP_L O Driver Equalization Level Control (DEQ[3:1]): During system initialization, GPIO[2:0] acts as the DEQ[3:1] pins, and they are used to control the driver current level. By default, they are set to ‘100’ without pin strapped. Wakeup Signal (Active LOW): When the Ring Indicator is received on UART channel 0 in L2 state, the WAKEUP_L is asserted. WAKEUP_L is an output signal with a weak internal pull-down resistor. TEST SIGNALS PIN NO. 106 NAME JTG_TDI TYPE I 109 JTG_TDO O 107 JTG_TMS I 108 JTG_TCK I 110 JTG_TRST_L I 5 SCAN_EN I 37 97, 102, 103, 104, 105, 111, 112, 113, 114 TEST NC I PI7C9X7954 Document Number DS40138 Rev 2-2 DESCRIPTION Test Data Input: When SCAN_EN is high, the pin is used (in conjunction with TCK) to shift data and instructions into the TAP in a serial bit stream. JTG_TDI is an input signal with a weak internal pull-up resistor. Test Data Output: When SCAN_EN is high, it is used (in conjunction with TCK) to shift data out of the Test Access Port (TAP) in a serial bit stream Test Mode Select: Used to control the state of the Test Access Port controller. JTG_TMS is an input signal with a weak internal pull-up resistor. Test Clock: Used to clock state information and data into and out of the chip during boundary scan. Test Reset: Active LOW signal to reset the TAP controller into an initialized state. JTG_TRST_L is an input signal with a weak internal pull-up resistor. Scan Test Enable Pin: SCAN_EN is an input signal with a weak internal pull-up resistor. This input signal should be tied to ground during normal operation. These pins can be left floating. Page 14 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 4.2.5. 4.2.6. EEPROM INTERFACE PIN NO. 11 NAME SR_CS TYPE O 10 SR_DO O 9 SR_DI I 8 SR_CLK_O O DESCRIPTION EEPROM Chip Select: SR_CS is an output signal with a weak internal pull-up resistor. EEPROM Data Output: Serial data output interface to the EEPROM. SR_DO is an output signal with a weak internal pull-up resistor. EEPROM Data Input: Serial data input interface to the EEPROM. SR_DI is an input signal with a weak internal pull-up resistor. EEPROM Clock Output. POWER PINS PIN NO. 12, 20, 33, 53, 69, 98, 99, 127, 128 17, 30, 32, 1, 2, 40, 41, 63, 95, 115, 116 25, 34 21 NAME VDDC TYPE P DESCRIPTION 1.8 V Power Pin: Used as digital core power pins. VDDA VDDR P P 1.8 V Power Pin: Used as analog core power pins. 3.3 V Power Pin: Used as digital I/O power pins. VDDCAUX VTT P P 3, 4, 13, 15, 19, 24, 27, 31, 35, 42, 54, 64, 70, 96, 100, 101, 117, 118 VSS P 1.8 V Power Pin: Used as auxiliary power pins. 1.8V Termination Voltage: Provides driver termination voltage at transmitter. Should be given the same consideration as VDDCAUX. Ground Pin: Used as ground pins. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 15 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 5. FUNCTIONAL DESCRIPTION The PI7C9X7954 is an integrated solution of four high-performance 16C550 UARTs with one x1 PCI Express host interface. The PCI Express host interface is compliant with the PCI Express Base Specification 1.1, PCI Express CEM Specification 1.1, and PCI Power Management 1.2. In addition, the chip is compliant with the Advanced Configuration Power Interface (ACPI) Specification and the PCI Standard Hot-Plug Controller (SHPC) and Subsystem Specification Revision 1.0. The x1 PCI Express host interface supports up to 2.5 Gbps bandwidth and complete PCI Express configuration register set. The PCI Express interface allows direct access to the configuration and status registers of the UART channels. The UARTs in the PI7C9X7954 support the complete register set of the 16C550-type devices. The UARTs support Baud Rates up to 15 Mbps in asynchronous mode. Each UART channel has 128-byte deep transmit and receive FIFOs. The high-speed FIFOs reduce CPU utilization and improve data throughput. In addition, the UARTs support enhanced features including automated in-band flow control using programmable Xon/ Xoff in both directions, automated out-band flow control using CTS#/ RTS# and/or DRS#/ DTR#, and arbitrary transmit and receive trigger levels. 5.1. CONFIGURATION SPACE The PI7C9X7954 has two sets of registers to allow various configuration and status monitoring functions. The PCI Express Configuration Space Registers enable the plug-and-play and auto-configuration when the device is connected to the PCI Express system bus. The UART configuration and internal registers enable the general UART operation functions, status control and monitoring. 5.1.1. PCI Express Configuration Space The PI7C9X7954 is recognized as a PCI Express endpoint, which is mapped into the configuration space as a single logical device. Each endpoint in the system, including the PI7C9X7954, is part of a Hierarchy Domains originated by the Root Complex, which is a tree with a Root Port at its head in the configuration space. The device configuration registers are implemented for the user to access the functionalities provided by the PCI Express specification. The specification utilizes a flat memory-mapped configuration space to access device configuration registers. All PCI Express endpoints facilitate a PCI-compatible configuration space to maintain compatibility with PCI software configuration mechanism. PCI Local Bus Specification, Revision 3.0 allocates 256 bytes per device function. PCI Express Base Specification 1.1 extends the configuration space to 4096 bytes to allow enhanced features. The first 256 bytes of the PCI Express Configuration Space are PCI 3.0 compatible region, and the rest of the 4096 bytes are PCI Express Configuration Space. The user can access the PCI 3.0 compatible region either by conventional PCI 3.0 configuration addresses or by the PCI Express memory-mapping addresses. These two types of accesses to the PCI 3.0 compatible region have identical results. The enhanced features in the PCI Express configuration space can only be accessed by PCI Express memory-mapping accesses. 5.1.2. UART Configuration Space Through the UART registers, the user can control and monitor various functionalities of the UARTs on the PI7C9X7954 including FIFOs, interrupt status, line status, modem status and sample clock. Each of the UART’s transmit and receive data FIFOs can be conveniently accessed by reading and writing the registers in the UART configuration space. These registers allow flexible programming capability and versatile device operations of the PI7C9X7954. Each UART is accessed through an 8-byte I/O blocks. The addresses of the UART blocks are offset by the base address referred by the Base Address Register (BAR). The value of the base address is loaded from the I/O or Memory Base Address defined in the PCI Express configuration PI7C9X7954 Document Number DS40138 Rev 2-2 Page 16 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 space. The PI7C9X7954 also supports enhanced features such as Xon/Xoff, automatic flow control, Baud Rate prescaling and various status monitoring. These enhanced features are available through the memory address offset by the BAR in the PCI Express configuration space. The basic features available in the registers in I/O mode are also available in the registers in memory-mapping mode. Accesses to these registers are equivalent in these two modes. The UARTs on the PI7C9X7954 supports operations in 16C450, 16C550 and 16C950 modes. These modes of operation are selected by writing the SFR, FCR and EFR registers. The PI7C9X7954 is backward compatible with these modes of operation. 5.2. DEVICE OPERATION The PI7C9X7954 is configured by the Root Complex in the bootstrap process during system start-up. The Root Complex performs bus scans and recognizes the device by reading vendor and device IDs. Upon successful device identification, the system then loads device-specific driver software and allocates I/O, memory and interrupt resources. The driver software allows the user to access the functions of the device by reading and writing the UART registers. The PCI Express interface incorporates convenient device operation and high system performance. 5.2.1. Configuration Access The PI7C9X7954 accepts type 0 configuration read and write accesses defined in the PCI Express Base1.1 Specification. The first 256 bytes of the PCI Express configuration are compatible with PCI 3.0. 5.2.2. I/O Reads/Writes The PCI Express interface of the PI7C9X7954 decodes incoming transaction packets. If the address is within the region assigned by the I/O Base Address Registers, the transaction is recognized as an I/O Read or Write. 5.2.3. Memory Reads/Writes Similar to the I/O Read/Write, if the address of the transaction packet is within the memory range, a Memory Read/Write occurs. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 17 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 5.2.4. Mode Selection All of the internal UART channels in the I/O Bridge support the 16C450, 16C550, Enhanced 16C550, and Enhanced 950 UART Modes. The mode of the UART operation is selected by toggling the Special Function Register (SFR[5]) and Enhanced Function Register (EFR[4]). The FIFO depth of each mode and the mode selection is tabulated in the table below. Table 5-1 Mode Selection UART Mode SFR[5] EFR[4] 450/550 X 0 Enhanced 550 0 1 Enhanced 950 1 1 5.2.5. FIFO Size 1/16 128 128 450/550 Mode The 450 Mode is inherently supported when 550 Mode is selected. When in the 450 Mode, the FIFOs are in the “Byte Mode”, which refers to the one-byte buffer in the Transmit Holding Register and the Receive Holding Register in each of the UART channels. When in the 550 Mode, the UARTs support an increased FIFO depth of 16. When EFR[4] is set to “0”, the SFR[5] is ignored, and the 450/550 Mode is selected. 5.2.6. Enhanced 550 Mode Setting the SFR[5] to “0” and EFR[4] to “1” enables the Enhanced 550 Mode. The Enhanced 550 Mode further increases FIFO depth to 128. 5.2.7. Enhanced 950 Mode 128-deep FIFOs are supported in the Enhanced 950 Mode. When the Enhanced 950 Mode is enabled, the UART channels support additional features:         5.2.8. Sleep mode Special character detection Automatic in-band flow control Automatic flow control using selectable arbitrary thresholds Readable status for automatic in-band and out-of-band flow control Flexible clock prescaler Programmable sample clock DSR/DTR automatic flow control Transmit and Receive FIFOs Each channel of the UARTs consists of 128 bytes of transmit FIFOs and 128 bytes of receive FIFOs, namely the Transmit Holding Registers (THR) and the Receive Holding Registers (RHR). The FIFOs provide storage space for the data before they can be transmitted or processed. The THR and RHR operate simultaneously to transmit and read data. The transmitter reads data from the THR into the Transmit Shift Register (TSR) and removes the data from top of the THR. It then converts the data into serial format with start and stop bits and parity bits if required. If the transmitter completes transmitting the data in the TSR and the THR is empty, the transmitter is in the idle state. The data that arrive most recently are written to the bottom of the THR. If the THR is full, and the user attempts to write data to the THR, a data overrun occurs and the data is lost. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 18 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 The receiver writes data to the bottom of the RHR when it finishes receiving and decoding the data bits. If the RHR is full when the receiver attempts to write data to it, a data overrun occurs. Any read operation to an empty RHR is invalid. The empty and full status of the THR and RHR can be determined by reading the empty and full flags in the Line Status Register (LSR). When the transmitter and receiver are ready to transfer data to and from the FIFOs, interrupts are raised to signal this condition. Additionally, the user can use the Receive FIFO Data Counter (RFDC) and Transmit FIFO Data Counter (TFDC) registers to determine the number of items in each FIFO. PCI EXPRESS MASTER UART COMMON MODE ADDRESS RHR WP RP LSR THR DATA0 LSR0 DATA0 DATA1 LSR1 DATA1 DATA2 LSR2 DATA2 DATA125 LSR125 DATA125 DATA126 LSR126 DATA126 DATA127 LSR127 DATA127 WP RP Figure 5-1 Transmit and Receive FIFOs PI7C9X7954 Document Number DS40138 Rev 2-2 Page 19 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 5.2.9. Automated Flow Control The device uses automatic in-band flow control to prevent data-overrun to the local receive FIFO and remote receive FIFO. This feature works in conjunction with the special character detection. When an XOFF condition is detected, the UART transmitter will suspend any further data transmission after the current character transmission is completed. The transmitter will resume data-transmission as soon as an XON condition is detected. The automatic in-band feature is enabled by the Enhanced Function Register (EFR). EFR[1:0] enables the in-band receive flow control, and EFR[3:2] enables the in-band transmit flow control. The out-of-band flow control utilizes RTS# and CTS# pins to suspend and resume the data transmission and to prevent data-overrun. An asserted CTS# pin signals the UART to suspend transmission due to a full remote receive FIFO. Upon detecting an asserted CTS# pin, the UART will complete the current character transmission and enters idle mode until the CTS# pin is deasserted. The UART deasserts RTS# to signal the remote transmitter that the local receive FIFO reaches the programmed upper trigger level. When the local receive FIFO falls below the programmed lower trigger level, the RTS# is reasserted. The automatic out-of-band flow control is enabled by EFR[7:6]. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 20 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 5.2.10. Internal Loopback The internal loopback capability of the UARTs is enabled by setting Modem Control Register bit-4 (MCR[4]) to 1. When the feature is enabled, the data from the output of the transmit shift register are looped back to the input of the receive shift register. This feature provides the users a way to perform system diagnostics by allowing the UART to receive the same data it is sending. VCC TX[3:0] Transmit Shift Register Receive Shift Register RX[3:0] VCC RTS#[3:0] RTS# Modem / General Purpose Control Logic Internal Bus Lines and Control Signals MCR bit-4=1 CTS# CTS#[3:0] VCC DTR#[3:0] DTR# DSR# DSR#[3:0] Figure 5-2 Internal Loopback in PI7C9X7954 PI7C9X7954 Document Number DS40138 Rev 2-2 Page 21 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 5.2.11. Crystal Oscillator The PI7C9X7954 uses a crystal oscillator or an external clock source to provide system clock to the Baud Rate Generator. When a clock source is used, the clock signal should be connected to the XTLI pin, and a 2K pull-up resistor should be connected to the XTLO pin. When a crystal oscillator is used, the XTLI is the input and XTLO is the output, and the crystal should be connected in parallel with two capacitors. XTLI R XTLO 14.7456 MHz C1 C2 Figure 5-3 Crystal Oscillator as the Clock Source External Clock VCC XTLI GND VCC R1 2K XTLO Figure 5-4 External Clock Source as the Clock Source PI7C9X7954 Document Number DS40138 Rev 2-2 Page 22 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 5.2.12. Baud Rate Generation The built-in Baud Rate Generator (BRG) allows a wide range of input frequency and flexible Baud Rate generation. To obtain the desired Baud Rate, the user can set the Sample Clock Register (SCR), Divisor Latch Low Register (DLL), Divisor Latch High Register (DLH) and Clock Prescale Registers (CPRM and CPRN). The Baud Rate is generated according to the following equation: BaudRate  InputFrequ ency Divisor * Pr escaler The parameters in the equation above can be programmed by setting the “SCR”, “DLL”, “DLH”, “CPRM” and “CPRN” registers according to the table below. Table 5-2 Baud Rate Generator Setting Setting Description Divisor DLL + (256 * DLH) Prescaler 2 M * (SampleCloc k  N ) SampleClock 16  SCR , (SCR = ‘0h’ to ‘Ch’) M CPRM, (CPRM = ‘01h’ to ‘02h’) N CPRN, (CPRN = ‘0h’ to ‘7h’) To ensure the proper operation of the Baud Rate Generator, users should avoid setting the value ‘0’ to Sample Clock, Divisor and Prescaler. The following table lists some of the commonly used Baud Rates and the register settings that generate a specific Baud Rate. The examples assume an Input Clock frequency of 14.7456 Mhz. The SCR register is set to ‘0h’, and the CPRM and CPRN registers are set to ‘1h’ and ‘0h’ respectively. In these examples, the Baud Rates can be generated by different combination of the DLH and DLL register values. Table 5-3 Sample Baud Rate Setting Baud Rate DLH DLL 1,200 3h 00h 2,400 1h 80h 4,800 0h C0h 9,600 0h 60h 19,200 0h 30h 28,800 0h 20h 38,400 0h 18h 57,600 0h 10h 115,200 0h 08h 921,600 0h 01h 5.2.13. Power Management The PI7C9X7954 supports the D0, D1, D2 and D3 power states. The device is compliant with PCI Power Management Specification Revision 1.2. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 23 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6. PCI EXPRESS REGISTER DESCRIPTION 6.1. REGISTER TYPES REGISTER TYPE HwInt RO WO RW RWC RWCS RWS DEFINITION Hardware Initialization Read Only Write Only Read / Write Read / Write 1 to Clear Sticky - Read Only / Write 1 to Clear Sticky - Read / Write 6.2. CONFIGURATION REGISTERS The following table details the allocation of the register fields of the PCI 2.3 compatible type 0 configuration space header. 31 – 24 23 – 16 Device ID Status 15 – 8 7–0 Vendor ID Command Revision ID Master Latency Cache Line Size Timer Base Address Register 0 Base Address Register 1 Reserved Subsystem ID Subsystem Vendor ID Reserved Capability Pointer Reserved Reserved Interrupt Pin Interrupt Line Reserved Power Management Capabilities Next ID = 8C Capability ID = 01 PM Data PPB Support Power Management Data Message Control Register Next ID =9C Capability ID = 05 Message Address Register Message Upper Address Register Message Data Register VPD Register Next ID = A4 Capability ID = 03 VPD Data Register Vendor Define Register(28h) Next ID = E0 Capability ID = 09 XPIP CSR0 XPIP CSR1 ACK Latency Timer Replay Time-out counter UART Driver Selection Power Management Control Parameter Debug Register PHY Parameter Reserved GPIO Data and Control EEPROM Data EEPROM Control PCI Express Capability Register Next ID = 00h Capability ID = 10 Device Capability Device Status Device Control Link Capability Link Status Link Control Reserved Reserved PI7C9X7954 Document Number DS40138 Rev 2-2 Class Code Header Type Page 24 of 69 www.diodes.com BYTE OFFSET 00h 04h 08h 0Ch 10h 14h 18h~28h 2Ch 30h 34h 38h 3Ch 40h – 7Fh 80h 84h 8Ch 90h 94h 98h 9Ch A0h A4h A8h Ach B0h B4h B8h BCh – C4h C8h CCh – D4h D8h DCh E0h E4h E8h ECh F0h F4h - FCh October 2017 © Diodes Incorporated PI7C9X7954 Other than the PCI 2.3 compatible configuration space header, the I/O bridge also implements PCI express extended configuration space header, which includes advanced error reporting registers. The following table details the allocation of the register fields of PCI express extended capability space header. The first extended capability always begins at offset 100h with a PCI Express Enhanced Capability header and the rest of capabilities are located at an offset greater than 0FFh relative to the beginning of PCI compatible configuration space. 31 – 24 Next Capability Offset = 000h 6.2.1. 23 – 16 Capability Version 15 – 8 7–0 PCI Express Extended Capability ID = 001h Uncorrectable Error Status Register Uncorrectable Error Mask Register Uncorrectable Error Severity Register Correctable Error Status Register Correctable Error Mask Register Advanced Error Capabilities and Control Register Header Log Register BYTE OFFSET 100h 104h 108h 10Ch 110h 114h 118h 11Ch~128h VENDOR ID REGISTER – OFFSET 00h BIT 15:0 FUNCTION Vendor ID TYPE RO DESCRIPTION Identifies Pericom as the vendor of this I/O bridge. The default value may be changed by auto-loading from EEPROM. Reset to 12D8h. 6.2.2. DEVICE ID REGISTER – OFFSET 00h BIT 31:16 FUNCTION Device ID TYPE RO DESCRIPTION Identifies this I/O bridge as the PI7C9X7954. The default value may be changed by auto-loading from EEPROM. Reset to 7954h. 6.2.3. COMMAND REGISTER – OFFSET 04h BIT FUNCTION 0 I/O Space Enable 1 2 3 4 5 Memory Space Enable Bus Master Enable Special Cycle Enable Memory Write And Invalidate Enable VGA Palette Snoop Enable TYPE RW DESCRIPTION Controls a device’s response to I/O Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O Space accesses. RW Reset to 0b. Controls a device’s response to Memory Space accesses. A value of 0 disables the device response. A value of 1 allows the device to response to memory Space accesses. RO RO RO RO 6 Parity Error Response Enable RW 7 Wait Cycle Control RO PI7C9X7954 Document Number DS40138 Rev 2-2 Reset to 0b. It is not implemented. Hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Controls the device’s response to parity errors. When the bit is set, the device must take its normal action when a parity error is detected. When the bit is 0, the device sets its Detected Parity Error Status bit when an error is detected. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Page 25 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6.2.4. BIT FUNCTION TYPE 8 SERR# enable RW 9 Fast Back-to-Back Enable RO 10 Interrupt Disable RW 15:11 Reserved RO Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Controls the ability of the I/O bridge to generate INTx interrupt Messages. Reset to 0b. Reset to 00000b. STATUS REGISTER – OFFSET 04h BIT 18:16 FUNCTION Reserved 19 Interrupt Status TYPE RO RO 20 Capabilities List RO 21 22 66MHz Capable Reserved Fast Back-to-Back Capable Master Data Parity Error DEVSEL# Timing RO RO 23 24 26:25 27 28 29 30 31 6.2.5. DESCRIPTION This bit, when set, enables reporting of Non-fatal and Fatal errors detected by the device to the Root Complex. Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error RO RWC RO RWC RWC RWC RWC DESCRIPTION Reset to 000b. Indicates that an INTx interrupt Message is pending internally to the device. Reset to 0b. Set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure) Reset to 1b. Does not apply to PCI Express. Must be hardwired to 0b. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. It is not implemented. Hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a completer) whenever completing a request in the I/O bridge side using Completer Abort Completion Status. Reset to 0b. It is not implemented. Hardwired to 0b. It is not implemented. Hardwired to 0b. Set to 1 when the I/O bridge sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR Enable bit in the Command register is 1. Reset to 0b. Set to 1 whenever the I/O bridge receives a Poisoned TLP. RWC Reset to 0b. REVISION ID REGISTER – OFFSET 08h BIT 7:0 FUNCTION Revision TYPE RO DESCRIPTION Indicates revision number of the I/O bridge. The default value may be changed by auto-loading from EEPROM. Reset to 00h. 6.2.6. CLASS CODE REGISTER – OFFSET 08h BIT 15:8 23:16 31:24 FUNCTION Programming Interface Sub-Class Code Base Class Code PI7C9X7954 Document Number DS40138 Rev 2-2 TYPE RO RO RO DESCRIPTION Read as 02h to indicate no programming interfaces have been defined for PCI-to-PCI bridges Read as 00h to indicate device is PCI-to-PCI bridge Read as 07h to indicate device is a bridge device Page 26 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6.2.7. CACHE LINE REGISTER – OFFSET 0Ch BIT FUNCTION 7:0 Cache Line Size TYPE RW DESCRIPTION The cache line size register is set by the system firmware and the operating system to system cache line size. This field is implemented by PCI Express devices as a RW field for legacy compatibility purposes but has no impact on any PCI Express device functionality. Reset to 00h. 6.2.8. MASTER LATENCY TIMER REGISTER – OFFSET 0Ch BIT 15:8 6.2.9. FUNCTION Latency timer TYPE RO DESCRIPTION Does not apply to PCI Express. Must be hardwired to 00h. HEADER TYPE REGISTER – OFFSET 0Ch BIT FUNCTION TYPE 23:16 Header Type RO DESCRIPTION Read as 00h to indicate that the register layout conforms to the standard PCI-to-PCI bridge layout. 6.2.10. BASE ADDRESS REGISTER 0 – OFFSET 10h BIT FUNCTION 31:0 Base Address 0 TYPE RW DESCRIPTION Use this I/O base address to map the UART 16550 compatible registers. The base address can be allocated to 64 Bytes. Reset to 00000001h. 6.2.11. BASE ADDRESS REGISTER 1 – OFFSET 14h BIT FUNCTION 31:0 Base Address 1 TYPE RW DESCRIPTION Use this memory base address to map the UART 16550 compatible and enhanced registers. The base address can be allocated to 4096 Bytes. Reset to 00000000h 6.2.12. SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch BIT FUNCTION 15:0 Sub Vendor ID TYPE RO DESCRIPTION Indicates the sub-system vendor id. The default value may be changed by auto-loading from EEPROM. Reset to 0000h. 6.2.13. SUBSYSTEM ID REGISTER – OFFSET 2Ch BIT FUNCTION 31:16 Sub System ID TYPE RO DESCRIPTION Indicates the sub-system device id. The default value may be changed by auto-loading from EEPROM. Reset to 0000h. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 27 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6.2.14. CAPABILITIES POINTER REGISTER – OFFSET 34h BIT FUNCTION 7:0 Capabilities Pointer TYPE RO DESCRIPTION This optional register points to a linked list of new capabilities implemented by the device. This default value may be changed by auto-loading from EEPROM. The default value is 80h. 6.2.15. INTERRUPT LINE REGISTER – OFFSET 3Ch BIT 7:0 FUNCTION Interrupt Line TYPE RW DESCRIPTION Used to communicate interrupt line routing information. POST software will write the routing information into this register as it initializes and configures the system. Reset to 00h. 6.2.16. INTERRUPT PIN REGISTER – OFFSET 3Ch BIT FUNCTION TYPE 15:8 Interrupt Pin RO DESCRIPTION Identifies the legacy interrupt Message(s) the device uses. Reset to 01h. 6.2.17. POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h BIT 7:0 FUNCTION Enhanced Capabilities ID TYPE RO DESCRIPTION Read as 01h to indicate that these are power management enhanced capability registers. 6.2.18. NEXT ITEM POINTER REGISTER – OFFSET 80h BIT FUNCTION 15:8 Next Item Pointer TYPE RO DESCRIPTION The pointer points to the Power Management capability register (8Ch). Reset to 8Ch. 6.2.19. POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h BIT 19 FUNCTION Power Management Revision PME# Clock 20 Auxiliary Power RO 21 Device Specific Initialization RO 24:22 AUX Current RO 25 D1 Power State Support RO 26 D2 Power State Support RO 31:27 PME# Support RO 18:16 PI7C9X7954 Document Number DS40138 Rev 2-2 TYPE RO RO DESCRIPTION Read as 011b to indicate the I/O bridge is compliant to Revision 1.1 of PCI Power Management Interface Specifications. Does not apply to PCI Express. Must be hardwired to 0b. Read as 1b to indicate the I/O bridge forwards the PME# message in D3cold and an auxiliary power source is required. Read as 0b to indicate the I/O bridge does not have device specific initialization requirements. The default value may be changed by auto-loading from EEPROM. Reset as 111b to indicate the I/O bridge need 375 mA in D3 state. The default value may be changed by auto-loading from EEPROM. Read as 1b to indicate the I/O bridge supports the D1 power management state. The default value may be changed by auto-loading from EEPROM. Read as 1b to indicate the I/O bridge supports the D2 power management state. The default value may be changed by auto-loading from EEPROM. Read as 01000b to indicate the I/O bridge supports the forwarding of PME# message in all power states. The default value may be changed by auto-loading from EEPROM. Page 28 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6.2.20. POWER MANAGEMENT DATA REGISTER – OFFSET 84h BIT FUNCTION TYPE 1:0 Power State RW 2 Reserved RO 3 No_Soft_Reset RO 7:4 Reserved RO 8 PME# Enable RW DESCRIPTION Indicates the current power state of the I/O bridge. Writing a value of D0 causes a hot reset without asserting PEREST_L when the previous state was D3. 00b: D0 state 01b: D1 state 10b: D2 state 11b: D3 hot state Reset to 00b. Read as 0b. When set, this bit indicates that I/O bridge transitioning from D3hot to D0 does not perform an internal reset. When clear, an internal reset is performed when power state transits from D3hot to D0. The default value may be changed by auto-loading from EEPROM. Reset to 0b. Read as 0h. When asserted, the I/O bridge will generate the PME# message. Reset to 0b. Select data registers. 12:9 Data Select RW 14:13 Data Scale RO 15 PME status RO Reset to 0h. Read as 00b. Indicates that the PME# message is pending internally to the I/O bridge. Reset to 0b. 6.2.21. PPB SUPPORT EXTENSIONS – OFFSET 84h BIT 21:16 22 23 FUNCTION Reserved B2_B3 Support for D3HOT Bus Power / Clock Control Enable TYPE RO RO RO DESCRIPTION Reset to 000000b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. 6.2.22. PM DATA REGISTER – OFFSET 84h BIT FUNCTION 31:24 PM Data Register TYPE DESCRIPTION PM Data Register. RO Reset to 00h 6.2.23. MESSAGE SIGNALED INTERRUPTS (MSI) Capability ID Register 8Ch BIT 7:0 FUNCTION Enhanced Capability ID TYPE RO DESCRIPTION Read as 05h to indicate that this is Message Signaled Interrupt capability register. 6.2.24. MESSAGE SIGNALED INTERRUPTS (MSI) NEXT ITEM POINTER 8Ch BIT FUNCTION 15:8 Next Item Pointer TYPE DESCRIPTION The pointer points to the Vendor Specific capability register (9Ch). RO Reset to 9Ch. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 29 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6.2.25. MESSAGE CONTROL REGISTER – OFFSET 8Ch BIT FUNCTION TYPE 16 MSI Enable RW 19:17 22:20 6.2.26. Multiple Message Capable Multiple Message Enable RO RW DESCRIPTION 0b: The function is prohibited from using MSI to request service 1b: The function is permitted to use MSI to request service and is prohibited from using its INTx # pin Reset to 1’b0. Read as 3’b000. Reset to 3’b000. 23 64-bit address capable RO 0b: The function is not capable of generating a 64-bit message address 1b: The function is capable of generating a 64-bit message address 31:24 Reserved RO Reset to 1’b1. Reset to 8’h00. MESSAGE ADDRESS REGISTER – OFFSET 90h BIT 1:0 FUNCTION Reserved TYPE RO 31:2 Message Address RW DESCRIPTION Reset to 00b. If the message enable bit is set, the contents of this register specify the DWORD aligned address for MSI memory write transaction. Reset to 0. 6.2.27. MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h BIT FUNCTION 31:0 Message Upper Address TYPE RW DESCRIPTION This register is only effective if the device supports a 64-bit message address is set. Reset to 00000000h. 6.2.28. MESSAGE DATA REGISTER – OFFSET 98h BIT 15:0 FUNCTION Message Data TYPE RW DESCRIPTION Reset to 0000h. 6.2.29. VPD CAPABILITY ID REGISTER – OFFSET 9Ch BIT 7:0 FUNCTION Enhanced Capabilities ID TYPE RO DESCRIPTION Read as 03h to indicate that these are VPD enhanced capability registers. 6.2.30. NEXT ITEM POINTER REGISTER – OFFSET 9Ch BIT FUNCTION 15:8 Next Item Pointer TYPE DESCRIPTION The pointer points to the VPD capability register (A4h). RO Reset to A4h 6.2.31. VPD REGISTER – OFFSET 9Ch BIT FUNCTION 16 VPD Start PI7C9X7954 Document Number DS40138 Rev 2-2 TYPE RW DESCRIPTION Starts VPD read or write cycle. Assert by software and is de-asserted by hardware. Page 30 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT FUNCTION 17 VPD Operation TYPE DESCRIPTION Reset to 0b. 0b: Performs VPD read command to VPD table at the location as specified in VPD address 1b: Performs VPD write command to VPD table at the location as specified in VPD address RW 22:18 VPD Address RW 31:23 Reserved RO Reset to 0b. Contains DWORD address that is used to generate read or write cycle to the VPD table stored in EEPROM. Reset to 00000b. Read as 000h. 6.2.32. VPD DATA REGISTER – OFFSET A0h BIT FUNCTION 31:0 VPD Data TYPE DESCRIPTION When read, it returns the last data read from VPD table at the location as specified in VPD Address. RW When writes, it places the current data into VPD table at the location as specified in VPD Address. Reset to 00000000h. 6.2.33. VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h BIT 7:0 FUNCTION Enhanced Capabilities ID TYPE RO DESCRIPTION Read as 09h to indicate that these are Vendor Specific capability registers. 6.2.34. NEXT ITEM POINTER REGISTER – OFFSET A4h BIT FUNCTION 15:8 Next Item Pointer TYPE DESCRIPTION The pointer points to the PCI Express capability register (E0h). RO Reset to E0h. 6.2.35. LENGTH REGISTER – OFFSET A4h BIT FUNCTION 31:16 Length Information TYPE RO DESCRIPTION The length field provides the information for number of bytes in the capability structure (including the ID and Next pointer bytes). Reset to 28h. 6.2.36. XPIP CSR0 – OFFSET A8h (Test Purpose Only) BIT 31:0 FUNCTION Reserved TYPE RW DESCRIPTION Reset to 04001060h. 6.2.37. XPIP CSR1 – OFFSET ACh (Test Purpose Only) BIT 31:0 FUNCTION Reserved PI7C9X7954 Document Number DS40138 Rev 2-2 TYPE RW DESCRIPTION Reset to 004000271h. Page 31 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6.2.38. REPLAY TIME-OUT COUNTER – OFFSET B0h BIT FUNCTION 11:0 User Replay Timer TYPE RW DESCRIPTION A 12-bit register contains a user-defined value. The default value may be changed by auto-loading from EEPROM. 12 Enable User Replay Timer RW Reset to 000h. When asserted, the user-defined replay time-out value would be employed. The default value may be changed by auto-loading from EEPROM. 15:13 Reserved RO Reset to 0b. Reset to 000b. 6.2.39. ACKNOWLEDGE LATENCY TIMER – OFFSET B0h BIT FUNCTION 29:16 User ACK Latency Timer TYPE RW DESCRIPTION A 14-bit register contains a user-defined value. The default value may be changed by auto-loading from EEPROM. 30 Enable User ACK Latency RW Reset to 0000h.. When asserted, the user-defined ACK latency value would be employed. The default value may be changed by auto-loading from EEPROM. 31 Reserved RO Reset to 0b. Reset to 0b. 6.2.40. UART DRIVER SETTING – OFFSET B4h BIT FUNCTION 3:0 UART 0 Transmitter Driver Enable TYPE RW DESCRIPTION UART 0 DRIVER. The default value may be changed by auto-loading from EEPROM. 0000b: RS232 0001b: RS422 1011b: RS485-4W 1111b: RS485-2W Reset to 0000b. UART 1 DRIVER. The default value may be changed by auto-loading from EEPROM. 7:4 UART 1 Transmitter Driver Enable RW 0000b: RS232 0001b: RS422 1011b: RS485-4W 1111b: RS485-2W Reset to 0000b. UART 2 DRIVER. The default value may be changed by auto-loading from EEPROM. 11:8 UART 2 Transmitter Driver Enable RW 27:12 Reserved RW 31:28 UART 3 Transmitter Driver Enable RW PI7C9X7954 Document Number DS40138 Rev 2-2 0000b: RS232 0001b: RS422 1011b: RS485-4W 1111b: RS485-2W Reset to 0000b. Reserved UART 3 DRIVER. The default value may be changed by auto-loading from EEPROM. 0000b: RS232 0001b: RS422 Page 32 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT FUNCTION TYPE DESCRIPTION 1011b: RS485-4W 1111b: RS485-2W Reset to 0000b. 6.2.41. POWER MANAGEMENT CONTROL PARAMETER – OFFSET B8h BIT FUNCTION 5:0 Power Management Control Parameter TYPE RW 31:6 Reserved RO DESCRIPTION The default value may be changed by auto-loading from EEPROM. Reset to 000001b. Reset to 0000000h. 6.2.42. DEBUG REGISTER 1 – OFFSET BCh (Test Purpose Only) BIT FUNCTION 31:0 Debug Register 1 TYPE DESCRIPTION Used for test purpose only. RO Reset to 00000000h. 6.2.43. DEBUG REGISTER 2 – OFFSET C0h (Test Purpose Only) BIT FUNCTION 31:0 Debug Register 2 TYPE DESCRIPTION Used for test purpose only. RO Reset to 00000000h. 6.2.44. DEBUG REGISTER 3 – OFFSET C4h (Test Purpose Only) BIT FUNCTION 31:0 Debug Register 3 TYPE DESCRIPTION Used for test purpose only. RO Reset to 00000000h. 6.2.45. DEBUG REGISTER 4 – OFFSET C8h (Test Purpose Only) BIT FUNCTION TYPE 0 Low Driver Current HwInt 1 High Driver Current HwInt 5:2 9:6 11:10 13:12 31:14 Driver Transmit Current De-emphasis Transmit Equalization Receive Termination Adjustment Transmit Termination Adjustment Reserved HwInt DESCRIPTION It indicates the status of the strapping pin LODRV. The default value may be changed by auto-loading from EEPROM. It indicates the status of the strapping pin HIDRV. The default value may be changed by auto-loading from EEPROM. It indicates the status of the strapping pins DTX[3:0]. The default value may be changed by auto-loading from EEPROM. It indicates the status of the strapping pins DEQ[3:0]. The default value may be changed by auto-loading from EEPROM. HwInt It indicates the status of the strapping pins RXTRMADJ[1:0]. The default value may be changed by auto-loading from EEPROM. HwInt It indicates the status of the strapping pins TXTRMADJ[1:0]. The default value may be changed by auto-loading from EEPROM. HwInt RO Reset to 00000h. 6.2.46. GPIO CONTROL REGISTER – OFFSET D8h BIT FUNCTION 7:0 GPIO Input PI7C9X7954 Document Number DS40138 Rev 2-2 TYPE RO DESCRIPTION The current state of the GPIO[x] pin can be read from bit[x] in this register, where x=7 to 0. The bits are effective only when the corresponding GPIO I/O Enable bits are set to “0”. Page 33 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT FUNCTION TYPE 15:8 GPIO I/O Enable RW 23:16 GPIO Output RW 31:24 Reserved RO DESCRIPTION These 8 bits determine whether the GPIO pins are input or output pins. Bit[x+8] corresponds to GPIO[x], where x=7 to 0. If the bit is set to “0”, the corresponding GPIO pin is an input pin. If the bit is set to “1”, the corresponding GPIO pin is an output pin. The current state of the GPIO[x] pin can be written by bit[x+16] in this register, where x=7 to 0. The bits are effective only when the corresponding GPIO I/O Enable bits are set to “1”. Reserved 6.2.47. EEPROM CONTROL REGISTER – OFFSET DCh BIT FUNCTION 0 EEPROM Start RW 1 Reserved RO 2 EEPROM Preload Control RW EEPROM Operation Command RW 4:3 TYPE DESCRIPTION Starts the EEPROM read or write cycle. Reset to 0b. Reset to 0b. Enable preload start. Reset to 0b. EEPROM Operation Command. 00b: Reserved 01b: Write operation command 10b: Read operation command 11b: Reserved Reset to 00b. EEPROM RW address. 15:5 31:16 EEPROM Address EEPROM Write DATA Buffer RW Reset to 000h. EEPROM write data buffer register. RW Reset to 0000h. 6.2.48. PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h BIT 7:0 FUNCTION Enhanced Capabilities ID TYPE RO DESCRIPTION Read as 10h to indicate that these are PCI express enhanced capability registers. 6.2.49. NEXT ITEM POINTER REGISTER – OFFSET E0h BIT FUNCTION 15:8 Next Item Pointer TYPE DESCRIPTION Read as 00h. No other ECP registers. RO Reset to 00h. 6.2.50. PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h BIT FUNCTION 19:16 Capability Version RO 23:20 Device/Port Type RO 24 Slot Implemented Interrupt Message Number Reserved RO 29:25 31:30 PI7C9X7954 Document Number DS40138 Rev 2-2 TYPE RO RO DESCRIPTION Read as 0001b to indicate the I/O bridge is compliant to Revision 1.0a of PCI Express Base Specifications. Indicates the type of Legacy PCI Express Endpoint device. Reset to 1h. It is not implemented. Hardwired to 0b. It is not implemented. Hardwired to 00000b. Reset to 00b. Page 34 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6.2.51. DEVICE CAPABILITIES REGISTER – OFFSET E4h BIT FUNCTION 2:0 Max_Payload_Size Supported 4:3 5 8:6 11:9 12 13 14 Phantom Functions Supported Extended Tag Field Supported Endpoint L0s Acceptable Latency Endpoint L1 Acceptable Latency Attention Button Present Attention Indicator Present Power Indicator Present TYPE RO RO RO RO RO RO RO RO 15 Role_Base Error Reporting RO 17:16 Reserved RO 25:18 Captured Slot Power Limit Value RO DESCRIPTION Indicates the maximum payload size that the I/O bridge can support for TLPs. The I/O bridge supports 128 bytes max payload size. Reset to000b. It is not implemented. Hardwired to 00b. It is not implemented. Hardwired to 0b. Acceptable total latency that an Endpoint can withstand due to the transition from L0s state to the L0 state. Reset to 000b. Acceptable total latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. Reset to 000b. It is not implemented. Hardwired to 0b. It is not implemented. Hardwired to 0b. It is not implemented. Hardwired to 0b. When set, indicated that the device implements the functionality originally defined in the Error Reporting ECN. The default value may be changed by auto-loading from EEPROM. Reset to 1b. Reset to 00b. In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. This value is set by the Set_Slot_Power_Limit message or hardwired to “00h”. Reset to 00b. Specifies the scale used for the Slot Power Limit Value. 27:26 Captured Slot Power Limit Scale RO 31:28 Reserved RO This value is set by the Set_Slot_Power_Limit message or hardwired to “00b”. Reset to 00b. Reset to 0h. 6.2.52. DEVICE CONTROL REGISTER – OFFSET E8h BIT FUNCTION 0 Correctable Error Reporting Enable 1 Non-Fatal Error Reporting Enable 2 Fatal Error Reporting Enable 3 Unsupported Request Reporting Enable PI7C9X7954 Document Number DS40138 Rev 2-2 TYPE RW RW RW RW DESCRIPTION 0b: Disable Correctable Error Reporting. 1b: Enable Correctable Error Reporting. Reset to 0b. 0b: Disable Non-Fatal Error Reporting. 1b: Enable Non-Fatal Error Reporting. Reset to 0b. 0b: Disable Fatal Error Reporting. 1b: Enable Fatal Error Reporting. Reset to 0b. 0b: Disable Unsupported Request Reporting. 1b: Enable Unsupported Request Reporting. Reset to 0b. Page 35 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT FUNCTION 4 Enable Relaxed Ordering RO Max_Payload_Size RW 7:5 8 9 10 11 14:12 15 Extended Tag Field Enable Phantom Function Enable Auxiliary (AUX) Power PM Enable Enable No Snoop Max_Read_ Request_Size Reserved TYPE RO RO RWS RO RO RO DESCRIPTION It is not implemented. Reset to 0b. This field sets maximum TLP payload size for the device. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported in the Device Capabilities register. Any value exceeding the Max_Payload_Size Supported written to this register results into clamping to the Max_Payload_Size Supported value. Reset to 000b. It is not implemented. Hardwired to 0b. It is not implemented. Hardwired to 0b. When set, indicates that the I/O bridge is enabled to draw AUX power independent of PME AUX power. Reset to 0b. It is not implemented. Hardwired to 0b. It is not implemented. Hardwired to 000b. Reset to 0b. 6.2.53. DEVICE STATUS REGISTER – OFFSET E8h BIT FUNCTION TYPE 16 Correctable Error Detected RW1C DESCRIPTION Asserted when correctable error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. RW1C Reset to 0b. Asserted when non-fatal error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. RW1C Reset to 0b. Asserted when fatal error is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. RW1C Reset to 0b. Asserted when unsupported request is detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 17 18 Non-Fatal Error Detected Fatal Error Detected 19 Unsupported Request Detected 20 AUX Power Detected 21 31:22 Transactions Pending Reserved Reset to 0b. Asserted when the AUX power is detected by the I/O bridge RO RO RO Reset to 1b. It is not implemented. Hardwired to 0b. Reset to 000h. 6.2.54. LINK CAPABILITIES REGISTER – OFFSET ECh BIT FUNCTION 3:0 Maximum Link Speed TYPE DESCRIPTION Indicates the Maximum Link Speed of the given PCIe Link. RO Defined encodings are: 0001b, which indicates 2.5 Gb/s Link Reset to 1h. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 36 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT 9:4 11:10 14:12 FUNCTION TYPE Maximum Link Width RO Active State Power Management (ASPM) Support RO L0s Exit Latency RO 17:15 L1 Exit Latency RO 23:18 31:24 Reserved Port Number RO RO DESCRIPTION Indicates the maximum width of the given PCIe Link. Reset to 000001b (x1). Indicates the level of ASPM supported on the given PCIe Link. The I/O bridge supports L0s and L1 entry. The default value may be changed by auto-loading from EEPROM. Reset to 11b. Indicates the L0s exit latency for the given PCIe Link. The length of time this I/O bridge requires to complete transition from L0s to L0 is in the range of 256ns to less than 512ns. The default value may be changed by auto-loading from EEPROM. Reset to 011b. Indicates the L1 exit latency for the given PCIe Link. The length of time this I/O bridge requires to complete transition from L1 to L0 is in the range of 16us to less than 32us. The default value may be changed by auto-loading from EEPROM. Reset to 000b. Reset to 00000b. It is not implemented. Hardwired to 00h. 6.2.55. LINK CONTROL REGISTER – OFFSET F0h BIT FUNCTION 1:0 Active State Power Management (ASPM) Control 2 3 4 5 6 Reserved Read Completion Boundary (RCB) Link Disable Retrain Link Common Clock Configuration TYPE DESCRIPTION 00b: ASPM is Disabled. 01b: L0s Entry Enabled. 10b: L1 Entry Enabled. 11b: L0s and L1 Entry Enabled. RW Note that the receiver must be capable of entering L0s even when the field is disabled. RO RO RO RO RW Reset to 00b. Reset to 0h. It is not implemented. Hardwired to 0b. It is not implemented. Hardwired to 0b. It is not implemented. Hardwired to 0b. 0b: The components at both ends of a link are operating with asynchronous reference clock. 1b: The components at both ends of a link are operating with a distributed common reference clock. 7 Extended Synch RW Reset to 0b. When set, it transmits 4096 FTS ordered sets in the L0s state for entering L0 state and transmits 1024 TS1 ordered sets in the L1 state for entering L0 state 15:8 RsvdP RO Reset to 0b. Reset to 00h. 6.2.56. LINK STATUS REGISTER – OFFSET F0h BIT FUNCTION 19:16 Link Speed 25:20 Negotiated Link Width PI7C9X7954 Document Number DS40138 Rev 2-2 TYPE DESCRIPTION Indicates the negotiated Link Speed of the given PCIe Link. RO Defined encodings are: 0001b, which indicates 2.5 Gb/s Link Reset to 1h. Indicates the negotiated width of the given PCIe Link, RO Reset to 000001b. Page 37 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT FUNCTION TYPE 26 Training Error RO 27 28 31:29 Link Training Slot Clock Configuration Reserved RO RO RO DESCRIPTION When set, indicates a Link training error occurred. This bit is cleared by hardware upon successful training of the link to the L0 link state. Reset to 0b. When set, indicates the link training is in progress. Hardware clears this bit once link training is complete. Reset to 0b. It is not implemented. Hardwired to 0b. Reset to 000b. 6.2.57. PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h BIT 15:0 FUNCTION Extended Capabilities ID TYPE RO DESCRIPTION Read as 0001h to indicate that these are PCI express extended capability registers for advance error reporting. 6.2.58. CAPABILITY VERSION – OFFSET 100h BIT FUNCTION 19:16 Capability Version TYPE RO DESCRIPTION Indicates PCI-SIG defined PCI Express capability structure version number. Reset to 1h. 6.2.59. NEXT ITEM POINTER REGISTER – OFFSET 100h BIT FUNCTION 31:20 Next Capability Offset TYPE DESCRIPTION Read as 00h. No other ECP registers. RO Reset to 000h. 6.2.60. UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h BIT FUNCTION TYPE 0 Training Error Status RW1CS 3:1 Reserved 4 Data Link Protocol Error Status 11:5 Reserved 12 Poisoned TLP Status 13 14 15 RO RW1CS RO RW1CS Flow Control Protocol Error Status RW1CS Completion Timeout Status RW1CS Completer Abort Status RW1CS PI7C9X7954 Document Number DS40138 Rev 2-2 DESCRIPTION When set, indicates that the Training Error event has occurred. Reset to 0b. Reset to 000b. When set, indicates that the Data Link Protocol Error event has occurred. Reset to 0b. Reset to 0000000b. When set, indicates that a Poisoned TLP has been received or generated. Reset to 0b. When set, indicates that the Flow Control Protocol Error event has occurred. Reset to 0b. When set, indicates that the Completion Timeout event has occurred. Reset to 0b. When set, indicates that the Completer Abort event has occurred. Reset to 0b. Page 38 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT FUNCTION TYPE 16 Unexpected Completion Status RW1CS Reset to 0b. When set, indicates that the Receiver Overflow event has occurred. Receiver Overflow Status RW1CS Malformed TLP Status RW1CS 19 ECRC Error Status RW1CS 20 Unsupported Request Error Status 31:21 Reserved 17 18 DESCRIPTION When set, indicates that the Unexpected Completion event has occurred. Reset to 0b. When set, indicates that a Malformed TLP has been received. Reset to 0b. When set, indicates that an ECRC Error has been detected. Reset to 0b. When set, indicates that an Unsupported Request event has occurred. RW1CS RO Reset to 0b. Reset to 000h. 6.2.61. UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h BIT FUNCTION TYPE 0 Training Error Mask RWS 3:1 Reserved 4 Data Link Protocol Error Mask 11:5 Reserved 12 Poisoned TLP Mask 13 14 15 16 17 18 Flow Control Protocol Error Mask Completion Timeout Mask Completer Abort Mask Unexpected Completion Mask Receiver Overflow Mask Malformed TLP Mask RO RWS RO RWS RWS RWS RWS RWS RWS RWS DESCRIPTION When set, the Training Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 000b. When set, the Data Link Protocol Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 0000000b. When set, an event of Poisoned TLP has been received or generated is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Flow Control Protocol Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Completion Timeout event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Completer Abort event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Unexpected Completion event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Receiver Overflow event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, an event of Malformed TLP has been received is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 39 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT FUNCTION TYPE 19 ECRC Error Mask RWS 20 Unsupported Request Error Mask 31:21 Reserved RWS RO DESCRIPTION When set, an event of ECRC Error has been detected is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the Unsupported Request event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 000h. 6.2.62. UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch BIT FUNCTION TYPE 0 Training Error Severity RWS 3:1 Reserved 4 Data Link Protocol Error Severity 11:5 Reserved 12 Poisoned TLP Severity 13 Flow Control Protocol Error Severity RWS Completion Timeout Error Severity RWS 15 Completer Abort Severity RWS 16 Unexpected Completion Severity RWS Receiver Overflow Severity RWS 14 17 18 Malformed TLP Severity 19 ECRC Error Severity 20 Unsupported Request Error Severity 31:21 Reserved PI7C9X7954 Document Number DS40138 Rev 2-2 RO RWS RO RWS RWS RWS RWS RO DESCRIPTION 0b: Non-Fatal. 1b: Fatal. Reset to 1b. Reset to 000b. 0b: Non-Fatal. 1b: Fatal. Reset to 1b. Reset to 0000000b. 0b: Non-Fatal. 1b: Fatal. Reset to 0b. 0b: Non-Fatal. 1b: Fatal. Reset to 1b. 0b: Non-Fatal. 1b: Fatal. Reset to 0b. 0b: Non-Fatal. 1b: Fatal. Reset to 0b. 0b: Non-Fatal. 1b: Fatal. Reset to 0b. 0b: Non-Fatal. 1b: Fatal. Reset to 1b. 0b: Non-Fatal. 1b: Fatal. Reset to 1b. 0b: Non-Fatal. 1b: Fatal. Reset to 0b. 0b: Non-Fatal. 1b: Fatal. Reset to 0b. Reset to 000h . Page 40 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 6.2.63. CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h BIT FUNCTION TYPE DESCRIPTION When set, the Receiver Error event is detected. 0 Receiver Error Status RW1CS 5:1 Reserved 6 Bad TLP Status Reset to 0b. Reset to 0h. When set, the event of Bad TLP has been received is detected. RO RW1CS Reset to 0b. When set, the event of Bad DLLP has been received is detected. 7 Bad DLLP Status 8 REPLAY_NUM Rollover status 11:9 Reserved 12 Replay Timer Timeout status 31:13 Reserved RW1CS Reset to 0b. When set, the REPLAY_NUM Rollover event is detected. RW1CS Reset to 0b. Reset to 000b. When set, the Replay Timer Timeout event is detected. RO RW1CS RO Reset to 0b. Reset to 00000h. 6.2.64. CORRECTABLE ERROR MASK REGISTER – OFFSET 114h BIT FUNCTION TYPE 0 Receiver Error Mask RWS 5:1 Reserved 6 Bad TLP Mask 7 Bad DLLP Mask 8 REPLAY_NUM Rollover Mask 11:9 Reserved 12 Replay Timer Timeout Mask 31:13 Reserved RO RWS RWS RWS RO RWS RO DESCRIPTION When set, the Receiver Error event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 0h. When set, the event of Bad TLP has been received is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the event of Bad DLLP has been received is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. When set, the REPLAY_NUM Rollover event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 000b. When set, the Replay Timer Timeout event is not logged in the Header Log register and not issued as an Error Message to RC either. Reset to 0b. Reset to 00000h . 6.2.65. ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h BIT FUNCTION 4:0 First Error Pointer 5 ECRC Generation Capable 6 ECRC Generation Enable PI7C9X7954 Document Number DS40138 Rev 2-2 TYPE ROS RO DESCRIPTION It indicates the bit position of the first error reported in the Uncorrectable Error Status register. Reset to 00000b. When set, it indicates the I/O bridge has the capability to generate ECRC. Reset to 1b. When set, it enables the generation of ECRC when needed. RWS Reset to 0b. Page 41 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT FUNCTION TYPE 7 ECRC Check Capable RO 8 ECRC Check Enable 31:9 Reserved DESCRIPTION When set, it indicates the I/O bridge has the capability to check ECRC. Reset to 1b. When set, the function of checking ECRC is enabled. RWS RO Reset to 0b. Reset to 000000h. 6.2.66. HEADER LOG REGISTER – OFFSET From 11Ch to 128h BIT FUNCTION st TYPE 3:0 1 DWORD RO 7:4 2nd DWORD RO rd 11:8 3 DWORD RO 15:12 4th DWORD RO PI7C9X7954 Document Number DS40138 Rev 2-2 DESCRIPTION Hold the 1st DWORD of TLP Header. The Head byte is in big endian. Hold the 2nd DWORD of TLP Header. The Head byte is in big endian. Hold the 3rd DWORD of TLP Header. The Head byte is in big endian. Hold the 4th DWORD of TLP Header. The Head byte is in big endian. Page 42 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 7. UART REGISTER DESCRIPTION 7.1. REGISTERS IN I/O MODE Each UART channel has a dedicated 8-byte register block in I/O mode. The register block can be accessed the UART I/O Base Address, which is obtained by adding the UART Register Offset to the content of the Base Address Register 0 (BAR0). The following diagram shows the arrangement of individual UART register blocks. UART I/O Base Address (BAR0 + UART Register Offset) UART Register Offset 000h UART0 Registers 008h UART1 Registers 010h UART2 Registers 038h UART3 Registers Figure 7-1 UART Register Block Arrangement in I/O Mode Table 7-1 UART Base Address in I/O Mode UART UART0 UART1 UART2 UART3 PI7C9X7954 Document Number DS40138 Rev 2-2 UART I/O Base Address BAR0 + 000h BAR0 + 008h BAR0 + 010h BAR0 + 038h Page 43 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 Each register in the UART Register Block can be access by adding an offset to the UART I/O Base Address. The following table lists the arrangement of the registers in the UART Register Block in I/O mode. Table 7-2 Registers in I/O Mode Offset Register Name Mnemonic UART I/O Base Address + 00h Receive Holding Register RHR UART I/O Base Address + 00h Transmit Holding Register THR UART I/O Base Address + 01h Interrupt Enable Register IER UART I/O Base Address + 02h Interrupt Status Register ISR UART I/O Base Address + 02h FIFO Control Register FCR UART I/O Base Address + 03h Line Control Register LCR UART I/O Base Address + 04h Modem Control Register MCR UART I/O Base Address + 05h Line Status Register LSR UART I/O Base Address + 06h Modem Status Register MSR UART I/O Base Address + 07h Special Function register SFR Additional Standard Registers (Required LCR[7] = 1) UART I/O Base Address + 00h Division Latch Low DLL UART I/O Base Address + 01h Division Latch High DLH UART I/O Base Address + 02h Sample Clock Register SCR 7.1.1. Register Type RO WO RW RO WO RW RW RO RO RW RW RW RW RECEIVE HOLDING REGISTER – OFFSET 00h BIT 7:0 FUNCTION Rx Holding TYPE RO DESCRIPTION Data received Reset to 00h. 7.1.2. TRANSMIT HOLDING REGISTER – OFFSET 00h BIT 7:0 FUNCTION Tx Holding TYPE WO DESCRIPTION Data to transmit Reset to 00h. 7.1.3. INTERRUPT ENABLE REGISTER – OFFSET 01h BIT 0 FUNCTION Rx Data Available Interrupt TYPE RW DESCRIPTION 0b: Disable the Receive Data Ready Interrupt 1b: Enable the Receive Data Ready Interrupt 1 Tx Empty Interrupt RW Reset to 0b. 0b: Disable the Transmit Holding Register Empty Interrupt 1b: Enable the Transmit Holding Register Empty Interrupt 2 Rx Status Interrupt RW Reset to 0b. 0b: Disable the Receive Line Status Interrupt 1b: Enable the Receive Line Status Interrupt 3 Modem Status Interrupt RW Reset to 0b. 0b: Disable the Modem Status Register Interrupt 1b: Enable the Modem Status Register Interrupt 4 Xoff/Special character interrupt RW Reset to 0b. 0b: Disable the Software Flow Control Interrupt 1b: Enable the Software Flow Control Interrupt 5 RTS Interrupt RW Reset to 0b. 0b: Disable RTS/DTR Interrupt 1b: Enable RTS/DTR Interrupt Reset to 0b. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 44 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT 6 FUNCTION CTS Interrupt TYPE RW 7 Reserved RW DESCRIPTION 0b: Disable CTS/DSR interrupt 1b: Enable CTS/DSR interrupt Reset to 0b. 7.1.4. INTERRUPT STATUS REGISTER – OFFSET 02h BIT 7:0 FUNCTION Interrupt Status TYPE RO DESCRIPTION 0b: An interrupt is pending 1b: No interrupt pending Reset to C1h. Priority Level 1 2 3 4 5 6 7.1.5. Interrupt Status Bits BIT-7 BIT-6 BIT-5 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 Interrupt Source BIT-4 0 0 0 0 0 1 BIT-3 0 0 1 0 0 0 BIT-2 1 1 1 0 0 0 BIT-1 1 0 0 1 0 0 BIT-0 0 0 0 0 0 0 7 1 1 1 0 0 0 0 0 X 1 1 0 0 0 0 0 1 Rx data error Rx data available Rx time-out Tx FIFO empty Modem status change Xoff or special character detected CTS or RTS state changed No interrupt pending FIFO CONTROL REGISTER – OFFSET 02h BIT 0 FUNCTION FIFO Mode Enable TYPE WO DESCRIPTION 0b: Disable the FIFO mode 1b: Enable the FIFO mode 1 Rx FIFO Flush WO Reset to 0b. 0b: No action 1b: Reset the receive FIFO, self-clear after resetting the FIFO 2 Tx FIFO Flush WO Reset to 0b. 0b: No action 1b: Reset the transmit FIFO, self-clear after resetting the FIFO 3 5:4 Reserved Tx Trigger Level WO WO Reset to 0b. Reset to 0b. In the Enhanced Mode. 00b: 16 01b: 32 10b: 64 11b: 112 7:6 Rx Trigger Level PI7C9X7954 Document Number DS40138 Rev 2-2 WO Reset to 00b. In the Non-Enhanced mode 00b: 1 01b: 4 10b: 8 11b: 14 Reset to 00b. Page 45 of 69 www.diodes.com In the Enhanced mode 00b: 15 01b: 31 10b: 63 11b: 111 October 2017 © Diodes Incorporated PI7C9X7954 7.1.6. LINE CONTROL REGISTER – OFFSET 03h BIT 1:0 FUNCTION Data Length TYPE RW 2 Stop-Bit Length RW DESCRIPTION 00b: 5-bit data length 01b: 6-bit data length 10b: 7-bit data length 11b: 8-bit data length Reset to 11b. Bit 2 value 0 1 1 Data length 5,6,7,8 5 6,7,8 Stop bit length 1 1.5 2 Reset to 0b. 5:3 Parity Type RW Bit 5 X 0 0 1 1 6 Transmission Break RW 7 Divisor Latch Enable RW Bit 4 X 0 1 0 1 Bit 3 0 1 1 1 1 Parity selection No parity Odd parity Even parity Mark Space Reset to 000b. 0b: No transmit break condition 1b: Force the transmitter output to a space for alerting the remote receiver of a line break condition. Reset to 0b. 0b: Data registers are selected 1b: Divisor latch registers are selected Reset to 0b. 7.1.7. MODEM CONTROL REGISTER – OFFSET 04h BIT 0 FUNCTION DTR Pin Control TYPE RW DESCRIPTION 0b: Forces DTR output high 1b: Forces DTR output low 1 RTS Pin Control RW Reset to 0b. 0b: Forces RTS output high 1b: Forces RTS output low 2 Output 1 RW Reset to 0b. When the Internal Loopback Mode is enabled by setting Modem Control Register Bit[4], output of the Output1 is routed to RI. 3 Output 2 RW Reset to 0b. When the Internal Loopback Mode is enabled by setting Modem Control Register Bit[4], output of the Output2 is routed to DCD. 4 Internal Loopback Mode RW Reset to 0b. 0b: Disables Internal Loopback Mode 1b: Enables Internal Loopback Mode Reset to 0b. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 46 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT 5 FUNCTION AFE TYPE RW DESCRIPTION Autoflow Control Enable. When the AFE is enabled, autoflow control is enabled. When it is disabled, the diagnostic mode is enabled. In the diagnostic mode, transmitted data is immediately received. When AFE is set to “1”, MCR Bit 1 is used to enable and disable the auto-RTS. 6 7 Reserved Enhanced Transmission RW MCR Bit 5 (AFE) 1 MCR Bit 1 (RTS) 1 1 0 0 x Configuration Auto-RTS and auto-CTS are enabled (autoflow control enabled). Only auto-CTS is enabled. Auto-RTS and auto-CTS are disabled. Reset to 0b. Reset to 0b. 0b: Insert 1, 1.5 or 2 stop-bits between two transmitted characters. 1b: Insert 0.5 stop-bits between two transmitted characters. Note: Enabling feature may result in certain compatibility issues. This feature is only recommended when using two Pericom UART devices. Reset to 0b. 7.1.8. LINE STATUS REGISTER – OFFSET 05h BIT 0 FUNCTION Rx Data Available TYPE RO DESCRIPTION 0b: No data in the receive FIFO 1b: Data in the receive FIFO 1 Rx FIFO Overrun RO Reset to 0b. 0b: No overrun error 1b: Overrun error 2 Rx Parity Error RO Reset to 0b. 0b: No parity error 1b: Parity error 3 Rx Frame Error RO Reset to 0b. 0b: No framing error 1b: Framing error 4 Rx Break Error RO Reset to 0b. 0b: No break condition 1b: Break condition 5 Tx Empty RO Reset to 0b. 0b: Tx Holding Register is not empty. 1b: Tx Holding Register is empty. 6 Tx Complete RO Reset to 0b. 0b: Tx Shift Register is not empty. 1b: Tx Shift Register is empty. 7 Rx Data Error RO Reset to 0b. 0b: No Rx FIFO error 1b: Rx FIFO error Reset to 0b. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 47 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 7.1.9. MODEM STATUS REGISTER – OFFSET 06h BIT 0 FUNCTION Delta CTS TYPE RO DESCRIPTION 0b: No change in CTS input. 1b: Indicates the CTS input has changed state. This bit is read-clear. 1 Delta DSR RO 2 Trailing RI Edge RO 3 Delta DCD RO 4 CTS RO Reset to 0b. 0b: The CTS input state is the logic 0 1b: The CTS input state is the logic 1 5 DSR RO Reset to 0b. 0b: The DSR input state is the logic 0 1b: The DSR input state is the logic 1 6 RI RO Reset to 0b. The input state of RI pin 7 DCD RO Reset to 0b. The input state of DCD pin Reset to 0b. 0b: No change in DSR input. 1b: Indicates the DSR input has changed state. This bit is read-clear. Reset to 0b. 0b: No change in RI input 1b: Indicates the RI input has changed state from the logic 0 to the logic 1. This bit is read-clear. Reset to 0b. 0b: No change in DCD input 1b: Indicates the DCD input has changed state. This bit is read-clear. Reset to 0b. 7.1.10. SPECIAL FUNCTION REGISTER – OFFSET 07h BIT 0 FUNCTION Force Transmission TYPE RW DESCRIPTION Forces transmitter to always to transmit data. 1b: Enabled 0b: Disabled 1 Auto DSR and DTR Flow Control RW Reset to 0b. Auto DSR and DTR flow control enable 1b: Enables DSR and DTR auto flow control 0b: Disables DSR and DTR auto flow control 2 3 4 5 Reserved Reserved Reserved 950 Mode RO RO RW RW Reset to 0b. Reset to 0b. Reset to 0b. Reset to 0b. 1b: Enables 950 mode 0b: Non-950 mode 6 RFD / LSR Counter Select RW Reset to 0b. 1b: OFFSET 15 bit[7:0] acts as the Line Status Register Counter 0b: OFFSET 15 bit[7:0] acts as the Receive FIFO Data Counter Reset to 0b. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 48 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT 7 FUNCTION TFD / SCR Select TYPE RW 7:6 Reserved RW DESCRIPTION 1b: OFFSET 16 bit[7:0] acts as the Transmit FIFO Data Counter 0b: OFFSET 16 bit[7:0] acts as the Sample Clock Register Reset to 0b. Reset to 00b. 7.1.11. DIVISOR LATCH LOW REGISTER – OFFSET 00h, LCR[7] = 1 BIT 7:0 FUNCTION Divisor Low TYPE RW DESCRIPTION Lower-part of the divisor register Reset to 00h. 7.1.12. DIVISOR LATCH HIGH REGISTER – OFFSET 01h, LCR[7] = 1 BIT 7:0 FUNCTION Divisor High TYPE RW DESCRIPTION Higher-part of the divisor register Reset to 00h. 7.1.13. SAMPLE CLOCK REGISTER – OFFSET 02h, LCR[7] = 1 BIT 3:0 FUNCTION Sample Clock TYPE RW DESCRIPTION This register determines the Sample Clock value (SC) used in the Baud Rate Generator. Please refer to 5.2.12 Baud Rate Generation for more detail 0000b: SC = 16 0001b: SC = 15 0010b: SC = 14 0011b: SC = 13 0100b: SC = 12 7:4 Reserve PI7C9X7954 Document Number DS40138 Rev 2-2 R 0101b: SC = 11 0110b: SC = 10 0111b: SC = 9 1000b: SC = 8 1001b: SC = 7 1010b: SC = 6 1011b: SC = 5 1100b: SC = 4 Other settings are reserved. Reset to 0h. Reset to 0h. Page 49 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 7.2. REGISTERS IN MEMORY-MAPPING MODE Each UART channel has a dedicated 512-byte register block in Memory mode. The register block can be accessed by the UART Memory Base Address, which is obtained by adding the UART Register Offset to the content of the Base Address Register 1 (BAR1). The following diagram shows the arrangement of individual UART register blocks. UART Memory Base Address (BAR1 + UART Register Offset) UART Register Offset 0000h UART0 Registers 0200h UART1 Registers 0400h UART2 Registers 0E00h UART3 Registers Figure 7-2 UART Register Block Arrangement in Memory Mode Table 7-3 UART Base Address in Memory Mode UART UART0 UART1 UART2 UART3 PI7C9X7954 Document Number DS40138 Rev 2-2 UART I/O Base Address BAR1 + 0000h BAR1 + 0200h BAR1 + 0400h BAR1 + 0E00h Page 50 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 Each register in the UART Register Block can be access by adding an offset to the UART Memory Base Address. The following table lists the arrangement of the registers in the UART Register Block in memory mode. Table 7-4 Memory-Map Mode Offset UART Memory Base Address + 00h UART Memory Base Address + 00h UART Memory Base Address + 01h UART Memory Base Address + 02h UART Memory Base Address + 02h UART Memory Base Address + 04h UART Memory Base Address + 04h UART Memory Base Address + 05h UART Memory Base Address + 06h UART Memory Base Address + 07h UART Memory Base Address + 08h UART Memory Base Address + 09h Register Name Receive Holding Register Transmit Holding Register Interrupt Enable Register Interrupt Status Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Special Function Register Divisor Latch Low Divisor Latch High UART Memory Base Address + 0Ah UART Memory Base Address + 0Bh Enhanced Function Register XON 1 Character/Special Character 1 XON 2 Character/Special Character 2 XOFF 1 Character/Special Character 3 XOFF 2 Character/Special Character 3 ACR Register Transmitter Interrupt Trigger Level Receiver Interrupt Trigger Level Automatic Flow control lower trigger level Automatic Flow control lower higher level Baud rate Prescale Receive FIFO Data Counter / Line Status Register Counter Transmit FIFO Data Counter / Sample Clock Register UART Memory Base Address + 0Ch UART Memory Base Address + 0Dh UART Memory Base Address + 0Eh UART Memory Base Address + 0Fh UART Memory Base Address + 10h UART Memory Base Address + 11h UART Memory Base Address + 12h UART Memory Base Address + 13h UART Memory Base Address + 14h UART Memory Base Address + 15h UART Memory Base Address + 16h UART Memory Base Address + 17h UART Memory Base Address + 100h ~17Fh UART Memory Base Address + 180h ~1FFh 7.2.1. Global Register of LSR UART0 FIFO DATA Register. Use this register to map FIFO data content. UART0 FIFO DATA LSR Register. Use this register to map FIFO data relative LSR content. Mnemonic RHR THR IER ISR FCR LCR MCR LSR MSR SFR DLL DLH Register Type RO WO RW RO WO RW RW RO RO RW WO WO EFR XON1 RW RW XON2 RW XOFF1 RW XOFF2 RW ASR TTL RW RW RTL FCL RW RW FCH RW CPR RFD / LSR Counter TFD Counter / SCR GLSR FIFO_D RW RO FIFO_LSR RW RW RW RW RECEIVE HOLDING REGISTER – OFFSET 00h BIT 7:0 FUNCTION Rx Holding TYPE RO DESCRIPTION When data are read from the Receive Holding Register (RHR), they are removed from the top of the receiver’s associated FIFOs, which holds a queue of data received by the receiver. Data read from the RHR when the FIFOs are empty are invalid. The Line Status Register (LSR) indicates the full or empty status of the FIFOs. Reset to 00h. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 51 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 7.2.2. TRANSMIT HOLDING REGISTER – OFFSET 00h BIT 7:0 FUNCTION Tx Holding TYPE WO DESCRIPTION When data are written to the Transmit Holding Register (THR), they are written to the bottom of the transmitter’s associated FIFOs, which holds a queue of data to be transmitted by the transmitter. Data written to the THR when the FIFOs are full are lost. The Line Status Register (LSR) indicates the full or empty status of the FIFOs. Reset to 00h. 7.2.3. 7.2.4. INTERRUPT ENABLE REGISTER – OFFSET 01h BIT 0 FUNCTION Rx Data Available Interrupt TYPE RW DESCRIPTION 0b: Disable the Receive Data Ready Interrupt 1b: Enable the Receive Data Ready Interrupt 1 Tx Empty Interrupt RW Reset to 0b. 0b: Disable the Transmit Holding Register Empty Interrupt 1b: Enable the Transmit Holding Register Empty Interrupt 2 Rx Error Status RW Reset to 0b. 0b: Disable the Receive Line Status Interrupt 1b: Enable the Receive Line Status Interrupt 3 Modem Status Interrupt RW Reset to 0b. 0b: Disable the Modem Status Register Interrupt 1b: Enable the Modem Status Register Interrupt 4 Xoff/Special character interrupt RW Reset to 0b. 0b: Disable the Software Flow Control Interrupt 1b: Enable the Software Flow Control Interrupt 5 RTS Interrupt RW Reset to 0b. 0b: Disable RTS/DTR Interrupt 1b: Enable RTS/DTR Interrupt 6 CTS Interrupt RW Reset to 0b. 0b: Disable CTS/DSR interrupt 1b: Enable CTS/DSR interrupt 7 Reserved RW Reset to 0b. Reset to 0b. INTERRUPT STATUS REGISTER – OFFSET 02h BIT 7:0 FUNCTION Interrupt Status TYPE RO DESCRIPTION 0b: An interrupt is pending 1b: No interrupt pending Reset to C1h. Priority Level 1 2 3 4 5 6 Interrupt Status Bits BIT-7 BIT-6 BIT-5 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 PI7C9X7954 Document Number DS40138 Rev 2-2 Interrupt Source BIT-4 0 0 0 0 0 1 BIT-3 0 0 1 0 0 0 BIT-2 1 1 1 0 0 0 Page 52 of 69 www.diodes.com BIT-1 1 0 0 1 0 0 BIT-0 0 0 0 0 0 0 Rx data error Rx data available Rx time-out Tx FIFO empty Modem status change Xoff or special character detected October 2017 © Diodes Incorporated PI7C9X7954 7.2.5. 7 1 1 1 0 0 0 0 0 X 1 1 0 0 0 0 0 1 CTS or RTS state changed No interrupt pending FIFO CONTROL REGISTER – OFFSET 02h BIT 0 FUNCTION FIFO Mode Enable TYPE WO DESCRIPTION 0b: Disable the FIFO mode 1b: Enable the FIFO mode 1 Rx FIFO Flush WO Reset to 0b. 0b: No action 1b: Reset the receive FIFO, self-clear after resetting the FIFO 2 Tx FIFO Flush WO Reset to 0b. 0b: No action 1b: Reset the transmit FIFO, self-clear after resetting the FIFO 3 5:4 Reserved Tx Trigger Level WO WO Reset to 0b. Reset to 0b In the Enhanced Mode: 00b: 16 01b: 32 10b: 64 11b: 112 7:6 7.2.6. Rx Trigger Level WO Reset to 00b. In the Non-Enhanced mode 00b: 1 01b: 4 10b: 8 11b: 14 Reset to 00b. In the Enhanced mode 00b: 15 01b: 31 10b: 63 11b: 111 LINE CONTROL REGISTER – OFFSET 03h BIT 1:0 FUNCTION Data Length TYPE RW 2 Stop-Bit Length RW DESCRIPTION 00b: 5-bit data length 01b: 6-bit data length 10b: 7-bit data length 11b: 8-bit data length Reset to 00b. Bit 2 value 0 1 1 Data length 5,6,7,8 5 6,7,8 Stop bit length 1 1.5 2 Reset to 0b. 5:3 Parity Type RW Bit 5 X 0 0 1 1 6 Transmission Break RW Bit 4 X 0 1 0 1 Bit 3 0 1 1 1 1 Parity selection No parity Odd parity Even parity Mark Space Reset to 000b. 0b: No transmit break condition 1b: Force the transmitter output to a space for alerting the remote receiver of a line break condition. Reset to 0b. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 53 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT 7 FUNCTION Divisor Latch Enable TYPE RW DESCRIPTION 0b: Data registers are selected 1b: Divisor latch registers are selected Reset to 0b. 7.2.7. MODEM CONTROL REGISTER – OFFSET 04h BIT 0 FUNCTION DTR Pin Control TYPE RW DESCRIPTION 0b: Forces DTR output high 1b: Forces DTR output low 1 RTS Pin Control RW Reset to 0b. 0b: Forces RTS output high 1b: Forces RTS output low 2 Output 1 RW Reset to 0b. When the Internal Loopback Mode is enabled by setting Modem Control Register Bit[4], output of the Output1 is routed to RI. 3 Output 2 RW Reset to 0b. When the Internal Loopback Mode is enabled by setting Modem Control Register Bit[4], output of the Output2 is routed to DCD. 4 Internal Loopback Mode RW Reset to 0b. 0b: Disables Internal Loopback Mode 1b: Enables Internal Loopback Mode 5 AFE RW Reset to 0b. Autoflow Control Enable. When the AFE is enabled, autoflow control is enabled. When it is disabled, the diagnostic mode is enabled. In the diagnostic mode, transmitted data is immediately received. When AFE is set to “1”, MCR Bit 1 is used to enable and disable the auto-RTS. 6 7 Reserved Enhanced Transmission RW MCR Bit 5 (AFE) 1 MCR Bit 1 (RTS) 1 1 0 0 x Configuration Auto-RTS and auto-CTS are enabled (autoflow control enabled). Only auto-CTS is enabled. Auto-RTS and auto-CTS are disabled. Reset to 0b. Reset to 0b. 0b: Insert 1, 1.5 or 2 stop-bits between two transmitted characters. 1b: Insert 0.5 stop-bits between two transmitted characters. Note: Enabling feature may result in certain compatibility issues. This feature is only recommended when using two Pericom UART devices. Reset to 0b. 7.2.8. LINE STATUS REGISTER – OFFSET 05h BIT 0 FUNCTION Rx Data Available TYPE RO DESCRIPTION 0b: No data in the receive FIFO 1b: Data in the receive FIFO Reset to 0b. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 54 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT 1 FUNCTION Rx FIFO Overrun TYPE RO DESCRIPTION 0b: No overrun error 1b: Overrun error 2 Rx Parity Error RO Reset to 0b. 0b: No parity error 1b: Parity error 3 Rx Frame Error RO Reset to 0b. 0b: No framing error 1b: Framing error 4 Rx Break Error RO Reset to 0b. 0b: No break condition 1b: Break condition 5 Tx Empty RO Reset to 0b. 0b: Tx Holding Register is not empty. 1b: Tx Holding Register is empty. 6 Tx Complete RO Reset to 0b. 0b: Tx Shift Register is not empty. 1b: Tx Shift Register is empty. 7 Rx Data Error RO Reset to 0b. 0b: No Rx FIFO error 1b: Rx FIFO error Reset to 0b. 7.2.9. MODEM STATUS REGISTER – OFFSET 06h BIT 0 FUNCTION Delta CTS TYPE RO DESCRIPTION 0b: No change in CTS input. 1b: Indicates the CTS input has changed state. This bit is read-clear. 1 Delta DSR RO 2 Delta RI RO 3 Delta DCD RO 4 CTS RO Reset to 0b. 0b: The CTS input state is the logic 0 1b: The CTS input state is the logic 1 5 DSR RO Reset to 0b. 0b: The DSR input state is the logic 0 1b: The DSR input state is the logic 1 6 RI RO Reset to 0b. 0b: No change in DSR input. 1b: Indicates the DSR input has changed state. This bit is read-clear. Reset to 0b. 0b: No change in RI input 1b: Indicates the RI input has changed state from the logic 0 to the logic 1. This bit is read-clear. Reset to 0b. 0b: No change in DCD input 1b: Indicates the DCD input has changed state. This bit is read-clear. Reset to 0b. The input state of RI pin Reset to 0b. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 55 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT 7 FUNCTION DCD TYPE RO DESCRIPTION The input state of DCD pin Reset to 0b. 7.2.10. SPECIAL FUNCTION REGISTER – OFFSET 07h BIT 0 FUNCTION Force Transmission TYPE RW DESCRIPTION Forces transmitter to always to transmit data. 1b: Enabled 0b: Disabled 1 Auto DSR and DTR Flow Control RW Reset to 0b. Auto DSR and DTR flow control enable 1b: Enables DSR and DTR auto flow control 0b: Disables DSR and DTR auto flow control 2 3 4 5 Reserved Reserved Reserved 950 Mode RO RO RW RW Reset to 0b. Reset to 0b. Reset to 0b. Reset to 0b. 1b: Enables 950 mode 0b: Non-950 mode 6 RFD / LSR Counter Select RW Reset to 0b. 1b: OFFSET 15 bit[7:0] acts as the Line Status Register Counter 0b: OFFSET 15 bit[7:0] acts as the Receive FIFO Data Counter 7 TFD / SCR Select RW Reset to 0b. 1b: OFFSET 16 bit[7:0] acts as the Transmit FIFO Data Counter 0b: OFFSET 16 bit[7:0] acts as the Sample Clock Register Reset to 0b. 7.2.11. DIVISOR LATCH LOW REGISTER – OFFSET 08h BIT 7:0 FUNCTION Divisor Low TYPE RW DESCRIPTION Lower-part of the divisor register Reset to 00h. 7.2.12. DIVISOR LATCH HIGH REGISTER – OFFSET 09h BIT 7:0 FUNCTION Divisor High TYPE RW DESCRIPTION Higher-part of the divisor register Reset to 00h. 7.2.13. ENHANCED FUNCTION REGISTER – OFFSET 0Ah BIT 1:0 FUNCTION In-Band Receive Flow Control Mode TYPE RW DESCRIPTION When in-band receive flow control is enabled, the UART compares the received data with the programmed XOFF character(s). When this occurs, the UART will disable transmission as soon as any current character transmission is complete. The UART then compares the received data with the programmed XON character(s). When a match occurs, the UART will re-enable transmission (see section 7.11.6). 00b: In-band receive flow control is disabled. 01b: Single character in-band receive flow control enabled, PI7C9X7954 Document Number DS40138 Rev 2-2 Page 56 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT FUNCTION TYPE 3:2 In-Band Transmit Flow Control Mode RW DESCRIPTION recognising XON2 as the XON character and XOFF2 as the XOFF character. 10b: Single character in-band receive flow control enabled, recognising XON1 as the XON character and XOFF1 and the XOFF character. 11b: The behavior of the receive flow control is dependent on the configuration of EFR[3:2]. Single character in-band receive flow control is enabled, accepting XON1 or XON2 as valid XON characters and XOFF1 or XOFF2 as valid XOFF characters when EFR[3:2] = “01” or “10”. EFR[1:0] should not be set to “11” when EFR[3:2] is ‘00’. Reset to 00b. When in-band transmit flow control is enabled, XON/XOFF character are inserted into the data stream whenever the RFL passes the upper trigger level and falls below the lower trigger level respectively. For automatic in-band flow control, bit 4 of EFR must be set. The combinations of software transmit flow control can then be selected by programming EFR[3:2] as follows. 00b: 01b: -band transmit flow control is disabled logic. -band transmit flow control enabled, using XON2 as the XON character and XOFF2 as the XOFF character. 10b: -band transmit flow control enabled, using XON1 as the XON character and XOFF1 as the XOFF character. 11b: The value EFR[3:2] = “11” is reserved for future use and should not be used 4 Enhanced Mode RW 5 Special Character Detection Enable RW 6 Automatic RTS Flow Control Enable RW 7 Automatic CTS Flow Control Enable RW Reset to 00b. 0b: -Enhanced mode. 1b: use addition function except 16550 mode. functions. If Reset to 0b. 0b: Special character detection is disabled. 1b: While in Enhanced mode (EFR[4]=1), the UART compares the incoming receiver data with the XOFF1 or XOFF2 value and interrupt will be asserted. If In-Band Flow Control is enabled, this bit must be set to ‘1’. Reset to 0b. 0b: RTS flow control is disabled. 1b: RTS flow control is enabled in Enhanced mode (i.e. EFR[4] = 1), where the RTS# pin will be forced inactive high if the RFL reaches the upper flow control threshold. This will be released when the RFL drops below the lower threshold. 650 and 950-mode drivers should use different threshold level. Reset to 0b. 0b: CTS flow control is disabled (default). 1b: CTS flow control is enabled in Enhanced mode (i.e. EFR[4] = 1), where the data transmission is prevented whenever the CTS# pin is held inactive high. 650 and 950-mode drivers should use different threshold level. Reset to 0b. 7.2.14. XON SPECIAL CHARACTER 1 – OFFSET 0Bh BIT 7:0 FUNCTION XON1 TYPE RW DESCRIPTION Xon character 1. Reset to 00h. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 57 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 7.2.15. XON SPECIAL CHARACTER 2 – OFFSET 0Ch BIT 7:0 FUNCTION XON2 TYPE RW DESCRIPTION Xon character 2. Reset to 00h. 7.2.16. XOFF SPECIAL CHARACTER 1 – OFFSET 0Dh BIT 7:0 FUNCTION XOFF1 TYPE RW DESCRIPTION Xoff character 1. Reset to 00h. 7.2.17. XOFF SPECIAL CHARACTER 2 – OFFSET 0Eh BIT 7:0 FUNCTION XOFF2 TYPE RW DESCRIPTION Xoff character 2. Reset to 00h. 7.2.18. ADVANCE CONTROL REGISTER – OFFSET 0Fh BIT 0 FUNCTION Transmitter Terminate Condition TYPE RO DESCRIPTION Indicates current transmitter terminate condition. If transmitter is disabled by remote terminate, the condition can be shown by this bit. 1b: Disabled by remote terminate. 0b: The transmitter can transmit data normally. 1 Remote TX Disable RO Reset to 0b. Remote TX Disable. 1b: If transmitter has sent XOFF message or RTS message, then DTR is inactive, and then it is enabled. 0b: otherwise 2 Xon/Xoff Detect RO Reset to 0b. When receiving a XON/XOFF character from a remote transmitter, this bit is set to ‘1’. Otherwise, this bit is set to ‘0’. The bit is read-clear. If the Xoff/Special Character Interrupt is enabled, the Xoff Detect status is also reflected in the Interrupt Status Register (Priority Level 6). 1b: Event true 0b: Event false 3 Special Character Detect RO Reset to 0b. When detecting the special characters from a remote transmitter, this bit is set to ‘1’. Otherwise, this bit is set to ‘0’. The bit is read-clear. If the Xoff/Special Character Interrupt is enabled, the status is also reflected in the Interrupt Status Register (Priority Level 6). 1b: Event true 0b: Event false 7:4 Reserved PI7C9X7954 Document Number DS40138 Rev 2-2 RO Reset to 0b. Reset to 0000b. Page 58 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 7.2.19. TRANSMIT INTERRUPT TRIGGER LEVEL – OFFSET 10h BIT 7:0 FUNCTION TTL TYPE RW DESCRIPTION Transmitter Interrupt Trigger Level. Reset to 00h. 7.2.20. RECEIVE INTERRUPT TRIGGER LEVEL – OFFSET 11h BIT 7:0 FUNCTION RTL TYPE RW DESCRIPTION Receiver Interrupt Trigger Level. Reset to 00h. 7.2.21. FLOW CONTROL LOW TRIGGER LEVEL – OFFSET 12h BIT 7:0 FUNCTION FCL TYPE RW DESCRIPTION Automatic Flow Control Low Trigger Level. Reset to 00h. 7.2.22. FLOW CONTROL HIGH TRIGGER LEVEL – OFFSET 13h BIT 7:0 FUNCTION FCH TYPE RW DESCRIPTION Automatic Flow Control High Trigger Level. Reset to 00h. 7.2.23. CLOCK PRESCALE REGISTER – OFFSET 14h BIT 3:0 FUNCTION CPRN TYPE RW 7:4 CPRM RW DESCRIPTION N number in calculating the Prescaler, which is used to generate the Baud Rate. Reset to 0000b. M number in calculating the Prescaler, which is used to generate the Baud Rate. It is recommended that the value of the CPRM be set to “0000”, “0001” or “0010”. Reset to 0000b. 7.2.24. RECEIVE FIFO DATA COUNTER – OFFSET 15h, SFR[6] = 0 The function of this register is selected by the Special Function Register (Offset 07h) bit 6. When SFR[6] is set to ‘1’, this register functions as the Receive FIFO Data Counter. Otherwise, it functions as the Line Status Register Counter. BIT 7:0 FUNCTION Receive FIFO Data Counter TYPE RO DESCRIPTION The Receive FIFO Data Counter indicates the amount of data in the Receive FIFO. Reset to 00h. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 59 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 7.2.25. LINE STATUS REGISTER COUNTER – OFFSET 15h, SFR[6] = 1 BIT 7:0 FUNCTION Line Status Register Counter TYPE RO DESCRIPTION The Line Status Register Counter indicates the amount of data in the LSR. Reset to 00h. 7.2.26. TRANSMIT FIFO DATA COUNTER – OFFSET 16h, SFR[7] = 1 The function of this register is selected by the Special Function Register (Offset 07h) bit 7. When SFR[7] is set to ‘1’, this register functions as the Transmit FIFO Data Counter. Otherwise, it functions as the Sample Clock Register. BIT 7:0 FUNCTION Transmit FIFO Data Counter TYPE RO DESCRIPTION The Transmit FIFO Data Counter indicates the amount of data in the Transmit FIFO. Reset to 00h. 7.2.27. SAMPLE CLOCK REGISTER – OFFSET 16h, SFR[7] = 0 BIT 3:0 FUNCTION Sample Clock TYPE RW DESCRIPTION This register determines the Sample Clock value (SC) used in the Baud Rate Generator. Please refer to 5.2.12 Baud Rate Generation for more detail 0000b: SC = 16 0001b: SC = 15 0010b: SC = 14 0011b: SC = 13 0100b: SC = 12 7:4 Reserved RO 0101b: SC = 11 0110b: SC = 10 0111b: SC = 9 1000b: SC = 8 1001b: SC = 7 1010b: SC = 6 1011b: SC = 5 1100b: SC = 4 Other settings are reserved. Reset to 0h. Reset to 0h. 7.2.28. GLOBAL LINE STATUS REGISTER – OFFSET 17h BIT 0 FUNCTION RX Data Available TYPE RO DESCRIPTION 0b: No data in the receive FIFO 1b: Data in the receive FIFO 1 RX FIFO Overrun RO Reset to 0b. 0b: No overrun error 1b: Overrun error 2 RX Parity Error RO Reset to 0b. 0b: No parity error 1b: Parity error 3 RX Frame Error RO Reset to 0b. 0b: No framing error 1b: Framing error 4 RX Break Error RO Reset to 0b. 0b: No break condition 1b: Break condition 5 TX Empty RO Reset to 0b. 0b: Tx Holding Register is not empty. 1b: Tx Holding Register is empty. Reset to 0b. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 60 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 BIT 6 FUNCTION TX Complete TYPE RO 7 RX Data Error RO DESCRIPTION 0b: Tx Shift Register is not empty. 1b: Tx Shift Register is empty. Reset to 0b. 0b: No Rx FIFO error 1b: Rx FIFO error Reset to 0b. 7.2.29. RECEIVE FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh BIT 7:0 FUNCTION Receive FIFO Data TYPE RO DESCRIPTION This register is used to map RX FIFO data content. Reset to 00h. 7.2.30. TRANSMIT FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh BIT 7:0 FUNCTION Transmit FIFO Data TYPE WO DESCRIPTION This register is used to map TX FIFO to memory space. Reset to 00h. 7.2.31. LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh BIT 7:0 FUNCTION Line Status FIFO TYPE RO DESCRIPTION This register is used to map FIFO data relative LSR content. Reset to 00h. PI7C9X7954 Document Number DS40138 Rev 2-2 Page 61 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 8. EEPROM INTERFACE The EEPROM interface consists of five pins: SR_DI (EEPROM data input), SR_DO (EEPROM data output), SR_CS (EEPROM chip select), SR_CLK_O (EEPROM clock output), and SR_ORG (EEPROM organization). The device may control a 93C56 or compatible parts using 2K bits. The EEPROM is used to initialize a number of registers before enumeration. This is accomplished at start-up when RTS[0] is de-asserted, at which time the data from the EEPROM is loaded. The EEPROM interface is organized into a 16-bit base, and the device supplies a 7-bit EEPROM word address. 8.1. AUTO MODE EERPOM ACCESS The device may access the EEPROM in a WORD or BYTE format, which is decided by the SR_ORG# at start-up. If SR_ORG# is asserted at start-up, EEPROM is accessed using the WORD format. Otherwise, Byte format is used. 8.2. EEPROM MODE AT RESET During a reset, the device will automatically load the information/data from the EEPROM if the automatic load condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized, and if RTS[0] is de-asserted, the autoload initiates right after the reset. 8.3. EEPROM SPACE ADDRESS MAP AND DESCRIPTION EEPROM ADDRESS 00h 02h 04h 06h 08h 0Ah PCIE REGISTER OFFSET Offset 00h bit[15:0] Offset 00h bit[31:16] Offset 2Ch bit[15:0] Offset 2Ch bit[31:16] Bit[0] - Offset 80h bit[21] Bit[3:1] - Offset 80h bit[24:22] DEFAULT Value A868h 12D8h 7954h 0000h 0000h 0b 111b Bit[4] - Offset 80h bit[25] 1b Bit[5] - Offset 80h bit[26] 1b Bit[10:6] - Offset 80h bit[31:27] Bit[11] - Offset 84h bit[3] 01000b 1b 0Ch 0Eh 10h Bit[13:12] - Offset A8h bit[14:13] Offset B0h bit[15:0] Offset B0h bit [31:16] Bit[1:0] - Offset ECh bit[11:10] 00b 0000h 0000h 11b 12h Bit[4:2] - Offset ECh bit[14:12] Bit[7:5] - Offset ECh bit[17:15] Offset B4h bit[15:0] 011b 000b 0000h PI7C9X7954 Document Number DS40138 Rev 2-2 DESCRIPTION Check Code Vendor ID Device ID Subsytem Vendor ID Subsytem ID Device Specific Initialization: When set, the DSI is required. Aux. Current: When set, the I/O bridge needs 375 mA in D3 state. D1 Support: When set, this bridge supports D1 Power Management state. D2 Support: When set, this bridge supports D2 Power Management state. PME Support: When set, the PME supports D1 and D2 Power Management states. No Soft Reset: When set, the device does not trigger the Internal Reset Command during the transition from D3hot to D0 power state. XPIP CSR0 Replay Time-out Counter Acknowledge Latency Timer ASPM Capability Support: When set, this bridge supports L0s and L1 entry Exit L0s Latency Timer Exit L1 Latency Timer UART Transmitter Drive Enable: RS232/422/485-2W/485-4W Selection for UART 0 to 3 Page 62 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 EEPROM ADDRESS 14h PCIE REGISTER OFFSET 16h Bit[1:0] - Offset B8h bit[17:16] 01b Bit[3:2] - Offset B8h bit[19:18] 00b Bit[5:4] - Offset B8h bit[21:20] 00b Bit[13:0] - Offset C8h bit[13:0] Bit[0] - Offset C4h bit[15] 0200h 1b 18h 1Ah Offset B4h bit[31:16] Bit[15:8] - Offset 34h bit[7:0] 1Ch 40h [7:0] - Offset 08h bit[7:0] PI7C9X7954 Document Number DS40138 Rev 2-2 DEFAULT Value 0000h 80h 00h 12D8h DESCRIPTION UART Transmitter Drive Enable: RS232/422/485-2W/485-4W Selection for UART 4 to 7 PM Control Parameter: Determines whether this bridge enters L1 or not when D3 condition occurs. PM Control Parameter: Determines the delay counter value when entering L1 PM Control Parameter: Determines whether this bridge asserts L0s/L1 handshake protocol PHY Parameter Role Based Error Report Enable: Indicates implement the role-base error reporting Capability List Pointer: Points to a linked list of new capabilities implemented by the device Revision ID: Indicates revision number of device Check Code Page 63 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 9. ELECTRICAL SPECIFICATION 9.1. ABSOLUTE MAXIMUM RATINGS Table 9-1 Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) --65oC to 150oC -0.3v to 2.1v Storage Temperature PCI Express supply voltage to ground potential (VDDA, VDDC, VTT and VDDCAUX) PCI supply voltage to ground potential (VDDR) DC input voltage for PCI Express signals -0.3v to 3.8v -0.3v to 2.1v Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 9.2. DC SPECIFICATIONS Table 9-2 DC Electrical Characteristics Symbol VDDA VDDC VDDCAUX VTT VDDR VIL VIH VOL VOH Min. 1.6v 1.6v 1.6v 1.6v 3.0v Typ. 1.8v 1.8v 1.8v 1.8v 3.3v Max. 2.0v 2.0v 2.0v 2.0v 3.6v 0.8v 2.0v 0.4v 2.6v VDDA: analog power supply for PCI Express Interface VDDC: digital power supply for the core VTT: termination power supply for PCI Express Interface VDDCAUX: auxiliary power supply VDDR: digital power supply for the I/O VIH: I/O input high voltage VIL: I/O input low voltage VOL: I/O output low voltage VOH: I/O output High voltage The typical power consumption of PI7C9X7954 is about 0.8 watt. 9.3. AC SPECIFICATIONS Table 9-3 Transmitter Characteristics Symbol Description Voltage Parameters VTX-DIFFa Output voltage compliance @ typical swing VTX-DIFFp (peak-to-peak, single ended) VTX-DIFFpp (peak-to-peak, differential) VSW Supported TX output voltage range (pp, differential) VOL Low-level output voltage VOH High-level output voltage VTX-CM-AC Transmit common-mode voltage in L0 PI7C9X7954 Document Number DS40138 Rev 2-2 Min Typical Max. Unit 400 800 700b 500 1000 600 1200 1400c mV mV mV 1.45 V V V 0.50 Page 64 of 69 www.diodes.com VTT - 1.5 *VTX-DIFFp VTT - 0.5VTX-DIFFp VTT - VTX-DIFFp October 2017 © Diodes Incorporated PI7C9X7954 Symbol VTX-CM-HiZ VTX-DE-RATIO VTX-IDLE-DIFFp VTX-RCV-DETECT Description Transmit common-mode voltage in L0s (TX) & L1 De-emphasized differential output voltage Electric Idle differential peak voltage Voltage change during Receive Detection Transmitter Differential Return loss Transmitter Common Mode Return loss Single-ended output impedance DC Differential TX Impedance Rise / Fall time of TxP, TxN outputs Min Typical VTX-CM-AC 0 Max. Unit V -7.96 dB 20 mV mV VTX-DIFFp RLTX-DIFF 10 RLTX-CM 6 ZOSE 40 ZTX-DIFF-DC 80 TTX-RISE, TTX-FALL 80 Jitter Parameters UI Unit Interval 399.88 TTX-MAX-JITTER Transmitter total jitter (peak-to-peak) TTX-EYE Minimum TX Eye Width (1 0.70 TTX-MAX-JITTER) TTX-EYE-MEDIAN-toMaximum time between the jitter median and MAX-JITTER maximum deviation from the median Timing Parameters LTLAT-10 Transmitter data latency (for n=10) 9 LTLAT-20 Transmitter data latency (for n=20) 9 LTX-SKEW Transmitter data skew between any 2 0 lanes TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid electrical idle after sending an Electrical Idle ordered set TEIExit Time to exit Electrical Idle (L0s) state into L0 TBTEn Time from asserting BeaconTxEn to beacon being transmitted on the lane a. Measured with Vtt = 1.2V, HiDrv=’0’,LowDrv=’0’ and Dtx=’0000’. b. Minimum swing assumes LoDrv = 1, HiDrv = 0 and Dtx =1100 c. Max swing assumes LoDrv = 0, HiDrv = 1, Dtx = 0010, VTT = 1.8V d. As measured between 20% and 80% points. Will depend on package characteristics. e. Measured using PCI Express Compliance Pattern dB dB Ω Ω ps 50 100 60 120 110d 400 400.12 0.30e ps UI UI 0.15 UI 11 11 2+ 200ps 8 UI UI UI 12 16 ns 30 80 ns Max. Unit ns Table 9-4 Receiver Characteristics Symbol Voltage Parameters VRX-DIFFp-p VRX-IDLE-DET-DIFFp-p VRX-CM-AC TRX-RISE, TRX-FALL ZRX-DIFF-DC ZRX-COM-DC ZRX-COM-INITIAL-DC ZRX-COM-HIGH-IMP-DC RLRX-DIFF RLRX-CM Jitter Parameters TRX-MAX-JITTER TRX-EYE TRX-EYE-MEDIAN-to-MAX-JITTER PI7C9X7954 Document Number DS40138 Rev 2-2 Description Min Differential input voltage (peak-to-peak) Differential input threshold voltage (peak-to-peak) to assert TxIdleDetect output Receiver common-mode voltage for AC-coupling Rise time / Fall time of RxP, RxN inputs Differential input impedance (DC) Single-ended input impedance Initial input common mode impedance (DC) Powered down input common mode impedance (DC) Receiver Differential Return Lossa Receiver Common Mode Return Lossb 170 1200 mV 65 175 mV 150 mV 160 Ps 120 60 60 Ω Ω Ω Receiver total jitter tolerance Minimum Receiver Eye Width Maximum time between jitter median and max deviation from Typical 0 80 40 5 100 50 50 200k Ω 10 6 dB dB 0.65 0.35 Page 65 of 69 www.diodes.com 0.325 UI UI UI October 2017 © Diodes Incorporated PI7C9X7954 Symbol Description median Min Timing Parameters LRLAT-10 LRLAT-20 TRX-SKEW Receiver data latency for n=10 Receiver data latency for n=20 Receiver data skew between any 2 lanes TBDDly Beacon-Activity on channel to detection of Beacond TRX-IDLE_ENTER Delay from detection of Electrical Idle condition on the channel to assertion of TxIdleDetect output TRX-IDLE_EXIT Delay from detection of L0s to L0 transition to deassertion of TxIdleDetect output a. Over a frequency range of 50 MHz to 1.25 GHz. b. Over a frequency range of 50 MHz to 1.25 GHz. c. Assuming synchronized bit streams at the respective receiver inputs. d. This is a function of beacon frequency PI7C9X7954 Document Number DS40138 Rev 2-2 Typical Max. Unit 29 60 1c bits bits bits 200 us 10 20 ns 5 10 ns 28 49 0 Page 66 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 10. CLOCK SCHEME The PI7C9X7954 requires 100MHz differential clock inputs through CLKINP and CLKINN Pins as shown in the following table. Table 10-1 Input Clock Requirements Symbol Description Min ClkInFREQ Reference input clock range ClkInDC Duty cycle of input clock 40 TR, TF Rise/Fall time of input clock VSW Differential input voltage swing (zero-to-peak) 0.4 a. RCUI (Reference Clock Unit Interval) refers to the reference clock period PI7C9X7954 Document Number DS40138 Rev 2-2 Page 67 of 69 www.diodes.com Typical 100 50 - Max. 60 0.2 0.8 Unit MHz % RCUIa V October 2017 © Diodes Incorporated PI7C9X7954 11. PACKAGE INFORMATION The package of PI7C9X7954 is a 14mm x 14mm LQFP (128 Pin) package. The following are the package information and mechanical dimension: Figure 11-1 Package Outline Drawing PI7C9X7954 Document Number DS40138 Rev 2-2 Page 68 of 69 www.diodes.com October 2017 © Diodes Incorporated PI7C9X7954 12. Order Information Part Number PI7C9X7954 FDEX Temperature Range -40oC to 85oC (Industrial Temperature) PI 7C 9X7954 Package 128-pin LQFP 14mm x 14mm Pb-Free & Green Yes FD E X Tape & Reel Pb-Free and Green Package Code Blank=Standard =Revision Device Type Device Number Family Pericom PI7C9X7954 Document Number DS40138 Rev 2-2 Page 69 of 69 www.diodes.com October 2017 © Diodes Incorporated