2SJ364

2SJ364

  • 厂商:

    PANASONIC

  • 封装:

  • 描述:

    2SJ364 - Silicon P-Channel Junction FET - Panasonic Semiconductor

  • 详情介绍
  • 数据手册
  • 价格&库存
2SJ364 数据手册
Silicon Junction FETs (Small Signal) 2SJ364 Silicon P-Channel Junction FET For analog switch unit: mm 2.1±0.1 s Features 0.65 0.425 1.25±0.1 0.425 1 2.0±0.2 1.3±0.1 0.65 3 2 s Absolute Maximum Ratings (Ta = 25°C) 0.2 Parameter Gate to Drain voltage Drain current Gate current Allowable power dissipation Channel temperature Storage temperature Symbol VGDS ID IG PD Tch Tstg Ratings 65 −20 −10 150 150 −55 to +150 Unit V mA mA mW °C °C 1: Source 2: Drain 3: Gate 0.9±0.1 0.7±0.1 0 to 0.1 0.2±0.1 EIAJ: SC-70 S-Mini Type Package (3-pin) Marking Symbol (Example): 4M s Electrical Characteristics (Ta = 25°C) Parameter Drain to Source cut-off current Gate to Source leakage current Gate to Drain voltage Gate to Source cut-off voltage Forward transfer admittance Drain to Source ON-resistance Symbol IDSS* IGSS VGDS VGSC | Yfs | RDS(on) Conditions VDS = −10V, VGS = 0 VGS = 30V, VDS = 0 IG = 10µA, VDS = 0 VDS = −10V, ID = −10µA VDS = −10V, ID = −1mA, f = 1kHz VDS = −10mV, VGS = 0 VDS = −10V, VGS = 0, f = 1MHz 1.8 65 1.5 2.5 300 12 4 3.5 min − 0.2 typ max −6 10 Unit mA nA V V mS Ω pF pF Input capacitance (Common Source) Ciss Reverse transfer capacitance (Common Source) Crss * IDSS rank classification Runk IDSS (mA) O − 0.2 to −1 4MO P − 0.6 to −1.5 4MP Q −1 to −3 4MQ R −2.5 to −6 4MR Marking Symbol 0.15–0.05 +0.1 0.3–0 q Low ON-resistance q Low-noise characteristics +0.1 1 Silicon Junction FETs (Small Signal) PD  Ta 200 –4.0 Ta=25˚C 175 –3.5 –2.5 2SJ364 ID  VDS –3.0 VDS=–10V ID  VGS Allowable power dissipation PD (mW) Drain current ID (mA) Drain current ID (mA) 150 125 100 75 50 25 0 0 20 40 60 80 100 120 140 160 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0 –2 –4 –6 –8 –10 –12 VGS=0V –2.0 –1.5 0.2V 0.4V 0.6V 0.8V –1.0 – 0.5 0 0 1 2 3 4 5 Ambient temperature Ta (˚C) Drain to source voltage VDS (V) Gate to source voltage VGS (V) | Yfs |  VGS 4.0 16 VDS=–10V f=1kHz Ta=25˚C | Yfs |  ID Input capacitance (Common source), Output capacitance (Common source), Reverse transfer capacitance (Common source) Ciss,Coss,Crss (pF) 24 Ciss, Coss, Crss  VDS VDS=–10V f=1kHz Ta=25˚C f=1MHz VGS=0 Ta=25˚C Forward transfer admittance |Yfs| (mS) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.0 Forward transfer admittance |Yfs| (mS) 14 12 10 8 6 4 2 0 20 16 Ciss 12 8 4 Coss Crss 0 –1 –3 –10 –30 –100 1.5 1.0 0.5 0 0 –2 –4 –6 –8 –10 –12 Gate to source voltage VGS (V) Drain current ID (mA) Drain to source voltage VDS (V) 2
2SJ364
物料型号: - Panasonic 2SJ364

器件简介: - 该器件是一款适用于模拟开关的P沟道结型场效应管(Silicon P-Channel Junction FET),具有低导通电阻和低噪声特性。

引脚分配: - 1: 源极(Source) - 2: 漏极(Drain) - 3: 栅极(Gate) - 封装类型为S-Mini Type Package(3-pin)

参数特性: - 栅极到漏极电压(VGDS):65V - 漏极电流(Ip):-20mA - 栅极电流(IG):-10mA - 允许耗散功率(PD):150mW - 沟道温度(Tch):150°C - 存储温度(Tslg):-55至+150°C

功能详解: - 该器件在截止状态下,漏源之间的电流(Ipss)最小值为0.2mA,最大值为-6mA。 - 栅源之间的漏电流(IGss)在30V时最大值为10nA。 - 栅漏电压(VGDS)在10mA时为65V。 - 栅源截止电压(VGsc)在-10V时范围为1.5V至3.5V。 - 正向传输导纳(Y)在1kHz时范围为1.8至2.5mS。 - 漏源导通电阻(RDS(on))在-10mV时范围为300Ω。 - 输入电容(Ciss)在1MHz时范围为12pF。 - 反向传输电容(Crss)为4pF。

应用信息: - 适用于模拟开关。

封装信息: - 采用S-Mini Type Package(3-pin)封装,标记符号示例为4M。
2SJ364 价格&库存

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