AN5195K-C

ICs for TV AN5195K-C Single chip IC for PAL/NTSC color TV (built-in I2C bus interface) Unit: mm s Overview The AN5195K-C is an IC in which all of the PAL/NTSC system color television signal processing circuits are integrated on one chip. The rationalization of set production line can be realized by the incorporation of I2C bus interface. 58.4±0.3 64 33 17.0±0.2 1 32 3.85±0.2 0.7 min. 5.2 max. s Features • Built-in video IF circuit, sound IF circuit, video signal processing circuit, color signal processing circuit, and sync. signal processing circuit • Rationalization of set production line can be realized by the incorporation of I2C bus interface • Can be applied to PAL/NTSC/AV-NTSC/MNTSC system • Package: 64-SDIP, supply voltage: 5 V, 9 V (3.3) 19.05 0.25– 0.05 0° to 15° +0.1 (1.641) Seating plane 1.778 (1.0) 0.5–0.05 +0.1 SDIP064-P-0750B s Applications • TV, TV-video combination 1 AN5195K-C s Block Diagram SIF3 in/ sharpness 33 Deemphasis Pre-amp. Limiter SIF detect VCO ICs for TV ASW *1-bit Ext. audio in 34 SIF2 in 35 36 SIF1 in 37 IF AGC filter 38 Int. video1 in 39 SIF APC filter 40 Int. video2 in 41 VIF det. out 42 VIF APC1 filter VIF VCO 43 Video out Y-in 44 45 Hor. sync. sep. SIF SW *2-bit 32 31 30 29 Decoupling Ext. video in AFT out De-emphasis Audio out RF AGC GND(VIF/SIF) VIF2 in Video SW *1-bit LPF *1-bit 28 Level adjust *3-bit *6-bit 27 RF AGC IF amp. 26 25 24 APC1 *9-bit AFT IF AGC VCO VIF1 in 23 V (VIF/SIF) CC3 22 21 20 19 SCL SDA ACL GND (RGB/DAC) Hor. lock det. B-out G-out VIF detect SW out *6-bit Phase shift *7-bit Sharpness Y contrast Sync. in 46 Ver. sync. sep. Black expansion DAC out I C bus interface *Cut off 8-bit CV clamp Y clamp 2 CC2 HVBLK System SW *1-bit *Drive 7-bit *Cut off 8-bit VCC3(VCJ) 47 48 C in/black expansion 49 GND(VCJ) 50 FBP in 51 V AFC2 filter 52 Hor. lock DET *Drive 7-bit *Cut off 8-bit 18 17 16 15 HBLK LPF BGP G B R-out 14 V (9 V) CC1 13 B-in G-in R-in YS in BL det. Chroma VCO (3.58 MHz) Chroma VCO (4.43 MHz) 12 11 10 Hor. reg. SCP *3-bit AFC2 R ACC amp. Shut down Ver. count down APC Tint H-out Ver. clamp V-out SECAM interface −(B−Y) out −(R−Y) out S.C.P *6-bit 56 57 50 Hz /60 Hz detect ACC det. X-ray protect 55 Hor. count down Hor. VCO 54 HVCO (*6-bit) AFC1 filter AFC1 53 1H FF Contrast 9 8 7 6 *2-bit (50 Hz /60 Hz) Ver. out 2-bit 59 R−Y B−Y demod demod +/− CW generate Killer ident 58 Chroma VCO 1-bit 60 61 Saturation *6-bit PN/S SW 62 2 G−Y −(R−Y) in 64 RGB SW −(B−Y) in 63 Matrix APC filter 5 Killer out,50 Hz/60 Hz out SECAM det. out 4 Killer filter 3 (B) clamp filter 2 (G) clamp filter 1 (R) clamp filter Brightness B clamp G clamp R clamp Killer * 7-bit 50 Hz/60 Hz SECAM det SW *1-bit ICs for TV s Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (R) clamp (G) clamp (B) clamp Killer filter Killer out, 50 Hz/60 Hz out, SECAM det. out Chroma APC filter Chroma VCO (4.43 MHz) Chroma VCO (3.58 MHz) Black level det. YS input External R input External G input External B input VCC1 R output G output B output Hor. lock detect GND ACL SDA SCL VCC3-1 (VIF/SIF) VIF1 input VIF2 input GND (VIF/SIF) RF AGC output Audio output De-emphasis AFT output External video input DC decoupling filter (RGB/I2C/DAC) Description Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AN5195K-C Description SIF3 input/ sharpness External audio input SIF2 input SIF1 input IF AGC filter Internal video1 input SIF APC filter Internal video2 input VIF detect output VIF APC1 filter VIF VCO (fP/2) Video output Y input HV sync. input VCC3-2 (chroma/jungle/DAC) Chroma input/black expansion start GND (video/chroma/jungle) FBP input VCC2 (hor. stability supply) AFC2 filter AFC1 filter Hor. VCO (32 fH) X-ray protection input Hor. pulse output Ver. sync. clamp Ver. pulse output SECAM interface −(B−Y) output −(R−Y) output Sandcastle pulse output −(B−Y) input −(R−Y) input 3 AN5195K-C s Absolute Maximum Ratings Parameter Supply voltage VCC Symbol VCC1(14) VCC3(23, 47) Supply current ICC I14 I23+47 I51 Power dissipation*2 temperature*1 *1 ICs for TV Rating 10.5 6.0 67 126 27 1,480 −20 to + 70 −55 to + 150 Unit V mA PD Topr Tstg mW °C °C Operating ambient Storage temperature Note) *1 : Except fot the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2 : The power dissipation shown is the value for Ta = 70°C. s Recommended Operating Range Parameter Supply voltage Symbol VCC1 VCC3 Supply current I51 Range 8.1 to 9.9 4.5 to 5.5 10 to 25 mA Unit V s Electrical Characteristics at Ta = 25°C Parameter Power supply Supply current 1 Supply current 2 Supply current 3 Stabilized power supply voltage Stabilized power supply current Stabilized power supply input resistance VIF circuit I14 I23 I47 V51 I51 R51 Current at V14 = 9 V Current at V23 = 5 V Current at V47 = 5 V Voltage at I51 = 15 mA Current at V51 = 5 V DC measurement, gradient at I51 = 10 mA and 25 mA Modulation m = 87.5%, data 0B = 44 0B = 74 0B = 04 Frequency to become −3 dB for 1 MHz Sync. peak voltage at V[p-0] measurement High band side pull-in range (difference from fP = 38.9 MHz) Low band side pull-in range (difference from fP = 38.9 MHz) Delay point (input to become V27 = approx. 6.5 V) at data 0A = 00 to 3F 39 7 49 5.8 2 1 48 10 63 6.5 5 5 57 13 77 7.2 7 10 mA mA mA V mA Ω Symbol Conditions Min Typ Max Unit Typical input: fP = 38.9 MHz, VIN = 90 dBµ VPO VPOmax VPOmin fPC VSP fPPH fPPL ∆VRFDP 1.7 1.9 1.1 5.5 1.6 1.0  75 2.1 2.6 1.6 8 2.0 2.0 −2.0  2.5 3.3 2.1 12 2.4  −1.0 95 V[p-p] V[p-p] V[p-p] MHz V MHz MHz dBµ Video detection output (typ.) Video detection output (max.) Video detection output (min.) Video detection output f characteristics Sync. peak value voltage APC pull-in range (H) APC pull-in range (L) RF AGC delay point adjusting range 4 ICs for TV s Electrical Characteristics at Ta = 25°C (continued) Parameter VIF circuit (continued) Symbol ∆fP Conditions Min −1.2 Typ AN5195K-C Max Unit Typical input: fP = 38.9 MHz, VIN = 90 dBµ Dispersion without input VIN, V37 (IF AGC) = 0 V(measurement of difference from 38.9 MHz) Maximum current IC can sink when pin 27 is low ∆f = ±25 kHz V30 without input VIN V30 at f = fP −500 kHz V30 at f = fP +500 kHz DC measurement IO = − 0.4 mA to −1.0 mA ∆f = ±50 kHz 0B−D3 = 0 ∆f = ±50 kHz 0B−D3 = 0 ∆f = ±50 kHz 0B−D3 = 0 Ratio between fS = 5.5 MHz and 6.0 MHz, and 6.5 MHz 0 1.2 MHz VCO free-running frequency RF AGC maximum sink current IRFmax RF AGC minimum sink current AFT discrimination sensitivity AFT center voltage AFT maximum output voltage AFT minimum output voltage Detection output resistance IRFmin µAFT VAFT VAFTmax VAFTmin RO41 VSOP36 VSOP35 VSOP33 RSN/P 1.5 3.0 0 57 4.5 8.1 0.8 120  50 75 5.0 8.7 1.0 170 mA µA mV/kHz V V V Ω Leakage current of IC, when pin 27 is high −50 40 4.0 7.8 0.3 70 SIF circuit Typical input: fS = 6.0 MHz, fM = 400 Hz, VIN = 90 dBµ Audio detection output (PAL, SIF1) Audio detection output (PAL, SIF2) Audio detection output (PAL,SIF3) Audio detection output NTSC/PAL 0.90 0.90 0.90 1.15 1.15 1.15 − 0.5 0 5.0 4.0 6.0 5.0 6.5 5.5 7.0 6.0 40 60 1.40 1.40 1.40 1.5 3  4.2  5.2  5.7  6.2 48 72 V[rms] V[rms] V[rms] dB dB MHz MHz MHz MHz MHz MHz MHz MHz kΩ kΩ ∆f = ±25 kHz, 0B−D3 = 1, ratio to PAL (VSOP36) −2.5 −3 4.8  5.8  6.3  6.8  32 48 Audio detection output linearity ∆VSOP SIF pull-in range NTSC (4.5 MHz) SIF pull-in range NTSC (4.5 MHz) SIF pull-in range PAL (5.5 MHz) SIF pull-in range PAL (5.5 MHz) SIF pull-in range PAL (6.0 MHz) SIF pull-in range PAL (6.0 MHz) SIF pull-in range PAL (6.5 MHz) SIF pull-in range PAL (6.5 MHz) De-emphasis pin output resistance (PAL) De-emphasis pin output resistance (NTSC) fSNH Pull-in range of high frequency side (4.5 MHz) fSNL Pull-in range of low frequency side (4.5 MHz) fSPH Pull-in range of high frequency side (5.5 MHz) fSPL Pull-in range of low frequency side (5.5 MHz) fSPH Pull-in range of high frequency side (6.0 MHz) fSPL Pull-in range of low frequency side (6.0 MHz) fSPH Pull-in range of high frequency side (6.5 MHz) fSPL Pull-in range of low frequency side (6.5 MHz) R29P R29N Impedance of pin 29 at PAL Impedance of pin 29 at NTSC 5 AN5195K-C s Electrical Characteristics at Ta = 25°C (continued) Parameter AV SW circuit Video SW voltage gain Video SW f characteristics Video SW external input pin voltage Video SW external output DC voltage Video SW external input resistance Video SW output resistance GVSW fVSW V31 V44E RI31 RO44 f = 1MHz, VIN = V[p-p] Frequency to become −3 dB from f = 1 MHz, VIN = 0.714 V[0-p] DC measurement DC measurement, 03−D7 = 1, 0B−D7 = 1 DC measurement DC measurement, IO = − 0.6 mA to −1.0 mA DC measurement, IIN = −1.0 mA DC measurement Data 03−D7 = 1, 0B−D7 = 1 (external input) f = 400 Hz, VIN = 1 V[p-p] DC measurement DC measurement DC measurement DC measurement Data 03 = 20 (typ.) (contrast) Data 03 = 3F (max.) Data 03 = 00 (min.) 5.7 8 1.7 4.2 44 100 1.3 3.7 −1 3.7 3.7 55 200 6.7 10 2.0 4.8 56 140 1.6 4.3 0 4.2 4.2 65 400 Symbol Conditions Min Typ ICs for TV Max Unit 7.7  2.3 5.4 68 180 1.9 4.9 1 4.7 4.7 75 600 dB MHz V V kΩ Ω V V dB V V kΩ Ω Video SW internal clamp pin voltage V38,40 Video SW internal output DC voltage Audio SW voltage gain Audio SW input pin voltage Audio SW output DC voltage Audio SW input resistance Audio SW output resistance Video signal processing circuit Video output (typ.) Video output (max.) Video output (min.) Contrast variable range Video frequency characteristics Picture quality variable range Pedestal level (typ.) Pedestal level variable width Brightness control sensitivity Video input clamp voltage ACL sensitivity Blanking off threshold voltage Blanking level Service SW threshold voltage *1 DC restoration ratio V44I GASW V34 V28 RI34 RO28 Typical input: 0.6 V[p-p] (VWB = 0.42 V[p-p] stair-step), at G-out VYO VYOmax VYOmin 1.9 4.1 0.15 15 5.5 9 2.0 2.0 14 3.2 2.4   90 2.4 5.0 0.50 20 6.0 13 2.5 2.6 20 3.7 3.0 1.0  100 2.9 5.9 1.00 25  17 3.0 3.2 26 4.2 3.6 1.5 0.3 110 V[0-p] V[0-p] V[0-p] dB MHz dB V V mV/ Step V V/V V V % YCmax/min 03 = 3F 03 = 00 fYC Pin 33 = 5 V (sharpness), frequency to become −3 dB from f = 0.2 MHz YSmax/min V33 = 7 V , f = 3.8 MHz V33 = 5 V VPED ∆VPED ∆VBRT VYCLP ACL VYBL VSTH TDC Data 02 = 40 (typ.) (brightness) Difference between data 02 = 00 and 7F Average amount of change at data 02 = 30 and 50 per 1 step Clamp voltage of pin 45 Change of Y-out, when V20 = 3.0 V → 3.5 V DC voltage of blanking pulse Stop voltage of vertical output, when lowering pin 20 (ACL) voltage APL 10% to 90% ∆AC − ∆DC TDC = × 100 ∆AC DC measurement: IC inside sink current Video input clamp current IYCLP 8 13 18 µA Note) *1: Take great care for not to become V20 < 0.9 V at set design so that the pin 20 is combined use for service SW when it is used as the ACL. 6 ICs for TV s Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol ∆VIPL ∆TBL Conditions Min − 0.2 0.9 Typ AN5195K-C Max Unit Video signal processing circuit (continued) Pedestal difference voltage Brightness voltage tracking Typical input: 0.6 V[p-p] (VWB = 0.42 V[p-p] stair-step), at G-out 0 1.0 1.0 1.0 0.2 1.1 1.2 1.1 V Times Times Times/ Times Difference voltage of R,G,B-out pedestal R,G,B-out fluctuation level ratio of data 02 (brightness) = 20 to 60 Video voltage gain relative ratio ∆GYC Video voltage gain tracking ∆TCONT Output ratio of R,B-out against G-out 0.8 Gain ratio of R,G,B-out at data 03 (contrast) = 10 to 30 0.9 Chroma signal processing circuit Color-difference output (typ.) Color-difference output (max.) Color-difference output (min.) Contrast variable range ACC characteristics 1 ACC characteristics 2 NTSC tint center NTSC tint variable range 1 NTSC tint variable range 2 Color-difference output ratio (R) Color-difference output ratio (G) Color-difference output angle (R) Color-difference output angle (G) PAL color killer tolerance NTSC color killer tolerance APC pull-in range (H) APC pull-in range (L) Color killer detection output voltage (color) Color killer detection output voltage (B&W) Demodulation output −(B−Y) Demodulation output −(R−Y) VCO Burst 150 mV[p-p] (PAL), reference is B-out Input: Color bar data 00 = 20 (typ.), 03 = 20 (typ.) Data 00 = 3F, amplitude of one side, 03 = 20 Data 00 = 00, 03 = 20 2.9 2.6  15 0.9 0.8 −7 30 −65 0.46 0.28 78 224 −57 −57 450  4.5 0 555 430 −6 84 3.7 3.3  20 1.0 1.0 0 50 −50 0.56 0.34 90 236 −44 −44 700 −700 5.0 0.1 695 540 0 90 350 4.5  V[p-p] V[0-p] VCOmax VCOmin 100 mV[p-p] 25 1.2 1.2 7 65 −30 0.66 0.40 102 248 −34 −34  −450  0.5 dB Times Times Step deg deg Times Times deg deg dB dB Hz Hz V V CCmax/min 03 = 3F , 00 = 20 03 = 00 ACC1 ACC2 ∆θC ∆θ1 ∆θ2 R/B G/B ∠R ∠G VKILLP VKILLN fCPH fCPL VKC VKBW VDB VDR Burst 150 mV[p-p] → 300 mV[p-p] Burst 150 mV[p-p] → 30 mV[p-p] Difference from data 01 = 20 (tint), when adjusted at tint center Input: Rainbow, data 01 = 3F Input: Rainbow, data 01 = 00 Input: Rainbow for both PAL/NTSC Input: Rainbow for both PAL/NTSC Input: Rainbow for both PAL/NTSC Input: Rainbow for both PAL/NTSC 0 dB = 150 mV[p-p] 0 dB = 150 mV[p-p] For both PAL/NTSC For both PAL/NTSC V5, when chroma input Data 0A−D6 = 0, 0A−D7 = 1, killer out V5, when chroma input Data 0A−D6 = 0, 0A−D7 = 1, killer out Input: Measurement at pin 60 for both color bar PAL/NTSC Input: Measurement at pin 61 for both color bar PAL/NTSC Phase shift of B−Y axis Phase difference from B−Y axis 835 mV[p-p] 650 mV[p-p] 6 96 deg deg Demodulation output angle ∠(B−Y) ∠RDB Demodulation output angle ∠(R−Y) ∠RDR CW output level (4.43 MHz) VCWP AC component, when VCO is set at 4.43 MHz 250 450 mV[p-p] 7 AN5195K-C s Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min  1.31 50 4.5 0.8 4.1 Typ  1.41 100 5.0 1.3 4.6 ICs for TV Max Unit Chroma signal processing circuit (continued) CW output level (3.58 MHz) CW output level period (SECAM) SECAM discrimination current SECAM discrimination output PAL/NTSC DC level SECAM DC level RGB processing circuit Drive adjustment range Cut-off adjustment range YS threshold voltage YS threshold voltage Internal and external pedestal difference voltage External RGB output voltage VCWN TCW ISECAM VSE V59PN V59S GDV VCUTOFF VYSON VYSOFF ∆VPL/IE VERGB Burst 150 mV[p-p] (PAL), reference is B-out 50 1.51 150  1.65 5.1 mV[p-p] ms µA V V V AC component, when VCO is set at 3.58 MHz CW output period at SECAM and PAL Minimum value for taking out current from pin 59 and discriminating as SECAM V5 data, when SECAM signal inputted 0A−D6 = 1, 0A−D7 = 0, SECAM det. out V59 DC level at PAL/NTSC V59 DC level at SECAM AC change amount of R, B-out, when drive adjustment max. and min. DAC data are typical 5 6 2.4   0 0 2.2 1.0 17 10 0.92 7 2.7  0.4 200 200 2.7 1.2 22  1.06 dB V V V mV mV V[p-p] Times dB MHz Times DC change amount of R,G,B-out, 2.1 when cutoff adjustment max. and min. Minimum DC voltage, when YS turns on 1.0 Maximum DC voltage, when YS turns off YS = 5 V Internal-external Input 0.7 V[p-p], contrast 03 = 20 (typ.) Output ratio of external R,G,B-out 03 = 3F 03 = 00 Input 0.2 V[p-p] External 0.7 V[p-p]/internal 0.6 V[p-p] input, contrast 03 = 20 (typ.)  −200 200 1.8 0.8 12 8 0.78 External RGB pedestal difference voltage ∆VEPL External RGB output difference voltage ∆VERGB External RGB contrast variable ECmax/min range External RGB frequency characteristics fRGBC Internal and external RGB output voltage ratio VE/I Synchronizing signal processing circuit Horizontal free-running oscillation frequency Horizontal output pulse duty cycle Horizontal pull-in range PAL vertical free-running oscillation frequency NTSC vertical free-running oscillation frequency Vertical output pulse width PAL vertical pull-in range NTSC vertical pull-in range Horizontal output voltage (H) Horizontal output voltage (L) 8 fHO τHO fHP fVO-P fVO-N τVO fVP-P fVP-N V56H V56L Without sync. signal input Upward going pulse duty cycle Difference from fH = 15.625 kHz Data 01−D7 = 1, 02−D7 = 0 Forced 50 Hz mode, no sync. signal input Data 01−D7 = 1, 02−D7 = 1 Forced 60 Hz mode, no sync. signal input For both PAL/NTSC fH = 15.625 kHz, forced 50 Hz mode fH = 15.75 kHz, forced 60 Hz mode High-level DC voltage Low-level DC voltage 15.33 15.63 15.93 31 ±500 48 58 9 46 56 2.9  37 ±650 50 60 10   3.2  43  52 62 11 54 64 3.5 0.3 kHz % Hz Hz Hz 1/fH Hz Hz V V ICs for TV s Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ AN5195K-C Max Unit Synchronizing signal processing circuit (continued) Vertical output voltage (H) Vertical output voltage (L) Picture center variable range Overvoltage protective operation voltage Vertical frequency discrimination 50 Vertical frequency discrimination 60 Sync. signal clamp voltage Horizontal output start voltage V58H V58L ∆THC VXRAY f50 f60 V46 VfHS High-level DC voltage Low-level DC voltage Change amount of phase difference of H sync. and H-out of data 0B = 40 to 47 Minimum voltage of pin 55 at which H-out stops to appear Vertical frequency to become V5 = low (< 0.5 V) Vertical frequency to become V5 = high (> 4.5 V) V46 clamp voltage Minimum V50 to become f0 >10 kHz, when horizontal oscillation output is more than 1 V[p-p] 3.9  2.6 0.60 47 57 1.0 3.4 4.2  3.2 0.68   1.3 4.2 4.5 0.3 4.4 0.76 55 63 1.6 5.0 V V µs V Hz Hz V V I2C interface Sink current at ACK SCL, SDA signal input high-level IACK VIHI Maximum value of pin 21 sink current when ACK 1.8 3.1   2.5    5.0  0.9 100 mA V V kbit/s SCL, SDA signal input low-level VILO Maximum frequency allowable to input • Design reference data fImax Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter VIF circuit Symbol Conditions Input level to become VPO1 = −3 dB Input level to become VPO1 = +1 dB Min   50     0.5  46 2 Typ Max    5 5   3.0 200  5 Unit dBµ dBµ dB % deg IRE IRE dB kHz dB V/ Step 9 Typical input: fP = 38.9 MHz, VIN = 90 dBµ VPS VPmax SNP DGP DPP ∆VBN ∆VBNC GRF ∆fPD IM SRF Deference from sync. peak value Deference from sync. peak value Input level difference to become V27 = 1 V → 7 V Frequency drift from 5 seconds to 5 mins. after SW on VfC −VfP = −2 dB, VfC −VfP = −12 dB Average amount of change of output voltage V27 at data 1 step 45 110    −45 45     Input sensitivity Maximum allowable input SN ratio Differential gain Differential phase Black noise detection level Black noise clamp level RF AGC operation sensitivity VCO switch on drift Intermodulation RF AGC adjustment sensitivity AN5195K-C s Electrical Characteristics at Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. ICs for TV Parameter VIF circuit (continued) Symbol Conditions Min Typ    1.2 4.0     300 300 1.0 Max Unit Typical input: fP = 38.9 MHz, VIN = 90 dBµ SAFT ∆VP/V ∆VP/T RI24,25 CI24,25 VSIF βP fVCO Average amount of change of output voltage V30 at data 1 step VCC = ±10% Ta = −20°C to +70°C f = 38.9 MHz f = 38.9 MHz fS = 38.9 MHz−6.0 MHz, P/S = 20 dB ∆V42 = ± 0.1 V Free-running frequency change width at data 0C = 00 to 7F Ta = −20°C to +70°C Ta = −20°C to +70°C Ta = −20°C to +70°C, input frequency at which AFT output voltage becomes 4.5 V Output DC voltage at AV SW external mode Input level to become VSOP = −3 dB AM = 30% ∆f = ±50 kHz ∆f = ±50 kHz, fM = 400 Hz, on/off VCC = ±10% Ta = −20°C to +70°C DC measurement DC measurement f = 1 MHz, VIN = 1 V[p-p] Internal → Internal f = 1 MHz, VIN = 1 V[p-p] Internal → External, External → Internal fS = 6.5 MHz, fM = 400 Hz, VIN = 1 V[p-p] fS = 6.5 MHz, fM = 1.0 kHz, VIN = 1 V[p-p] 0.1     90 2.0 3    0.5 0.3 ±15 ±10   110 3.5 5 5   1.8 V/ Step % % kΩ pF dBµ kHz/mV MHz dB kHz kHz V AFT offset adjustment sensitivity Video detection output fluctuation with VCC Video detection outputtemperature characteristics Input resistance (pin 24, pin 25) Input capacitance (pin24, pin 25) Sound IF output level VCO control sensitivity VCO control range RF AGC delay-point temperature ∆VDP/T characteristics VCO free-running frequency temperature characteristics AFT center frequency temperature characteristics External mode output DC voltage SIF circuit ∆fP/T ∆fAFT/T V41EXT Typical input: fS = 6.0 MHz, fM = 400 Hz, VIN = 90 dBµ VLIM AMR THD SNA ∆VS/T RI35 RI36 CTVII CTVEI CTAII  55  55              30 30    50  1.0  ±10 ±10   −55 −55 −60 dBµ dB % dB % % kΩ kΩ Input limiting level AM rejection ratio Total harmonic distortion SN ratio Audio output with VCC fluctuation ∆VS/V Audio output temperature characteristics SIF input resistance SIF input resistance AV SW circuit Video SW cross-talk (Internal → Internal ) Video SW cross-talk (External → Internal) Audio SW cross-talk (Internal → Internal) dB dB dB 10 ICs for TV s Electrical Characteristics at Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. AN5195K-C Parameter AV SW circuit (continued) SIF SW cross-talk (External → Internal) Symbol Conditions fS = 6.5 MHz, fM = 400 Hz, VIN = 1 V[p-p] Inside f = 400 Hz, VIN = 1 V[p-p] Min  Typ  Max −60 Unit CTAEI dB Video signal processing circuit Black level extension 1 Black level extension 2 Black level extension 3 Typical input: 0.6 V[p-p] (VBW = 0.42 V[0-p] stair-step) at G-out VBL1 VBL2 VBL3 Input: Total black, difference between the −100 voltage at pin 9 = 9 V and open (with RC filter) Input: Total black, difference between the voltage at pin 9 = 3 V and 9 V Input: approx. 20IRE, difference between the voltage at pin 9 = open and 9 V, 03 (contrast) = 3F (max.) Y-out output level difference, when sharpness max. and min. Pedestal level DC difference, when sharpness max. and min. 03 (contrast) = 20 (typ.) 03 (contrast) = 3F (max.) Start point at V48 = 4.5 V VCC1= 9 V (allowance: ±10%) Ta = −20°C to +70°C V20 at which output amplitude becomes 90% when ACL pin (V20) is dereased from 5 V 400 100 0 700 300 100 1 000 500 mV mV mV Contrast variation with sharpness Brightness variation with sharpness Input dynamic range Y signal SN ratio Black level extension start point ∆VCS ∆VBS VImax SNY VBLS ∆VY/T VACL −300 −250  53 37   3.4 0 0   42   3.7 300 250 1.6  47 ±15 ±10 4.0 mV mV V[p-p] dB IRE % % V Video output with VCC fluctuation ∆VY/V Video output-temperature characteristics ACL start point Color signal processing circuit Burst 150 mV[p-p] (PAL), reference is B-out 2 fSC level of pin 60 and pin 61 2 fSC level of pin 15, pin 16, and pin 17 Difference from f = 4.433619 MHz Difference from f = 3.579545 MHz VCC1 = 9 V (allowance: ±10%), VCC3 = 5 V (allowance: ±10%) Tint shift, when ∆fC = −300 Hz to +300 Hz change Tint shift, when ∆fC = −300 Hz to +300 Hz change Output amplitude ratio between PAL and NTSC Pin 61: Output amplitude difference per 1H for − (R−Y) pin Band to become −3 dB   −300 −300 −300   0.7  1.0        1.0   30 50 300 300 300 5 5 1.3 50  mV mV Hz Hz Hz deg/ 100 Hz deg/ 100 Hz Times mV MHz 11 Demodulation output residual carrier VCAR1 Color difference output residual carrier VCAR2 VCO free-running frequency (PAL) VCO free-running frequency (NTSC) fCO fluctuation with VCC Static phase error (PAL) Static phase error (NTSC) PAL/NTSC Line crawling Color difference output bandwidth fCP fCN ∆fC/VCC ∆θP ∆θN RP/N ∆VPAL fCC AN5195K-C s Electrical Characteristics at Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. ICs for TV Parameter Symbol ∆VC/V ∆VC/T RO60,61PN RO60,61S ∆VCBW RC/Y Conditions VCC1 = 9 V (allowance: ±10%), VCC3 = 5 V (allowance: ±10%) Ta= −20°C to +70°C DC measurement DC measurement Pedestal level DC difference, when burst signal with or without Color bar input, B-out Contrast typ., color data 00 = 30 Min   390 100 −60 0.9 Typ   480  0 1.2 Max ±15 ±15 570  60 1.5 Unit Color signal processing circuit (continued) Color-difference output fluctuation with VCC Color-difference output temperature characteristics PAL/NTSC output impedance SECAM output impedance Color/B&W DC difference voltage (C−Y)/Y RGB processing circuit YS changeover speed fYS Burst 150 mV[p-p] (PAL), reference is B-out % % Ω kΩ mV V[0-p]/ V[0-p] fYS, when YS input is 3 V[0-p], output level −3 dB Contrast max., data 03 = 3F Leakage, when f = 1 MHz, 1 V[p-p], YS = 5 V 7 1.0       −50 MHz V[p-p] dB External RGB input dynamic range VDEXT Internal/external crosstalk CTRGB Synchronizing signal processing circuit Lock detection output voltage Lock detection charge and discharge current EBP (RGB) slice level EBP (AFC2) slice level Horizontal AFC µ Horizontal VCO β Burst gate pulse position PAL burst gate pulse width NTSC burst gate pulse width Burst gate pulse output voltage VLD ILD VFBP VFBPH µH βH PBGP WBGPP WBGPN VBGP V18, when horizontal AFC lock DC measurement Minimum voltage of pin 50, when blanking is applied to RGB output Minimum voltage of pin 50 at which AFC2 operates DC measurement β curve gradient near f = 15.75 kHz For both PAL/NTSC, delay from H. sync. rise 5.7 ±0.6 0.4 1.5 30 1.4 0.2 3.4 2.5 6.3 ±0.8 0.75 1.9 37 1.9 0.4 4.0 3.0 4.7 2.4 2.4 1.41 1.11  6.9 ±1.1 1.1 2.3 44 2.4 0.6 4.6 3.5 4.9 2.7 2.7 1.51 1.21 19 V mA V V µA/µs Hz/mV µs µs µs V V V ms ms µs DC voltage of pin 62 in BGP period DC voltage in H-blanking pulse period of pin 62 4.5 2.1 H blanking pulse output voltage VHBLK V blanking pulse output voltage VVBLK PAL V blanking pulse width NTSC blanking pulse width FBP allowable range WVP WVN TFBP DC voltage in V-blanking pulse period 2.1 of pin 62 Pulse width at f = 15.625 kHz Pulse width at f = 15.75 kHz Time from H-out rise to FBP center 1.31 1.01 12 12 ICs for TV s Electrical Characteristics at Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. AN5195K-C Parameter Symbol Conditions Min Typ              Max Unit Synchronizing signal processing circuit (continued) FBP max. allowable input voltage VAFBP I2C Interface tBUF tSU,STA tHD,STA tLOW tHIGH tr tf tSU, DAT tHD, DAT tSU, ACK tHD, ACK tSU,STO L3,6,7 L8 L8-80 ∆Step 1LSB = {data (max.) − data (00)}/ 7, 63, 127 1LSB = {data (FF) − data (00)}/255 (except 7F → 80) LSB = {data (FF) − data (00)}/255 (7F → 80) Overlap of AFT 8-bit 2-stage changeover 4.0 4.0 4.0 4.0 4.0   0.25 0  0 4.0      1.0 0.35   3.5   µs µs µs µs µs µs µs µs µs µs µs µs 2.5 5.0 V Bus free before start Start condition set-up time Start condition hold time Low period SCL, SDA High period SCL Rise time SCL, SDA Fall time SCL, SDA Data set-up time (write) Data hold time (write) Acknowledge set-up time Acknowledge hold time Stop condition set-up time DAC 3, 6, 7-bit DAC DNLE 8-bit DAC DNLE 8-bit DAC DNLE 80 AFT DAC overlap 0.1 0.1 0.1 27 1.0 1.0 1.0 32 1.9 1.9 2.9 37 LSB Step LSB Step LSB Step Step • Typical conditions when testing 1. Input signal 1) VIF: fP = 38.9 MHz, VIN = 90 dBµ Video modulation : modulated signal is 10-staircase. Modulation m = 87.5% VIN = 90 dBµ, pin 25 input level approx. 84 dBµ 2) SIF: fS = 6.0 MHz, VIN = 90 dBµ, modulated signal fM = 400 MHz, deviation: PAL±50 kHz, NTSC±25 kHz 3) Video: 10-stair-step 0.6 V[p-p] (VBW = 0.42 V[0-p]) 4) Chroma: Color bar signal: Burst level 150 mV[p-p] Rainbow signal: Burst level 150 mV[p-p] 5) Sync. signal: 0.6 V[p-p] 13 AN5195K-C s Electrical Characteristics (continued) • Typical conditions when testing (continued) 2. I2C bus conditions: (PAL) Sub Address Data (H) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C SW typical condition PAL mode RF being inputted state (Video1 in, SIF1 in) 20 20 40 20 00 00 00 40 40 01 20 44 C0 DAC typical condition Color Tint Brightness Contrast Cut-off R Cut-off G Cut-off B Drive R, B Video output Picture center position AFT RF AGC VIF VCO Center Center Center Center Minimum Minimum Minimum Center Center Center Center Center Center ICs for TV s Terminal Equivalent Circuits Pin No. 1 2 3 C 9V (VCC1) 300 Ω Pins 1,2,3 300 Ω 0.01 µF Equivalent circuit Description Pin 1: Primary color signal clamp pin (R): Pin 3: Primary color signal clamp pin (B): • Clamp pulse uses internal clamp pulse (BGP) DC (V) DC Pin 2: Primary color signal clamp pin (G): approx. 7 V BGP 150 µA Brightness control 4 5V (VCC3) 3.3 V Killer det. circuit 1V 137 kΩ 4 0.47 µF 270 Ω 2.5 V 1.0 MΩ Killer filter pin: • Filter pin for killer detection circuit (operates for BGP period) • Killer turns on (without color output) at 2.8 V or less DC approx. 3.3 V BGP 9V 2.8 V 100 µA 14 ICs for TV s Terminal Equivalent Circuits (continued) Pin No. 5 Equivalent circuit VCC for microcomputer (5 V) 33 kΩ To microcomputer 0.47 µF 5 Floating resistor 175 Ω 40 µA 10 kΩ Off AN5195K-C Description Killer, 50 Hz/60 Hz and SECAM det. output pin: • Output selecting by SW (I2C bus) • Connect 33 kΩ load resistor of pin 5 to microcomputer VCC DC (V) DC low-level 0.2 V high-level 5V On 6 5V (VCC3) 3.3 V APC det. circuit 1V 0.047 µF 6 40 2.2 µF kΩ SW R 7.5 kΩ 2.5 V Pin for APC filter: • Filter pin for APC detection circuit (operates for BGP period) • Detection sensitivity becomes large when external R → large (Tends to pull-in easily. Tends to be affected by noise) β curve fC DC approx. 2.5 V BGP max. 1 mA VCO circuit 270 Ω V6 • At SECAM, APC circuit is stopped by short circuiting 40 kΩ resistor 7 8 Pin 7: Chroma oscillation pin (4.43 MHz): AC IP2 100 µA IP1 500 µA IN2 100 µA 100 µA IN1 500 µA Pin 8: Chroma oscillation pin (3.58 MHz): f = fC • Oscillation pin for chroma. Either approx. 0.7 V[p-p] one of 4.43 MHz or 3.58 MHz is DC 2.7 V 4.43 MHz oscillated 7 • Oscillation frequency changeover is C7 performed by 08−D7 bit of I2C bus 12 pF • At 08−D7= 0 IP1 and IP2 turn-on and at 4.43 MHz, DC 2.7V 3.58 MHz 8 oscillation starts At 08−D7=1 C8 IN1 and IN2 turn-on and at 3.58 15 pF MHz, oscillation starts • Pattern design of pin and oscillator element should be as short as possible. 15 AN5195K-C s Terminal Equivalent Circuits (continued) Pin No. 9 Equivalent circuit Description ICs for TV DC (V) −Y 10 kΩ 5.1 V 100 µA 9V (VCC1) 80 µA 75 kΩ 9 To black expansion circuit R 180 kΩ 4.7 µF Black level detection pin: DC Blanking off SW pin approx. 5.1 V • Black level detection filter pin for black extension circuit 5V • Holds the most black Y level except (VCC3) blanking period 80 kΩ • Changes operating sensitivity (area judged as black) of black extension by external R To blanking circuit Responds with small area when R goes large. • To stop the black extension, set pin 9 to VCC (9 V). • Connected to GND, blanking comes off. (also the black extension is off) YS input pin: • Fast blanking pulse input pin for external analog RGB • Turns on at a voltage of 1 V[0-p] or more and off at 0.4 V[0-p] or less. AC (Pulse) 10 50 µA From microcomputer 10 2.7 kΩ 30 kΩ 100 µA 10 kΩ 9V (VCC1) To RGB output circuit 0.7 V 11 12 13 Pins 11,12,13 100 µA 9V (VCC1) Pin 11: External R input pin: Pin 12: External G input pin: Pin 13: External B input pin: • Output changes linearly according to input level. AC To color circuit BGP 200 µA 14  VCC1 (typ. 9 V): • Output part of VIF and SIF circuit • AV SW circuit • Video circuit • RGB circuit 9V (VCC1) DC 9V 15 16 17 C out 100 µA 100 Ω Pin 15: R-out pin: Pin 16: G-out pin: Pin 17: B-out pin: • BLK level: Approx. 0.9 V • Black (pedestal) level: Approx. 2.2 V • Blanking can be released when pin 9 (black level detection pin) is set at 0 V. AC 50 Ω Pins 15 16 17 500 µA 16 ICs for TV s Terminal Equivalent Circuits (continued) Pin No. 18 6.3 V (VCC2) 10 kΩ 800 µA I1 800 µA I2 50 µA 2.8 V 12 kΩ 12 kΩ AN5195K-C Equivalent circuit To chroma circuit 5V (VCC3) Description DC (V) Horizontal sync. detection pin: DC • Phase of horizontal synchronizing at synchronous signal and horizontal output pulse is approx. 6 V detected and outputted. at asynchronous approx. 0.3 V • Pin 18 is low at out of phase. • In asynchronous state, color control becomes min. and chroma output disappears. • Pay attention to impedance when voltage of pin18 is used by microcomputer (ZO ≥ 500 kΩ is required) Pin 56 H-out Pin 46 HV sync. in 18 ZO 0.022 µF 1 MΩ 10 kΩ • HVSYNC period When pin 56 is high: I1 on When pin 56 is low: I2 on GND: • RGB circuit • DAC I2C circuit 9V (VCC1) 19   20 5.9 V 60 kΩ 60 kΩ 6.9 kΩ 2.3 V Contrast control 7.1 kΩ 7.1 kΩ 6.9 kΩ 6.9 kΩ 20 To contrast circuit 2.1 V 3.5 V ACL pin: • Contrast can be reduced when DC voltage of pin 20 is decreased from the outside. • Service SW Note) When pin 20 is used as ACL, set design must be done not to become V20 < 0.9 V so that pin 20 operates also as the service SW. DC approx. 3 V 2.3 V ±1 V 100 µA 100 µA 4.7 µF 100 µA 21 5V (VCC3) 100 kΩ Data 1 kΩ 21 From microcomputer 50 µA 100 kΩ 1.7 V I2C bus data input pin: AC (pulse) ACK 30 kΩ To logic circuit 30 kΩ 17 AN5195K-C s Terminal Equivalent Circuits (continued) Pin No. 22 100 kΩ Clock 1 kΩ 22 From microcomputer 30 kΩ ICs for TV Equivalent circuit 5V (VCC3) 50 µA 100 kΩ 1.7 V Description I2C clock input pin: DC (V) AC (Pulse) To logic circuit 30 kΩ 23 24 25 3.5 V  5V (VCC3) VCC3-1 (typ. 5 V): • For VIF and SIF circuit Pin 24: VIF input pin-1: Pin 25: VIF input pin-2: • Input for VIF amp. and balanced input DC 5V AC f = fP DC level approx. 2.7 V 27 kΩ 1.2 1.2 kΩ kΩ 25 SAW 24 150 µA150 µA 26 27  5V (VCC3) GND: • For VIF and SIF circuit RF AGC output pin: • Open collector output. Can be used at given bias (max. 12 V) DC DC To tuner 27 IF AGC bias RF AGC control bias 40 kΩ 28 9V (VCC1) 270 Ω Audio output pin: 28 AC 0 kHz to 20 kHz 100 µA 400 µA 18 ICs for TV s Terminal Equivalent Circuits (continued) Pin No. 29 Detection output PAL NTSC 120 kΩ 60 kΩ 29 1 200 pF 1.7 kΩ 100 µA AN5195K-C Equivalent circuit 9V (VCC1) Description De-empahsis pin • De-empahsis filter pin for sound detection signal. • External C is the same for PAL and NTSC (internal impedance changes) • PAL: 120 kΩ//60 kΩ × 1 200 pF = 48 µs • NTSC: 60 kΩ × 1 200 pF = 72 µs AFT output pin • Center voltage offset should be adjusted by using bus. • If AFT defeat SW is turned on (09 = 00), V30 comes to a value determined by the value of externally attached resistor dividing. • AFT µ is variable by impedance of externally attached resistor. External video input pin • Input pin for external video signal. DC cut input. • Typical 1 V[p-p] DC (V) AC 0 kHz to 20 kHz 30 1.1 kΩ 1.1 kΩ 9V (VCC1) 9V DC 30 To tuner 1.1 kΩ 40 kΩ 1.1 kΩ max. 350 µΑ 31 50 µA To video SW 3.4 V 30 kΩ 50 kΩ 31 9V (VCC1) Ext. video AC 1 V[p-p] (composite) 10 µF 100 µA DC approx. 2.0 V 9V (VCC1) 32 10 kΩ typ. 4.5 V 3 kΩ 3 kΩ 1.7 kΩ 32 1.7 kΩ 10 µF Decoupling pin • S curve inside IC is wide band but DC feedback is applied so that DC voltage of output signal becomes constant. • DC level (typ. 4.5 V) fS → high: V32 → low DC 20 kΩ 100 µA 13 µA 9V (VCC1) SIF in 33 4.4 V 10 pF30 kΩ 1.8 kΩ 5 V to 7 V 100 µA Sharpness contorol 30 kΩ 200 µA 9V 100 µA To SIF limiter amp. 33 SIF signal input pin • Common use with DC input pin for sharpness control • DC bias is applied from external (DC: 5 V to 7 V for sharpness control) AC+DC AC f = fS 19 AN5195K-C s Terminal Equivalent Circuits (continued) Pin No. 34 50 µA To audio SW 5.4 V ICs for TV Equivalent circuit 9V (VCC1) Description External audio input pin: • Input pin for external audio signal input. DC cut input. • Typical input level should be adjusted to internal sound level. DC (V) AC 0 kHz to 20 kHz 65 kΩ 34 10 µF 150 µA 35 36 SIF in Pins 35 36 30 kΩ 1.8 kΩ 40 kΩ 30 kΩ 200 µA 9V 100 µA To SIF limiter amp. 9V (VCC1) 100 µA 3.7 V SIF signal input pin: • Input pin of SIF1, SIF2 and is biased in inside. AC+DC AC f = fS DC 3.0 V 37 5V (VCC3) To IF amp. 30 µA 0.47 µF 37 IF AGC filter pin: • Pin for IF AGC filter. The current obtained from peak AGC circuit is smoothed by external capacitor. • Since response becomes faster when C → small but sag tends to appear easily. DC approx. 2 V 38 40 50 µA To video SW 3.0 V 30 kΩ Pins 38 40 9V (VCC1) Int. video Internal video input pin: • Input pin for the signal detected in the VIF circuit (internal video signal) • Input with DC cut • Typical input: 1 V[p-p] AC 1 V[p-p] (composite) 10 µF 680 kΩ DC level approx. 1.6 V 9V (VCC1) 39 SIF APC filter pin: • Filter pin of SIF APC circuit DC P.C. VCO (4 MHz to 7 MHz) 8.4 kΩ 800 µA 13 kΩ 2 pF 72 µA 5.6 kΩ 7.5 kΩ To audio SW 39 1 000 pF 200 µA 20 ICs for TV s Terminal Equivalent Circuits (continued) Pin No. 41 75 µA 41 AN5195K-C Equivalent circuit 9V (VCC1) Description VIF detection output pin: • Adjust to 2 V[p-p] by I2C bus (uses upper rank 4-bit of 0 A) DC (V) AC 2 V[p-p] 42 50 µA 1 SW 0 5V (VCC3) 500 Ω 20 kΩ 42 150 Ω 75 µA 0.47 µF 25 µA 3.25 V APC1 filter pin: DC approx. 2.5 V • Filter pin of VIF APC1 circuit • VCO lock detection circuit is incorporated in the IC, and it changes over the time constant of APC filter. • Lock: SW: 0 Unlock: SW: 1 to VCO 43 5V (VCC3) 100 Ω 300 Ω 43 VIF oscillation pin: AC f = fP /2 • Chage the oscillation coil according to VIF frequency. approx. 0.7 V[p-p] 1 DC level • Oscillation frequency is × fP 2 approx. 3.9 V 800 µA 400 µA 100 µA 9V (VCC1) 50 µA 44 Video output pin: • Int. video1, int. video2 or ext. video signal selected by AV SW is outputted. AC 2 V[p-p] 44 400 µA DC level approx. 4.5 V 9V (VCC1) 50 µA 45 47 kΩ 4.3 V 45 10 µA 1.8 kΩ 43 kΩ Video input pin: • Input pin of video signal (possible also for composite video) • Typical input 0.6 V[p-p] • Sync. top is clamped to 3.5 V • Video signal should be inputted with low impedance. AC 0.6 V[p-p] 21 AN5195K-C s Terminal Equivalent Circuits (continued) Pin No. 46 16 kΩ 2 V[p-p] ICs for TV Equivalent circuit 5V (VCC3) 16 kΩ To H sync. sep. To V sync. sep. 1.3 V Description Vertical and horizontal sync. separation input pin: • Sync. top is clamped to 1.3 V. DC (V) AC 2 V[p-p] RH 0.1 µF 46 270 Ω CH 1 200 pF 20 µA 47 48 Chroma signal 1 000 pF 9V 10 kΩ 10 kΩ 48  VCC3-2 (typ. 5 V): • Chroma and Jungle circuit use 5V (VCC3) DC 5V AC+DC Burst typ. 150 mV[p-p] DC typ. 4.5 V Chroma signal input pin: Black extension start point adjustment pin • Pin 48 is chroma signal input pin and black extension start point is adjusted by DC voltage applied externally. 12.5 pF 15 kΩ 2.5 V 50 µA To chroma amp. 9V (VCC1) To black level expansion 100 µA 25 µA 49 50 100 µA  5V (VCC3) 50 µA GND: Video, chroma and jungle circuit use FBP input: • FBP input pin for horizontal blanking and APC circuit • Threshold level HBLK: 0.7 V AFC: 1.9 V • If DC 1.3 V is applied from outside, the state comes to all blanking DC 0V AC FBP 50 µA 100 µA 1.9 V 24 kΩ 0.7 V 50 µA To AFC 60 kΩ To HBLK 40 kΩ 40 kΩ 50 51 I51 typ. 15 mA 47 µF VCC2 51 To hor. OSC Horizontal stabilized power supply pin: • Stabilized power supply for horizontal circuit start up. Zener circuit is included inside. V51 6.3 V DC 6.3 V I51 22 ICs for TV s Terminal Equivalent Circuits (continued) Pin No. 52 2 kΩ 2 kΩ 1.9V AN5195K-C Equivalent circuit 6.3 V (VCC2) To hor. out V52 Description Horizontal AFC2 filter pin: • Pulse phase of FBP and IC inside are compared and capacitor connected to pin 52 is charged or discharged. • Screen center position adjustment is executed by charge or discharge of DC current with DAC. • According to the time from H-out to FBP-in, V52 is changed, and slice level of inside saw-tooth waveform is changed. Horizontal AFC1 filter pin: • Pulse phase of horizontal sync. signal and IC inside are compared and capacitor connected to pin 53 is charged or discharged. • R1, R2, C1 and C2 are lag-lead filters for AFC1 Horizontal β curve DC (V) DC 1.5 V to 3.5 V AFC2 detecter I From DAC (hor. position) 1 kΩ0.022 µF 52 50 µA 3.3 V 1 kΩ max.500 µA 53 4.3 V AFC1 detecter R1 27 kΩ 6.3 V (VCC2) DC typ. 4.3 V 27 kΩ 1.5 V 53 Hor. sync. 22 µF C2 820 Ω R2 200 µA 0.033 µF C1 Hor. OSC fH 1 000 µA V53 6.3 V (VCC2) 22 kΩ 300 Ω 54 100 54 µA 220 pF 200 µA 10 k 10 k Ω Ω 80 µA Horizontal oscillation pin: AC • Oscillation is done at 32 × fH ≅ 503 kHz f = 32 fH by ceramic resonator. (approx. 503 kHz) • Horizontal and vertical pulse are made by count-down circuit of IC inside. 55 4.3 V 20 kΩ 20 kΩ 40 kΩ 6.3 V (VCC2) 55 3V To count down 20 kΩ Overvoltage protection input pin: DC • Input pin for protection circuit Normally 0 V against X-ray caused by overvoltage. • Shut-down is started by inside logic circuit when H-out is low. (breakdown protection of horizontal drive TR) Horizontal pulse output pin: • Pulse duty approx. 36% AC Pulse 56 4.3 V 19 kΩ 50 Ω 56 10 kΩ 40 kΩ 6.3 V (VCC2) 2.8 V 0V Hor. out 23 AN5195K-C s Terminal Equivalent Circuits (continued) Pin No. 57 4.3 V 16 kΩ 4 kΩ 270 Ω 57 200 Ω R1 330 kΩ R2 220 Ω C1 0.33 µF 5V (VCC3) 50 kΩ 4.3 V 0V 58 43 kΩ ICs for TV Equivalent circuit 5V (VCC3) 3 kΩ Description Vertical sync. signal clamp pin: • Peak clamp pin in order to separate vertical sync. signal • Integrating amount of vertical sync. signal itself is determined by time constant of inside but triggering timing is determined by selecting R1 and C1 of external time constant. • Uses with R1 > 200 kΩ • R2 is for emitter current limiting resistor Vertical pulse output pin: • Negative polarity, pulse width 10 H DC (V) AC f = fV 50 kΩ To ver. count down 58 AC Pulse 59 fC 56.2 kΩ 12 kΩ SECAM interface pin: AC+DC • Inpu/output pin for interface with AC SECAM IC 250 mV[p-p] • SECAM mode is made by taking the or 13.7 kΩ 59 curr. of 100 µA or more from pin 59. 0 mV[p-p] 50 k To Ω DC SECAM IC • At SECAM 61.5 kΩ DC4.4 V+AC250 mV[p-p] 4.4 V 200 µA 100 µA • At non-SECAM or SECAM SECAM DC1.1 V+AC250 mV[p-p]: 4.43 MHz 1.1 V detecter or 0 mV[p-p]: 3.58 MHz SECAM 100 µA 100 µA 5V (VCC3) −(B−Y) 60 61 −(R−Y) To 1HDL 9V (VCC1) 50 µA 12 kΩ 60 61 100 µA Pin 60: −(B−Y) output pin: Pin 61: −(R−Y) output pin: • At SECAM, output circuit is off and comes to high impedance. • Output to 1HDL AC −(B−Y) −(R−Y) SECAM 0V SECAM 1.5 kΩ 2.5 kΩ 1.5 kΩ DC level approx. 2.1 V Sandcastle pulse output pin: • Sandcastle pulse is outputted to 1HDL and SECAM IC. AC Pulse 4.7 V 2.4 V 62 37 kΩ VBLK 15 kΩ 5V (VCC3) 42 kΩ 63 kΩ 62 44 kΩ HBLK BGP 24 ICs for TV s Terminal Equivalent Circuits (continued) Pin No. 63 64 Pins 63,64 From 1HDL CCP 200 µA To color circuit 100 µA AN5195K-C Equivalent circuit 9V (VCC1) Description Pin 63: −(B−Y) input pin: Pin 64: −(R−Y) input pin: • Input color difference signal from 1HDL output . • Pedestal level is clamped to 4 V by clamp circuit. DC (V) AC −(B−Y) −(R−Y) DC level 4V s System Application Example AN5195K-C (PAL/NTSC) U/V tuner VIF amp. Video det. SIF amp. FM det. AN5265 Sound output 2SC3942 Video output AN5534 Ver. def. Ver. output AN5071 Band SW Video/chroma signal process CRT PNA4602M IR reciever unit Deflection signal process MN152810 MN1871274 System MCU AN5637 SECAM decoder MN3868 1H CCD delay line 2SC4212 Hor. drv. EEPROM 2SD2522 Hor. output I2C bus 25 AN5195K-C 5.1 kΩ 10 kBΩ Sharpness ICs for TV 10 kBΩ s Application Circuit Example Ext. audio 470 Ω +B (12 V) TU1 33 34 35 36 37 38 39 40 41 42 32 31 30 29 28 27 26 25 24 23 22 21 20 10 µF Decoupling 10 µF 1F BM AFT BL AGC BH BT BU Ext.video 10 µF 10 µF 10 µF 10 µF 10 µF 10 µF 47 µF BPF 4.5 MHz 470 Ω 75 Ω 10 µF Ext. audio in BPF 5.5 470 Ω MHz 6.0 MHz SIF2 in 0.01 µF SIF1 in 0.01 µF AGC 680 kΩ SIF APC Int. V1 0.47 µF BPF 470 Ω 6.5 MHz AFT 150 kΩ 150 kΩ Aidio out 8.2 µH 0.01 µF 0.01 µF 4321 3.6 kΩ 10 kΩ 15 kΩ 15 kΩ 1.8 kΩ 47 µF AN78M09 100 µF 0.01 µF 7.5 kΩ 470 Ω 470 Ω Trap 5.5 H 1 000 pF 130 kΩ Int. V2 680 kΩ 1 200 pF 150 Ω 0.47 µF 39 kΩ RF AGC 6.8 kΩ 21 De-emphasis 1 200 pF 10 µF 3 Band SW 2 4 SW1 1 0.01 µF SIF3 in sharpness 12 H 1 kΩ 910 Ω 10 µF 9V 910 Ω 910 Ω GND (VIF/SIF) 0.01 µF SAW 0.39 µH 1.2 µH 910 Ω 56 Ω Det. out 910 Ω 6.0 H 6.5 H 2 V[p-p] APC1 VOSC 2.2 kΩ 1 kΩ 1 V[p-p] 43 44 45 VCC3 (VIF/SIF) SCL 47 µF 0.01 µF 4.7 Ω Video out 10 µF Y in Sync. in 9V SDA ACL 4.7 µF Hor. lock det. 4.7 Ω 3.58/4.43 On 2 kΩ 100 pF 4.7 µH 270 Ω 1 200 pF (VCJ) 0.1 µF 47 µF 46 AN5195K-C 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B G R VCC3 5V 120 pF 21 150 pF2.7 µH 1.2 kΩ 10 kΩ 3.58 MHz Trap 47 48 49 50 51 52 53 GND (RGB/DAC) 1 MΩ 0.022 µF 1 000 pF C in Trap&DL (340 nsec ±35 nsec) 9V 10 kΩ 30 pF56 µH 10 kΩ 10 kΩ GND (VCJ) FBP in 180 Ω 3.3 kΩ VCC2 47 µF 0.022 µF 1.8 kΩ 1.5 kΩ 1.5 kΩ 1.5 kΩ B 47 µF G R YS 0.47 µF 0.47 µF AFC2 0.033 µF AFC1 X-ray protect. HOSC 10 kBΩ 1 kΩ 47 pF 820 Ω10 µF 220 pF 54 55 56 57 0.47 µF 1 MΩ 10 kΩ 2.2 kΩ 123 33 pF H out 8.2 µH 10 kΩ 680 kΩ Ver. clamp 2.2 µF 220 Ω 4.7 µF BL det. 15 pF U-COM 3.58 MHz 12 pF 58 59 60 61 62 63 64 V out SECAM interface 54321 5V 2.2 µF 4.43 MHz 0.47 µF APC 0.047 µF MN3868(1H DL) 2 3 4 5 (8 V) 1 2 16 15 SECAM 14 13 12 0.01 µF 11 10 9 0.1 µF 0.47 µF 0.022 µF 0.022 µF 0.022 µF Killer G B Clamp filter 1 MΩ Killer out 50 Hz/60 Hz out SECAM det. out 0.1 µF 15 0.01 µF 0.1 µF −(R−Y) −(B−Y) S.C.P out out 1 16 0.1 µF 33 kΩ 1234567 180 kΩ VCC1 (9 V) 1.8 kΩ 12345 47 µF VCC1 = 9 V AN78M05 12 −(R−Y) −(B−Y) 0.022 µF 3 51 Ω 47 µF 14 Video Video out in In 4 5 6 13 12 11 10 9 820 Ω 0.047 µF 0.01 µF 7 8 0.1 µF 82 µH 82 µH 33 pF 33 pF 0.22 µF 8 5V 0.1 µF 7 VCC3 = 5 V 9V 26 R 0.047 µF 6 0.1 µF