AN5491K

ICs for TV AN5491K Synchronous signal and deflection distortion correction processing IC supporting I2C bus for HD, wide television Unit: mm s Overview The AN5491K is a deflection processor IC for synchronous signal processing and screen distortion correction. It synchronizes with the input signal of High-vision, wide television, NTSC, PAL and VGA by the external binary input signal of them so that a multimedia television can be realized easily. s Features • Supports the multiple-point horizontal frequency (15.7 kHz to 62.7 kHz) • Horizontal duty is controllable by external voltage. • Built-in full functions for correction (Horizontal and vertical: 16 items) • Over-current detection, shut-down and hold-down 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 13.7±0.3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 36.8±0.3 0.96±0.25 3.3±0.25 4.76±0.25 3° to 15° 15.3±0.25 +0.1 0.3 –0.05 SDIP042-P-0600A s Applications • High-vision televisions, Wide screen televisions and Projection televisions 1.778 0.9±0.25 0.5±0.1 1 2 Corner level I2L AGC EHT-DC EHT-AC × 32 ×8 ×4 ×2 ×1 V-out VGA GND EW out H-GND DEF GND Phase out Lock det. 37 H-out 38 36 34 27 19 25 26 31 35 33 30 29 28 24 23 22 32 Lock det. fH switch input BOW V-S Upper Lower Corner correction V-LIN Trapezoid crrection Phase crrection AN5491K s Block Diagram H-AFC2 H-duty adj. 39 H VCO H-OSC 42 EW H-WID Phase V-POS out Parallel out POL V EHT-AC EHT out correction V- EHT H- EHT 4 2 5 V-amp. Gain-SW Latch-SW V-latch pulse I2C decode V-AGC timing H AFC1 Sync. DEF DAC Data latch HP slice X-ray det. V-BLK gen. FBP in 41 V-SAW correction V/I converter H-parabola Trape 7 6 40 Counter input Ramp /AGC VP slice 16 13 14 12 15 17 V OSC 18 20 H-POS H AFC2 H duty H out 222 Counter BF Counter PG Counter decode 7 2 Counter Shut down det. 10 11 21 1 BLK out V-SAW in V-SAW lower V-SAW upper Comparator in Comparator out 2 3 4 5 6 7 8 9 VS2 SCL SDA VP in Ramp V-OSC I2L VCC H-VCC Shut down Comparator ref. H-AFC1 DEF VCC Trapezoid H-pulse in ICs for TV ICs for TV s Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 H-AFC1 H-pulse input H-VCC (6.2 V) Shut down SW Comparator ref. (6.5 V) Comparator Comparator output BLK output V-SAW slice voltage (High) V-SAW slice voltage (Low) V-SAW input I2L I2C VCC (5 V) SDA input Description Pin No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 V-AGC EHT-DC input EHT-AC input ×8 ×4 VGA V-output DEF GND Phase output ×2 EW output Corner slice voltage I2L GND ×1 H-GND Lock det. H-output H-duty H-AFC2 FBP input H-OSC Description AN5491K I2C SCL input DEF VCC (9 V) V-pulse input V-pulse output V-OSC × 32 V-ramp Trapezoid correction voltage s Absolute Maximum Ratings Parameter Supply voltage Symbol VCC VCC1 VCC2 Supply current ICC ICC1 ICC2 I3 Power dissipation *2 *1 Rating 5.6 10 24 29 14 600 −20 to +70 −55 to +150 Unit V mA PD Topr Tstg *1 mW °C °C Operating ambient temperature Storage temperature Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2: The power dissipation shown is for the independent IC without a heat sink in free air at Ta = 70°C. 3 AN5491K s Recommended Operating Range Parameter Supply voltage Symbol VCC1 VCC2 Range 4.5 to 5.0 to 5.5 8.1 to 9.0 to 9.9 ICs for TV Unit V s Electrical Characteristics at Ta = 25°C Parameter DC characteristics Circuit current ICC1 Circuit current ICC2 Circuit current ICC3 Synchronizing signal processing Horizontal free-running oscillation frequency 1 [Divide-by-8] Horizontal free-running oscillation frequency 2 [Divide-by-16] Horizontal free-running oscillation frequency 3 [Divide-by-32] Horizontal output pulse duty cycle 1 [Divide-by-32] Horizontal output pulse duty cycle 2 [Divide-by-32] Horizontal high-level output voltage Horizontal low-level output voltage Horizontal output start voltage fHO8 fHO16 fHO32 τHO1 τHO2 VFHH VFHL VFHS Pin 2: Without input, Pin 25: High Pins 19, 26, 31, 35: Low Pin 2: Without input Pins 19, 25, 26, 31, 35: Low Pin 2: Without input Pin 19: High Pin 2: Without input, Pin 39: 2 V Pin 19: High Pin 2: Without input, Pin 39: 5 V Pin 19: High DC voltage for pin 38 high-level DC voltage for pin 38 low-level Minimum voltage of pin 3 to become f > 10 kHz when horizontal oscillation output is 1 V[p-p] or more in divide-by-32 mode. Pin 25: Low, Pins 19, 26, 31, 35: High Change amount of phase difference between HP and H-out of Data 08: [00] to [1F] Pin 19: Low, Change amount of phase difference between HP and H out of Data 08: [00] to [1F] Slice level of pin 2 Pin 4 voltage at I4 = 50 µA 61.5 30.8 15.4 11.7 23.9 2.8 0  62.7 31.4 15.7 14.0 28.5 3.5  4.2 63.9 32.0 16.0 16.6 33.7 4.2 0.3 5.0 kHz kHz kHz µs µs V V V I12 I15 I3 VCC1 = 5 V, VCC2 = 9 V VCC1 = 5 V, VCC2 = 9 V VCC1 = 5 V, VCC2 = 9 V, VCC3 = 6.5 V 13.6 16.8 6.0 17.0 21.0 7.5 20.4 25.2 9.0 mA mA mA Symbol Conditions Min Typ Max Unit Screen center variable range 1 [Divide-by-16] tDH16 2.16 2.70 3.24 µs Screen center variable range 2 [Divide-by-32] tDH32 3.8 4.8 5.8 µs Horizontal input pulse threshold voltage Over-voltage protective operation voltage VT2 V4 0.9 0.60 1.5 0.75 2.1 0.90 V V 4 ICs for TV s Electrical Characteristics at Ta = 25°C (continued) Parameter Deflection correction processing VP pulse for OSD low-level VP pulse for OSD high-level EHT-AC input pin voltage Vertical input signal threshold voltage Vertical free-running oscillation frequency Typical vertical output amplitude Typical EW output amplitude Phase out amplitude Ramp waveform amplitude AGC input and output current Service SW: ON time Vertical output DC BLK pulse high-level BLK pulse low-level Vertical output amplitude variable ratio (max.) Vertical output amplitude variable ratio (min.) VLOSD VHOSD V24 VTFV fVO VV VEW VPHASE VRAMP IAGC V28SW VHBLK VLBLK ∆VAMPmax V amplitude ratio between typ. → max. ∆VAMPmin V amplitude ratio between typ. → max. VCC1 = 5 V, VCC2 = 9 V VCC1 = 5 V, VCC2 = 9 V Pin 24: Open Pin 16: Input Pin 16: Without input external R = 10 kΩ, C = 3.3 µF V amplitude DAC: Typ. EW output amplitude for typical vertical output amplitude = 1.25 V[p-p] Side pin parallel, DAC: Typ. fV = 50 Hz to 120 Hz 0 2.2 2.00 0.9 35 0.88 0.8 − 0.1 2.15 1.6 3.1 4.5 0 +40 −40  2.75 2.45 1.5 44 1.10 1.0 0 2.45 2.0 3.5 5.0  +50 −50 Symbol Conditions Min Typ AN5491K Max Unit 0.4 3.3 2.90 2.1 53 1.32 1.2 0.1 2.75 2.4 3.9 5.5 0.4 +60 −60 V V V V Hz V[p-p] V[p-p] V[p-p] V[p-p] mA V V V % % V V V V V V V[p-p] V[p-p] V V V Vertical output DC variable amount (min.) ∆VSHIFTmin Vertical DC: Typ. → min. Vertical output DC variable amount (max.) ∆VSHIFTmax Vertical DC: Typ. → max. − 0.28 − 0.38 − 0.48 +0.28 +0.38 +0.48 Vertical output trapezoidal waveform ∆VTRAPmin Trapezoidal waveform correction: − 0.28 − 0.38 − 0.48 correction variable amount (min.) Typ. → min. Vertical output trapezoidal waveform ∆VTRAPmin Trapezoidal waveform correction: +0.28 +0.38 +0.48 correction variable amount (max.) Typ. → max. External trapezoidal waveform center voltage Vertical output center DC level EW output (min.) to parabolic amplitude change EW output (max.) to parabolic amplitude change EW output (min.) (DC) to horizontal amplitude change EW output (max.) (DC) to horizontal amplitude change EW output (bottom voltage) 1 to EHT-DC change V21 V28 VEWmin VEWmax Parabolic amplitude: Min. Parabolic amplitude: Max. 2.4 2.8 − 0.1 1.4 3.0 3.5 0 1.8 3.6 4.2 0.1 2.2 ∆VEWmin Horizontal amplitude: Min. ∆VEWmax Horizontal amplitude: Max. ∆VEDC1 EHT-DC: 5.0 V → 3.8 V Horizontal EHT: Max. EHT-AC gain: Min. − 0.95 −1.15 −1.35 +0.95 +1.15 +1.35 +1.04 +1.30 +1.56 5 AN5491K s Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ ICs for TV Max Unit Deflection correction processing (continued) EW output (bottom voltage) 2 to EHT-DC change EW output (bottom voltage) 1 to EHT-AC change EW output (bottom voltage) 2 to EHT-AC change EW output parabolic DC level ∆VEDC2 EHT-DC: 5.0 V → 6.2 V Horizontal EHT: Max. EHT-AC gain: Min. ∆VEAC1 EHT-AC: 2.35 V → 1.35 V Horizontal EHT: Max. EHT-AC gain: Max. ∆VEAC2 EHT-AC: 2.35 V → 3.35 V Horizontal EHT: Max. EHT-AC gain: Max. V32 Typ. −1.04 −1.30 −1.56 V +0.25 +0.35 +0.45 V − 0.25 − 0.35 − 0.45 V 2.2 2.7 3.4 V V V V V V V V V Parallelogram correction fluctuation 1 ∆VUPH1 Parallelogram correction: (upper side) Typ. → min. Parallelogram correction fluctuation 2 ∆VUPH2 Parallelogram correction: (upper side) Typ. → max. Parallelogram correction fluctuation 3 ∆VBPH1 Parallelogram correction: (lower side) Typ. → min. Parallelogram correction fluctuation 4 ∆VBPH2 Parallelogram correction: (lower side) Typ. → max. Bow shape correction fluctuation 1 (upper side) Bow shape correction fluctuation 2 (upper side) Bow shape correction fluctuation 3 (lower side) Bow shape correction fluctuation 4 (lower side) I2C interface SCL, SDA input threshold voltage Sink capacity at ACK Maximum clock frequency • Design reference data VTH VACK fSCL VCC1 = 5 V I = 3 mA in case of pull-up resistor 1.6 Ω ∆VUSD1 Bow shape correction: Typ. → min. ∆VUSD2 Bow shape correction: Typ. → max. ∆VBSD1 ∆VBSD2 Bow shape correction: Typ. → min. Bow shape correction: Typ. → max. +0.16 +0.26 +0.36 − 0.16 − 0.26 − 0.36 − 0.25 − 0.35 − 0.45 +0.16 +0.26 +0.36 − 0.24 − 0.34 − 0.44 +0.12 +0.22 +0.32 − 0.17 − 0.27 − 0.37 +0.12 +0.22 +0.32 1.5  100    3.0 0.4  dB V kHz Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter DC characteristics AGC pulse width Ramp discharge current Ramp charge current 1 Ramp charge current 2 Symbol τAGC IRAMP1 IRAMP2 IRAMP3 Conditions Min  3.6 Typ Max     Unit µs mA µA µA 95  138 32.9 f = 120 Hz, Pin 4: 5.7 V f = 30 Hz, Pin 4: 7.5 V   6 ICs for TV s Electrical Characteristics at Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. AN5491K Parameter DC characteristics (continued) BLK output amplitude Vertical output drive current Vertical output amplitude fluctuation with supply voltage Vertical output DC fluctuation with supply voltage EW output amplitude fluctuation with supply voltage EW output DC fluctuation with supply voltage Synchronizing signal processing Horizontal free-running oscillation frequency [Divide-by-15] Horizontal output pull-in range [Divide-by-8] Comparator detection operation voltage Lock detection output voltage Lock detection charge and discharge current FBP (AFC2) slice level Horizontal AFC µ Horizontal VCO β FBP allowable range 1 [Divide-by-8] FBP allowable range 2 [Divide-by-16] FBP allowable range 3 [Divide-by-32] AFC1 reference current 1 AFC1 reference current 2 AFC1 reference current 3 AFC1 reference current 4 Horizontal output pull-in range 1 [Divide-by-16] Horizontal output pull-in range 2 [Divide-by-32] Symbol Conditions Min Typ Max Unit VBLK I28 VV ∆VCC V28 ∆VCC VEW ∆VCC V32 ∆VCC Difference of VCCmax − VCCmin Difference of VCCmax − VCCmin Difference of VCCmax − VCCmin Difference of VCCmax − VCCmin 4 −2     5  0.1 1.0 0.1 1.0 6      V mA V V V V fHO15 fHP8 V6 V37 ILOCK VTFBP µ β tFBP8 tFBP16 tFBP32 IAFC1 IAFC2 IAFC3 IAFC4 fHP16 fHP32 Pin 2: Without input, Pin 19: Low Pins 25, 26, 31, 35: High 32.9 33.5 34.1  6.9 6.9  2.3   9 13 20       kHz Hz V V mA V µA/µs Hz/mV µs µs µs mA mA mA mA Hz Hz Pin 2: Without input, Pin 25: High ±2 000 ±2 600 Pins 19, 26, 31, 35: Low Pin 6: Minimum voltage to become high, Pin 5: 6.2 V V37 in horizontal AFC lock mode DC measurement in divide-by-32 Minimum voltage of pin 41 at which AFC operates. DC measurement in divide-by-32 Slant of β curve near f = 15.7 kHz Time from H-out rise to FBP center Time from H-out rise to FBP center Time from H-out rise to FBP center Data 0C = "11" (D1, D0) Data 0C = "01" (D1, D0) Data 0C = "10" (D1, D0) Data 0C = "00" (D1, D0) Pin 2: Without input Pins 19, 25, 26, 31, 35: Low Pin 2: Without input Pin 19: High 5.7 5.7  1.5   3 4 6     6.3 6.3 ±0.8 1.9 37 1.9    0.82 1.1 1.5 2.0 ±1 000 ±1 300 ±500 ±650 7 AN5491K s Electrical Characteristics at Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. ICs for TV Parameter Deflection correction processing Vertical output S-shape variable ratio 1 Vertical output S-shape variable ratio 2 Vertical output (upper side) linearity variable ratio 1 Vertical output (upper side) linearity variable ratio 2 Vertical output (lower side) linearity variable ratio 1 Vertical output (lower side) linearity variable ratio 2 Vertical output EHT-DC change 1 Vertical output EHT-DC change 2 Vertical output EHT-AC change 1 Vertical output EHT-AC change 2 EW output (min.) to trapezoidal waveform change EW output (max.) to trapezoidal waveform change EW output (min.) to upper corner trapezoidal waveform change EW output (max.) to upper corner trapezoidal waveform change EW output (min.) to lower corner trapezoidal waveform change EW output (max.) to lower corner trapezoidal waveform change Symbol ∆VSC1 ∆VSC2 Conditions Min   Typ −28 1.5 Max   Unit % % Vertical S-shape: Ratio of min.→max. Vertical S-shape: Ratio of min.→ max. (Change of V-out 40% to 60% point) ∆VULIN1 Vertical linearity (upper side): Typ.→max. ∆VULIN2 Vertical linearity (upper side): Typ.→min. ∆VBLIN1 Vertical linearity (lower side): Typ.→max. ∆VBLIN2 Vertical linearity (lower side): Typ.→min. ∆VEDC1 EHT-DC = 5.0 V → 3.8 V Vertical EHT: Max., EHT gain: Max. ∆VEDC2 EHT-DC = 5.0 V → 6.2 V Vertical EHT: Max., EHT gain: Max. ∆VEAC1 EHT-AC = 2.35 V → 1.35 V EHT: Max., EHT gain: Max. ∆VEAC2 EHT-AC = 2.35 V → 3.35 V EHT: Max., EHT gain: Max. ∆VTRAPmin Trapezoidal SW: On, Trapezoidal: Typ. → min. ∆VTRAPmax Trapezoidal SW: On, Trapezoidal: Typ. → max. ∆VUCmin Upper corner: Typ. → min. Corner slice voltage: 1 V ∆VUCmax Upper corner: Typ. → max. Corner slice voltage: 1 V ∆VBCmin Lower corner: Typ. → min. Corner slice voltage: 1 V ∆VBCmax Lower corner: Typ. → max. Corner slice voltage: 1 V External trapezoidal correction: 3V→2V External trapezoidal correction: 3V→4V                 +12 −10 +9 −11 −30 +25 −12 +12 −40 +40 −45 +45 −45 +45 −40 +40                 % % % % % % % % % % % % % % % % External trapezoidal waveform correction ∆VETR1 fluctuation 1 (Parabolic amplitude) External trapezoidal waveform correction ∆VETR2 fluctuation 2 (Parabolic amplitude) 8 ICs for TV s Electrical Characteristics at Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. AN5491K Parameter I2C interface Symbol Conditions 1LSB = {Data(max.) − Data(00)}/7,15,31,63 1LSB = {Data(max.) − Data(00)}/127 1LSB = {Data(max.) − Data(00)}/127 Min Typ Max Unit 3, 4, 5, 6-bit DAC DNLE 7-bit DAC DNLE (Except for 40) 7-bit DAC DNLE (40 only) L1 L2 L3 0.1 0.1 −1.0 1.0 1.0 1.0 1.9 1.9 2.0 LSB/step LSB/step LSB/step s Terminal Equivalent Circuits Pin No. 1 Equivalent circuit Description AFC1: Horizontal frequency detection pin • Pin for adjusting the frequency of horizontal input pulse and the internal reference pulse. • Connect a lag lead filter. Voltage 6.5 V 3.15 V 4.3 V 27 kΩ 1 DC approx. 4.3 V 5.3 V 2 3V 100 kΩ 2 1 kΩ 1.5 V 9V H-pulse in: Horizontal synchronizing signal input pin • Polarity is as shown in the right figure (Negative). • Slice level is 1.5 V. • Input polarity is one polarity only (not corresponding to both polarities). AC 1.5 V H rate 3 12 V 330 Ω 3 VCC: Horizontal system power supply (6.5 V) pin • Connect an external zener DC 6.5 V 4 28 kΩ 28 kΩ 6.5 V 4 Shut down: DC Control pin for shut-down Normal: GND • Horizontal output stops (GND) if a voltage 1 VBE and over (more than approx. 0.75 V) is applied to the pin. 9 AN5491K s Terminal Equivalent Circuits (continued) Pin No. 5 Equivalent circuit 6.5 V ICs for TV Description Comparator ref.: Reference voltage input pin for comparator • Attach zener diode externally (approx. 6.2 V) (Usable as reference voltage for hold-down) Voltage DC 5 1 kΩ 6 6.5 V Comparator: Input pin for comparator detection • (Usable as pin for hold-down detection) 5 1 kΩ DC 6 1 kΩ 7 9V 25 kΩ Comparator out: Comparator detection output pin • Connect pull-up resistors outside the IC. (usable as hold-down control pin) Note) Use under 400 µA or less. DC Normally: High 7 20 kΩ 48.3 kΩ 20 kΩ 8 9V BLK out: Blanking pulse output pin • Normally: Low At BLK: High (5 V) DC At BLK: High 8 99.8 kΩ 9 9V Upper side slice: Upper side slice voltage input pin for BLK pulse generation Upper side DC 9 20 kΩ 145 Ω 145 Ω BLK 10 ICs for TV s Terminal Equivalent Circuits (continued) Pin No. 10 9V AN5491K Equivalent circuit Description Lower side slice: Lower side slice voltage input pin for BLK Pulse generation Voltage DC 10 20 kΩ 145 Ω Lower side BLK 11 9V 25 µA V-SAW in: V-SAW input pin for BLK pulse generation AC 11 20 kΩ 145 Ω 12  VCC: Power supply (5 V) pin for DAC/I2L • Connect a pass capacitor (0.01 µF) between pin 12 and GND (pin 19). DC 5V 13 5V 20 µA SDA: I2C data input pin 5V 13 1 kΩ GND 14 5V 20 µA SCL: I2C clock input pin 5V 14 1 kΩ GND 15  VCC: Pin for deflection system power supply (9 V) • Connect a pass capacitor between the pin and GND. DC 9V 11 AN5491K s Terminal Equivalent Circuits (continued) Pin No. 16 290 Ω 25 µA ICs for TV Equivalent circuit 9V Description V-pulse in: Vertical sync. signal input pin • Polarity is as shown in the right figure (Negative) • Slice level is 1.5 V. • Input polarity is only one polarity (Not correspond to both polarities) Voltage AC (Pulse) 1.5 V 0V V rate 16 30 kΩ 290 Ω 1.5 V 17 9V 17 55 kΩ V-pulse out: AC Vertical sync. signal output pin (Pulse) • If vertical sync. signal input is present: 2.5 V Outputs the pulse synchronized with input V. Not present: Outputs free-running V pulse. 0V (Usable for microcomputer OSD control) V rate V-OSC: Vertical oscillation pin • Connect CR. • Free-running oscillation when there is no input. AC 5.8 V 18 9V 5V 36 kΩ 18 1 kΩ 50 µA V rate 3.1 V 19 150 kΩ 19 6.5V × 32: Horizontal free-running oscillation frequency control pin • To be used by high/low control. • Input is controlled by open collector output. DC 30 kΩ 30 kΩ 30 kΩ 20 1kΩ 9V V-ramp pin: • The pin for generating reference V sawtooth waveform for IC inside. • Connect an 0.22 µF mylar capacitor. AC 2.5 V 20 V rate 2.5V 0V 12 ICs for TV s Terminal Equivalent Circuits (continued) Pin No. 21 25 µA 21 145 Ω AN5491K Equivalent circuit 9V Description External trapezoidal waveform: The pin for controlling trapezoidal waveform compensation from outside. • Used by linking to V-position shift (at AC coupling). typ. 3.0 V Voltage DC 2 V to 4 V 22 500 Ω 9V 22 500 Ω 145 Ω V-AGC: Vertical AGC pin • AGC pin to make a vertical output amplitude constant. • Connect 3.3 µF tantalum capacitor. DC 23 9V 23 3.8 V 20 kΩ 5.45 V EHT-DC: DC Pin for extremely high-tension compensation (EHT) • DC-coupled to pin. Operating range: 3.8 V to 6.2 V 24 25 µA 20 kΩ 24 145 Ω 9V 25 µA 20 kΩ EHT-AC Pin for extremely high-tension compensation • AC-coupled to pin. AC 2.35 V in an open mode Operating range: 1.35 V to 3.35 V × 8: Horizontal free-running oscillation frequency control pin • To be used by high/low control. • Input is controlled by open collector output. DC 145 Ω 25 150 kΩ 25 20 kΩ 20 kΩ 6.5 V 13 AN5491K s Terminal Equivalent Circuits (continued) Pin No. 26 150 kΩ 26 20 kΩ 20 kΩ Equivalent circuit 6.5 V Description × 4: Horizontal free-running oscillation frequency control pin • To be used by high/low control. • Input is controlled by open collector output. ICs for TV Voltage DC 27 6.5 V 27 60 kΩ V-FB: Forced progressive mode pin • To be used by high/low control. • At high: Multi-point mode At low: Progressive mode DC 28 300 Ω ×5 9V V-out: V sawtooth waveform output pin • Typ. 1.25 V[p-p] AC 9V 100 Ω 28 ×5 0V 290 Ω 29 30  GND: GND pin for deflection-system circuit (9 V) DC GND 9V 290 Ω 30 Phase out: AC Pin for side pin (Bow shape) correction, parallelogram correction and control pulse output. DC • Connect to H-AFC2 pin via 1 µF (non- approx. 3.7 V polarity) capacitor. 290 Ω Max. 300 mV[p-p] 14 ICs for TV s Terminal Equivalent Circuits (continued) Pin No. 31 150 kΩ 31 20 kΩ 20 kΩ 32 500 Ω 40 kΩ 10 kΩ 300 Ω 1.5 V EW out: Parabolic waveform output pin Equivalent circuit 6.5 V Description × 2: Horizontal free-running oscillation frequency control pin • To be used by high/low control. • Input is controlled by open collector output. AN5491K Voltage DC 9V AC 9V 32 33 50 µA 50 µA 9V 33 Corner slice: DC The voltage to set a slice point of upper and lower corner correction. • The correction gain can be controlled inde- Externally set pendently by I2C bus for upper and lower, at 0 VDC to respectively. 1.25 VDC 34 35 GND: GND pin for 5 V system (I2C/I2L) × 1: Horizontal free-running oscillation frequency control pin • To be used by high/low control. DC GND DC 6.5 V 150 kΩ 35 10 kΩ 36 37  GND: GND pin for 6.5 V system (Horizontal system) DC GND 200 Ω 820 µA 37 880 µA 6.5 V Lock det.: DC Horizontal lock detection pin • Connect 0.022 µF and 1 MΩ between the At lock mode: pin and GND. 6V At unlocked mode: GND 15 AN5491K s Terminal Equivalent Circuits (continued) Pin No. 38 Equivalent circuit 6.5 V ICs for TV Description H-out: Horizontal output pin • The length of high-period can be adjusted by a separate pin. Voltage AC 2.9 V 3.2 mA 38 15 kΩ 40 kΩ GND H rate 39 6.5 V 124 kΩ 39 10 kΩ 124 kΩ H-duty: Pin for controlling the length of high-period of horizontal output pulse. • Apply DC voltage from the outside. DC 1 V to 5 V 40 6.5 V 1.9 V 40 3.9 V AFC2: Horizontal phase detection pin • Pin for controlling phase difference between horizontal output pulse and FBP. • Phase out waveform is also connected to this pin via capacitor. • Connect 0.015 µF between this pin and GND. DC 1.5 V to 4.5 V 41 6.5 V 50 µA 2.7 kΩ 41 100 kΩ 1.9 V FBP input pin: AC • Slices at 1.9 V (in the IC) and then uses 1.9 V as AFC2 control pulse. • Do not input any signal under GND insiGND de the IC. 42 6.5 V 270 Ω 42 270 Ω 300 Ω 200 µA 10 kΩ H-OSC: AC Reference oscillation pin (500 kHz) 2.25 V • Connect CERALOCK (CSB500F48), and temperature guaranteed (N750) 220 pF capacitor in series between this pin and 0.5 V[p-p] GND. 100 µA 3.0 V 16 ICs for TV s Application Circuit Example 9V AGC EHT DC EHT AC 3.3 µF 22 23 24 18 9 V 10 kΩ V-out DEF GND Phase out 28 29 30 17 16 15 14 4.7 kΩ 4.7 kΩ 9V 3.3 µF 21 20 0.22 µF AN5491K Trapezoid Ramp V-OSC VS2 VP in DEF VCC SCL EW out Corner level V × 32 ×8 ×4 ×2 ×1 VGA I2L GND 1 MΩ 0.22 µF 6.5V 10 kΩ 1 µF 6.5 V 220 pF *1 H-OSC 32 33 19 25 26 31 35 27 34 36 37 38 39 40 41 42 13 SDA I2L VCC V-SAW in V-SAW lower V-SAW upper BLK out Comparator out Comparator in Comparator ref. Shut down H-VCC 330 Ω 12 V H-pulse in 22 µF 620 Ω H-AFC1 0.033 µF 12 5V 11 10 9 8 7 6 5 6.5 V 4 3 6.5 V 2 1 H-GND Lock det. H-out H-duty adj. H-AFC2 FBP in *1: Horizontal oscillator TAFCSB500F48 [Murata Manufacturing Co. Ltd.] 17