AN6448NFBP

AN6448NFBP Speech Network IC Incorporating Cross-Point Switch s Overview The AN6448NFBP is a speech network IC suitable for multifunction cordless telephones. It incorporates a cross-point switch controlled by serial input. It allows speech path switching and mixing, and provides for three- or four-person communication and other sophisticated functions. It also incorporates REC/PLAY amplifiers with VOX circuits. 48 49 17.2±0.4 14.0±0.3 33 32 Unit : mm s Features • The speech block can operate on line voltage, with no exter• • • • • nal power supply, and is operational even during a commercial power failure. Incorporates auto. PAD, dial mute, DC voltage regulation, and other basic speech functions. The cross-point switch can be operated independently. Each output of the cross-point switch can correspond to multiple inputs, allowing three-or four-person communication. The REC/PLAY amplifiers incorporate ALC and VOX circuits. Receiver volume can be increased by 6 dB or 9 dB. 64 1 16 17 0.2 -0.05 1.3±0.1 2.85±0.2 1.3±0.1 0.1±0.1 (0.8) 0.8 0.35 -0.05 SEATING PLANE +0.1 QFP package with 64 pins (QFH064-P-1414A) s Block Diagram 48 49 50 51 52 53 54 55 56 57 58 59 Power Supply Control 60 61 62 63 64 1 – + – + – + 47 46 45 – + 44 43 ACL 42 41 ACL Det 40 39 38 37 VOX Det. 36 35 34 33 32 VREF 10dB 0dB 0dB 0dB Comp I N J 31 30 29 0/12 dB 20 dB 18 dB 18 dB 28 27 D a1 a2 a3 a4 a5 a6 26 25 24 23 22 DC Cont. 21 20 19 0dB 20 dB 0dB 0dB 0dB P.O.R Line Supply Monitor 0dB Decoder Latch AP Hold off AP Cont. – + DM Cont. 0dB 0dB AP VREF 18 17 – + 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +0.1 14.0±0.3 17.2±0.4 s Absolute Maximum Ratings (Ta=25˚C) Parameter Supply voltage (1) Supply current (1) Supply voltage (2) Supply current (2) Power dissipation Note) Operating ambient temperature Storage temperature Note) In a free-air condition with Ta=75˚C. Symbol VCC ICC VL IL PD Topr Tstg Rating 7.0 50 12.0 135 640 –20 to +75 –55 to +150 Unit V mA V mA mW ˚C ˚C s Recommended Operating Conditions (Ta=25˚C) Parameter Operating supply voltage range (1) Operating supply voltage range (2) Clock frequency Symbol VCC VL fCLK Condition min 4.5 3 typ 5 max 5.5 11 250 Unit V V kHz s Electrical Characteristics (Ta=25˚C) Parameter Speech network block Rec. gain Rec. automatic PAD width Trans. gain Trans. automatic PAD width DTMF gain DTMF automatic PAD width REC/PLAY amp. block Head bias current REC preamp. output EQ amp. gain Switch block SP out max output DH out max output RF1 out max output RF2 out max output L-REC out max output VO–SP VO–DH VO–RF1 VO–RF2 VO–LR Input L-SP IN, THD=5% Input RF1 IN, THD=5% Input RF2 IN, THD=5% Input RF1 IN, THD=5% Input AUX IN, THD=5% 0 0 0 0 0 4 4 4 4 4 dBm dBm dBm dBm dBm I–REC VO–RP GV–EQ Vin=–45dBm, Rin=10kΩ Vin=–40dBm 145 –13.4 27.8 180 –11.4 29.8 215 –9.4 31.8 µA dBm dB GV–ER1 AP–ER GV–EM1 AP–EM GV–ED1 AP–EDT IL=30mA, VCC=5V, Vin=–42dBm IL=30 to 80mA, VCC=5V, Vin=–42dBm IL=30mA, VCC=5V, Vin=–38dBm IL=30 to 80mA, VCC=5V, Vin=–38dBm IL=30mA, VCC=5V, DM=ON, Vin=–30dBm IL=30 to 80mA, VCC=5V, V–DMC=LOW, Vin=–30dBm 30.5 2.5 27.7 2.5 16.9 2.5 32.5 3.7 29.7 4 18.9 4.1 34.5 5 31.7 5 20.9 5.5 dB dB dB dB dB dB Symbol Condition min typ max Unit s Timing Chart 1/fCLK twh (CLK) tWL 90% 2.5V 10% (CLK) CLK 10% 90% 2.5V tr (CLK) 2.5V tf (CLK) DATA 2.5V 2.5V tsu (DATA) th (DATA) tsu STR (STB) tsr 2.5V (STB) 2.5V tW (STB) s Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Ground Line power (+) input Side-tone adjustment Line voltage control (1) Int. ref. voltage output (1) Int. ref. voltage output (2) Hold-reset control Trans. preamp. output Auto. PAD control Rec. preamp. input Rec. preamp. output Rec. amp. input Rec. amp. output (1) Rec. amp. output (2) MIC preamp. output MIC preamp. input (1) MIC preamp. input (2) DTMF signal input BT signal input Dial mute control Line voltage control Line interruption detector output Hold-reset signal output No connection Strobe signal input Clock signal input No connection Data input Ground Logic power supply input VOX detector output SP link output Description Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RF2 link output RF1 link output Intercom link output VOX detection control VOX amp. input Time stamp link output Recording link output ALC input ALC detection control Loudspeaker link input Recording input Recording inverse input Recording preamp. output Recording bias current control To recording head EQ amp. inverse input EQ amp. output REC/PLAY int. ref. voltage output Ground MIX preamp. output MIX link input AUX preamp. output AUX link input Intercom link input RF1 link input RF2 link input Power-ON reset control External supply voltage input Internal supply voltage output Circuit voltage control (2) Line current bypass (2) Line current bypass (1) Description s Pin Descriptions PinNo. Symbol I/O 1 GND Waveform 0V Description Ground : • This is the ground pin for the speech network. Line power input : • Connects to the positive output of the diode bridge. Side-tone adjustment : • Grounded through R1 (27Ω). • Connects to the side-tone adjusting circuit to adjust side tone and receiver level. Line voltage control (1) : Int. ref. voltage output (1) : • Outputs half the Vreg reference voltage. • Grounded through a 0.01µF capacitor. Int. ref. voltage output (2) : • Output impedance=50Ω Hold-reset control : • Grounded through C5. Adjusts the output time of control signals. Hold-reset signal output : • This is an open-collector output to a microprocessor. • Requires a pull-up resistor. Equivalent Circuit GND for REC/PLY, VRER SPEECH and LINK. Remarks DC 2 VL I 2 3 to 10V TO 3 ST O The line drive gain (G) is : Z //Z G = Line Tel R1 Also assuming ZLine 600Ω ZTel 600Ω R1=27Ω : 300 =20.9dB 27 C2 and the internal resistance determine the f. characteristics. G=20log DC 0.3V 3 4 VL– CONT I DC1V 1V 5 VREF O (Const) 24kΩ 5 24 kΩ + – 61 Vreg 6 VREF 6 SN – O 1V (Const) 7 HCO IL VCC 62 + – 23 30kΩ 7 + – The larger the capacitance of C5, the wider the pulse width. 23 HCC 0V Hold-reset signal 120kΩ 8 T– FILTER O DC1V Trans. preamp. output : • C6 as connected between this pin and the ground forms a low-pass filter. Auto. PAD control : • Connects through a resistance to Pin61 (Vreg). If the resistance increases, the PAD operates closer to the near end. If the resistance decreases, the PAD operates closer to the far end. Rec. preamp. input : • Receiver signals are input from the side-tone circuit to this pin. • R7 and C8 connected between Pin11 and this pin determine Rec. preamp. output : • R7 and C8 connected between Pin10 and this pin determine the f. characteristics. • The output impedance is 100 ±50Ω. Rec. amp. input : Rec. amp. outputs (1 and 2) : • A ceramic or dynamic receiver is connected. • The output circuit is a BTL configuration. • The output impedance is 50± 30Ω. 4 6kΩ 8 C6 and the 6-kΩ internal resistance as illustrated on the left form a low-pass filter. 9 APC I Vreg-R · I IL 9 I IχIL 10 RV IN I + VREF 10 – 11 RV 11 PRE– OUT O + – 10kΩ 11 VREF The receiver preamplifier gain (G) is : 1 1 +ωC8 G= –20log R7 1 R6 + ωC9 12 RV FILTER O RV 13 OUT (1) · RV 14 OUT (2) VREF 13 + – VREF O VREF 14 12 The larger the capacitance of C10, the lower the high band gain as with a LPF. s Pin Descriptions (cont.) PinNo. Symbol I/O Waveform Description MIC preamp. output : • R11 and C13 connected between Pin17 and this pin determine the f. characteristics. • The output impedance is 300 ±100Ω. 16 + – Equivalent Circuit Remarks 15 MIC OUT O VREF VREF 10kΩ + – MIC 16 IN (+) MIC 17 IN (–) I MIC preamp. input (1) : • A bias resistor and a microphone connect to this pin. MIC preamp. input (2) : • R11 and C13 connected between Pin15 and this pin determine the f. characteristics. DTMF signal input : • DTMF signals are input through a coupling capacitor C14. • When DMC is low at Pin20, DTMF is enabled. • Input impedance is 10kΩ. BT signal input : • Beep tone (BT) signals are input through a coupling capacitor C15. • Input impedance is 10kΩ. Dial mute control : • Normal speech mode when Pin20 is high or open (MIC amp. ON and rec. amp. ON). • DTMF mode when Pin20 is low (DTMF amp. ON and BT amp. ON). VCC 17 15 Feedback is input to this pin through a capacitor. The capacitor and R9 to R11, and C12 and C13 determine the f. characteristics. I VREF MF– 18 IN VREF/SN 10kΩ 18 + – I VREF With signal ON The input impedance (10kΩ) and C14 or C15 form an input HPF. 19 BT– IN VREF 10kΩ 19 + – I VREF With signal ON 61 200kΩ 20 100kΩ 20 DMC I DC– 21 CONT I 0.2V Line voltage increases Line voltage control : • Line voltage is normal when this pin is high. Line voltage increases by 1 to 1.5V when this pin is low. Line interruption detector output : • This is an open collector output to a microprocessor, requiring a pull-up resistor connected to the microprocessor's power supply. This pin goes low when line voltage is 3.0V or more, and goes high when 1.5V or less. No connection Strobe signal input : • The strobe signal for serial control data is input to this pin. The rising edge of the strobe signal determines the timing at which internal control address or ON/OFF status is validated. Clock signal input : • The clock signal for serial control data is input to this pin. The rising edge of the clock signal determines the timing at which data is read. No connection 21 150kΩ 200kΩ VCC VL 2 22 TrCPC 22 CPC O R2 144kΩ R1 56kΩ • Referring to the left figure, the voltage, VCPC, at which T rCPC turns ON is calculated as follows: VCPC (ON) = R1 + R2 × VBE (TrCPC) R1 = 2.5V (Ta=25˚C) 0.2V Line interruption 24 NC 5V 25 10kΩ 300kΩ VCC 25 STR I 0V 5V 26 10kΩ 300kΩ VCC 26 CLK I 0V 27 NC s Pin Descriptions (cont.) PinNo. Symbol I/O Waveform 5V Description Data input : • Serial data is input to this pin. Data is read into the internal shift register in synchronization with clock signals. Ground : • This is the ground pin for the logic circuits. Logic power supply input : Equivalent Circuit 28 10kΩ 300kΩ VCC Remarks 28 DATA I 0V 29 GND L– 30 V CC VCC 31 VOX. O OUT 0V Voice on VOX detector output : • This is an open collector output. • This pin goes low when voice signals are input to Pin37. Loudspeaker link output : • This is a link switch output to an external loudspeaker amplifier. • The output amplifier gain is selectable between 12 and 0dB. • Output impedance is 50±30Ω. RF2 link output : • This is a link switch output. • Output impedance is 50±30Ω. RF1 link output : • This is a link switch output. • Output impedance is 50±30Ω. 31 • Output waveforms are shaped stable internally (by the threshold circuit). VREF LINK From LINK SW + – 0/12dB 50kΩ 32 32 SP. OUT O VREF 10kΩ VREF 30kΩ When address 2F of the crosspoint switch is OFF, the output amplifier gain is set to 12 dB. 33 RF2 – O OUT RF1 – O OUT VREF LINK From LINK SW 50kΩ + – VREF 33 34 34 10kΩ 68kΩ VREF VREF 35 DH – OUT O VREF Intercom link output : • This is a link switch output to a intercom. • Output impedance is 50±30Ω. LINK From LINK SW 10kΩ 50kΩ + – 35 90kΩ 36 VOX DET O DC (with a capacitor) Pin36 output Pin37 input (with no capacitor) Half-wave rectification VOX detection control : • A smoothing capacitor (C17) and a resistor (R19) connect in parallel to this pin to adjust the attack and recovery times of the VOX detector. VREF + 37 500Ω R1 – 500Ω 36 • VOX detection can be done in two ways : A) With small C17 (560pF) and small R19 (39kΩ) VOX input VOX output B) With large C17 (22µF) and large R19 (100kΩ) VOX input VOX output • Input sensitivity is calculated as follows : R2//ZC1 R1 Adjust the f. characteristics and sensitivity based on the above calculation. G= 37 VOX IN I VOX amp. input : • VOX (voice detection) signals are input to this pin. • Input impedance is 500Ω. C1 R2 s Pin Descriptions (cont.) PinNo. Symbol I/O LTS – 38 OUT O Waveform Description Time stamp link output : • This is a buffered link switch output. • Output impedance is 50±30Ω. Recording link output : • This is a buffered link switch output. • Output impedance is 50±30Ω. ALC input : • Pin45 connects through a coupling capacitor to this pin. • Input impedance is 10kΩ. DC (with a capacitor) Pin$1 output Input (with no capacitor) Full-wave rectification Equivalent Circuit Remarks VREF LINK To LINK SW + – 38 39 39 LRC – O OUT VREF 40 ALC. IN I VCC VREF + 41 ALC. DET O 42 SP – IN I VREF RD 43 PRE – IN I VREF RD 44 PRE – NF REC 45 PRE – OUT I VREF ALC detection control : • A smoothing capacitor (C20) and a resistor (R22) connect in parallel to this pin to adjust the attack and recovery times of the ALC. Loudspeaker link input : • SP signals to this pin are output through a coupling capacitor to the link switch. • Input impedance is 50kΩ. Recording input : • Recording signals are input through a coupling capacitor to this pin. • Input impedance is normally 10 kΩ. It decreases during ALC operation. Recording preamp. inverse input : • A C/R combination between Pin45 and this pin determines the gain and f. characteristics of the recording preamplifier. Recording preamp. output : • Outputs amplified recording signals. • Output impedance is 50±30Ω. Recording bias current control : • A C/R combination connected to this pin determines the recording bias current and gain of a recording head. • The smaller the resistance of the C/R combination, the greater the bias current and gain. To recording head : • A recording head connects to this pin. EQ amp. inverse input : • A C/R combination between pin49 and this pin determines the equalizer characteristics. EQ amp. output : • Outputs amplified equalizer signals. • Output impedance is 50±30Ω. REC/PLAY int. ref. voltage output : • The pin5 ref. voltage is buffered and output from this pin. 40 – 2kΩ 41 • Ground Pin41 if no ALC circuit is used. • The larger C20, the longer the attack time. The smaller R22, the shorter the recovery time. VREF + LINK To LINK SW 42 50kΩ – VREF 10kΩ 43 10kΩ From ALC + – 22kΩ + – 45 The gain (G) of the recording preamplifier is : G=– R26 R24 + 1 ωC23 44 O VREF VCC 61 46 BIAS ADJ VREF 45 + – 47 HEAD I/O Bias voltage During recording 0V During playing 0V 46 R27 47 • Address 07 of the cross-point SW determines the ON/OFF status of the rec. preamp. • The bias current to the head is : Vref ×3 IH = R27 1 Vref = VREG 2 48 EQ. NF I VREF VREF + From recording head 48 – 49 49 EQ. OUT O VREF • The gain of the equalizer amp. is calculated the same way as the receiver preamp. • Address 0F of the cross-point SW determines the ON/OFF status of the EQ amp. VREF 5 + – 50 VREF – PR O VREF (CONST) 1 2 50 s Pin Descriptions (cont.) PinNo. Symbol I/O 51 GND Waveform Description Ground : • Output impedance is 50±30Ω. MIX preamp. output : • A C/R combination between Pin53 and this pin determines the gain and f. characteristics of the MIX preamp. • Output impedance is 50±30Ω. MIX link input : • MIX signals are input through a coupling capacitor to this pin. AUX preamp. output : • A C/R combination between Pin55 and this pin determines the gain and f. characteristics of the AUX preamp. • Output impedance is 50±30Ω. AUX link input : • AUX signals are input through a coupling capacitor to this pin. Intercom link input : • Intercom signals are input through a coupling capacitor C33 to this pin. • Input impedance is 10kΩ. RF1 link input : • RF1 signals are input through a coupling capacitor C34 to this pin. • Input impedance is 10kΩ. RF2 link input : • RF1 signals are input through a coupling capacitor C34 to this pin. • Input impedance is 10kΩ. Power-ON reset control : • C36 between this pin and GND determines the power-ON reset time of the logic circuits. 5V 50kΩ 59 150kΩ Equivalent Circuit Remarks 52 MIX OUT O VREF + – VREF To LINK SW The gain of the MIX preamp. is calculated the same way as the rec. preamp. 53 MIX IN 53 52 I AUX 54 OUT O VREF + – VREF To LINK SW The gain of the AUX preamp. is calculated the same way as the rec. preamp. 55 AUX IN 55 54 I VREF 10kΩ 56 + – 56 DH IN I To LINK SW VREF 57 RF1 IN I VREF VREF 57/58 10kΩ + – The input impedance as illustrated left and C33, C34, or C35 form a HPF. To LINK SW 58 RF2 IN I VREF VCC 59 PR I + Comparator – Reset signal • The larger C36, the longer the power-ON reset time. • The power-ON reset signal is output when the supply voltage reaches 4V. 60 VCC ±0.5V VCC – 0.2V External supply voltage input : • 5 ± 0.5 V power supply is input to this pin. Internal supply voltage output : • A power supply derived from line voltage is output from this pin to the internal speech network. VL 2 61 61 Vreg O DC 2V during power failure 2 64 62 VLC Circuit voltage control (2) : 2-5 VDC depending on VL • This pin is grounded through C38. 62 C38 (typically 47µF) determines how the circuit voltage fluctuates. 63 s Pin Descriptions (cont.) PinNo. Symbol I/O Waveform DC Description Line current bypass (2) : • Line current is bypassed from this pin through R39 to GND. R39 must be 1/2 W or more. Equivalent Circuit 2 VL 33Ω 64 Power supply Remarks ZTel is 1.5 to 2kΩ on the IC side. It must be adjusted to 600Ω by inserting a 820Ω resistor between VL and GND. R40 33Ω 820Ω 100µ 63 PD2 O 0 to 3V depending on VL 64 VL 64 PDI I DC Same as above VL– 33Ω × IL Line current bypass (1) : • Line current is bypassed from this pin through R40 to Pinw. R40 must be 1/2 W or more. 63 15Ω s Logic Specifications (Basic Block Diagrams) Output (cross-point SW and other controls) Latch circuit Reset Decoder Decoder (6 bit, 48 channels) Shift register A6 A5 A4 A3 A2 A1 D Clock Time charts (assuming the address h26 latch is to be set) Clock Data Strobe Data 1 (A6) 0 (A5) 0 (A4) 1 (A3) 1 (A2) 0 (A1) 1 (D) Strobe 1. Data is read into the shift register in synchronization with a rising edge of the clock, with the higher data being shifted sequentially on a first-come highest-bit basis. 2. When the strobe is low, data is shifted sequentially on the sift register in synchronization with the clock. Data on the latch circuit will not change. 3. When the strobe goes high, the latched data whose address is represented by the highest 6-bit of the shift register is updated. Latched data is set when the least significant bit is 1, and reset when the bit is 0. 4. Referring to 3 above, if the address is h00 (the highest 6bit of the shift register are all 0s), the latch circuit is cleared (all reset) regardless of the data content. 5. At power-on, the latch circuit is cleared (by power-ON reset). s Logic Circuits Address Specifications 1. Cross-point switch Input Output Handset rec. Line output Loudspeaker 02 09 10 18 20 28 30 38 21 29 31 39 32 3A 0A 12 1A 23 2B 33 3B 2C 34 3C 35 3D 3E 0B 0C 14 1C 0D 15 1D 25 0E 16 1E 26 2E 37 Intercom RF1 RF2 Recording Time stamp Loudspeaker Microphone Receiver Intercom RF1 RF2 MIX AUX Note) Empty space means “not applicable.” Address is in hexadecimal. 2. Other control switches (Address) 00 07 0F 17 1F 27 2F (Description) All reset Recording amp. ON Playing amp. ON Receiver volume 6 dB up Receiver volume 9 dB up (when address 17 is on) Handset receiver amp. mute Loudspeaker amp. gain 12 dB down Note) Address is in hexadecimal. s Package power dissipation PD – Ta 1600 Power Dissipation PD (mW) 1400 1200 1000 800 600 400 200 0 0 25 50 75 100 125 150 640mW 900mW Ambient Temperature Ta (˚C) s Application Circuit PLAY IN REC OUT C42 1µF C24 To test the circuit, short R41 and use a 1kΩ resistor for a head. C23 0.1µF 22µF R27 LINK SP– IN ALC IN LINK R– OUT VOX IN JP2 J4 DH. OUT RF1. OUT C25 12kΩ REC. PRE. OUT R26 R25 56kΩ 1kΩ REC. PRE. NF R24 10kΩ REC. IN 10kΩ 0.15µF LINK. REC. OUT R20 R19 10kΩ VOX. 560pF DET R23 C22 0.068µF C21 VOX. IN C18 10kΩ 0.033µF 0.47µF ALC. 22µF DET C20 ALC. IN 0.068µF 1kΩ EQ. IN 100kΩ R29 P.R. HEAD R26 C19 R31 330kΩ 10kΩ R30 EQ. OUT 100µF C27 0.01µF 48 47 REC. ADJ 46 45 44 43 42 41 40 39 TS. OUT 38 37 36 C17 35 34 33 SP. OUT 49 – + 50 C28 P/R. VREF 51 P/R. GND MIX. OUT 52 20kΩ R32 + – 18 dB 0/12 dB 20 dB RF2. OUT 32 R21 22µF 47kΩ C26 JP3 – + ALC ALC Det 0dB 0dB R43 VOX Det. COMP I N J 120kΩ VOX. OUT 31 Vref 0dB 10dB 30 LOGIC. VCC 100µF C16 29 LIN REC OUT 18 dB LOGIC. GND DATA 28 R33 C30 10kΩ 0.068µF 53 MIX. IN 54 RF1 20kΩ R34 SP + – RF2 AUX. OUT DH TS OUT 27 NC D a1 a2 Latch Decoder a3 NC a4 a5 a6 23 HCC 24 26 CLK R35 10kΩ C32 SP MIC LIN 0.068µF AUX. IN R38 C33 DH. IN 0.068µF C34 55 56 0dB DH RF1 25 STR RF1. IN R37 57 R38 0.068µF C35 58 0dB RF2 MIX RF2. IN (R36 to 38 : for level adjustment) 0.068µF C36 10µF PRC VCC 100µF C39 C37 C38 100µF VREG 47µF VLC C39 R15 R40 VL R33 PD2 0dB AUX 59 Power Supply Control P.O.R DC Cont. 0dB 22 DC. CONT R13 20 DM. CONT BT. IN C15 0dB CPC VREG 60 21 61 Line Supply AP DM Cont. AP 0dB Open SW2 Hold off 62 Vref 19 AP Cont. 0dB 0.068µF DYMF. IN C14 10kΩ R11 27kΩ 0.068µF MIC. IN (–) C13 0.0015µF C12 0.068µF MIC MIC. IN (+) 63 18 + – 64 PD1 R. PreOUT T. FILTER R8 6.8kΩ C7 R6 0.1µF APC C9 12kΩ VL. CONT 0.01µF HCO 0.01µF C6 R. FILTER GND VL 22µF ST C2 Vref1 100µF R. PreIN Vref2 1 2 R1 27 3 R2 470 4 + 5 6 + C4 7 + C5 8 9 10 11 12 13 20 dB C11 MIC. OUT MIC. IN 14 15 16 R9 10kΩ GND 100 µF + – 0.1µF 22µF C3 C8 0.068µF R– OUT (1) 820kΩ R4 C1 2.7kΩ R5 121kΩ J1 Side-tone circuit 0.022µF R3 4.7kΩ JP1 J3 R– OUT (2) 0.001µF R7 47kΩ R10 10kΩ + – 17