AN8018

Voltage Regulators AN8018SA 1.8-volt 2-channel step-up, step-down, or inverting DC-DC converter control IC Unit: mm s Overview The AN8018SA is a two-channel PWM DC-DC converter control IC that features low-voltage operation. This IC can obtain the step-up, step-down and inverting voltages with a small number of external components. The minimum operating voltage is as low as 1.8 V so that it can operate with two dry batteries. In addition, since it uses the 16-pin surface mounting type package with 0.65 mm pitch, it is suitable for miniaturized highly efficient potable power supply. 5.0±0.2 16 9 (1.0) 4.4±0.2 6.4±0.3 0.15 −0.05 +0.10 0° to 10° 0.5±0.2 s Features (0.225) 0.65 0.22 − 0.05 +0.10 0.1±0.1 1.2±0.2 1 8 Seating plane • Wide operating supply voltage range (1.8 V to 14 V) • Incorporating a high precision reference voltage circuit SSOP016-P-0225A (allowance: ± 2%) • Control in a wide output frequency range is possible (20 kHz to 1 MHz). • Built-in wideband error amplifier (single gain bandwidth 10 MHz typical) • Built-in timer latch short-circuit protection circuit (charge current 1.1 µA typical) • Incorporating the under-voltage lock-out circuit (U.V.L.O.) (circuit operation-starting voltage 1.67 V typical) • Dead-time is variable. • Flatness of switching current can be obtained by staggering the turn-on timing of each channel. • Built-in unlatch function When DT1 pin is low level, or DT2 pin is high level, independent turn-off is possible. • Incorporating a on/off control function (active-high control input, standby mode current: 5 µA maximum) • Parallel operation is possible. • Output block • Totem pole 1 output • Output source-current: −50 mA maximum (Constant current output with a less supply voltage fluctuation is possible by connecting an external resistor to pin 11) • Output sink-current: +80 mA maximum • Open-collector 1 output • Output current: 50 mA maximum s Applications • LCD displays, digital still cameras, and PDAs 1 AN8018SA s Block Diagram VREF OSC DT1 VCC Voltage Regulators 9 16 1 On/ 15 off FB1 5 On/off control Reference 1.19 V Triangular wave voltage source oscillation VREF VREF 6 0.9 V 0.2 V 7 PWM1 Out1 Error amp. 1 IN−1 4 IN+1 3 Unlatch1 U.V.L.O. H L Latch R Q S VREF 0.9 V FB2 13 Error amp. 2 14 1.19 V S.C.P. comp. 0.22 V VCC 11 RB2 PWM2 0.9 V Unlatch2 IN+2 10 Out2 0.9 V VREF 8 GND S.C.P. s Pin Descriptions Pin No. Symbol 1 OSC Description Pin for oscillation timing resistor and capacitor connection 2 S.C.P. IN+1 IN−1 FB1 DT1 Out1 Pin for connecting the time constant setting capacitor for short-circuit protection 3 Error amplifier 1 block noninverting input pin 4 5 6 7 Error amplifier 1 block inverting input pin Output pin of error amplifier 1 block PWM1 block dead-time setting pin Out1 block open-collector type output pin 15 16 Off VREF 12 13 14 DT2 FB2 IN+2 Pin No. Symbol 8 9 10 11 GND VCC Out2 RB2 Description Grounding pin Power supply voltage application pin Out2 block push-pull type output pin Out2 block output source current setting resistor connection pin PWM2 block dead-time setting pin Output pin of error amplifier 2 block Error amplifier 2 block inverting input pin On/off control pin Reference voltage output pin 2 DT2 12 2 Voltage Regulators s Absolute Maximum Ratings Parameter Supply voltage Off terminal allowable application voltage IN+1 terminal allowable application voltage IN−1 terminal allowable application voltage IN+2 terminal allowable application voltage Out1 terminal allowable application voltage Supply current Out1 terminal output current Out2 terminal source current Out2 terminal sink current Power dissipation *1 *2 *2 *2 AN8018SA Symbol VCC VOFF VIN−1 VIN−1 VIN+2 VOUT ICC IO ISO(OUT) ISI(OUT) PD Topr Tstg Rating 15 15 6 6 6 15  +50 −50 +80 135 −30 to +85 −55 to +150 Unit V V V V V V mA mA mA mA mW °C °C Operating ambient temperature Storage temperature Note) 1. Do not apply external currents or voltages to any pins not specifically mentioned. For the circuit currents, '+' denotes current flowing into the IC, and '−' denotes current flowing out of the IC. 2. Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C. 3. *1: Ta = 85 °C. For the independent IC without a heat sink. Note that applications must observe the derating curve for the relationship between the IC power consumption and the ambient temperature. *2: VIN−1 , VIN-1 , VIN+2 = VCC when VCC < 6 V. s Recommended Operating Range Parameter Supply voltage Off control terminal application voltage Output source current Output sink current Timing resistance Timing capacitance Oscillation frequency Short-circuit protection time constant setting capacitance Output current setting resistance Symbol VCC VOFF ISO(OUT) ISI(OUT) RT CT fOUT CSCP RB Range 1.8 to 14 0 to 14 −40 (minimum) 70 (maximum) 1 to 51 100 to 10 000 20 to 1 000 1 000 (minimum) 180 to 15 000 Unit V V mA mA kΩ pF kHz pF Ω s Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C Parameter Reference voltage block Reference voltage Input regulation with input fluctuation Load regulation VREF Line Load IREF = − 0.1 mA VCC = 1.8 V to 14 V IREF = − 0.1 mA to −1 mA 1.166  −20 1.19 15 −5 1.214 30  V mV mV 3 Symbol Conditions Min Typ Max Unit AN8018SA Voltage Regulators s Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C (continued) Parameter U.V.L.O. block Circuit operation start voltage Error amplifier 1 block Input offset voltage Common-mode input voltage range Input bias current 1 High-level output voltage 1 Low-level output voltage 1 Output source current 1 Output sink current 1 Error amplifier 2 block Input threshold voltage Input bias current 2 High-level output voltage 2 Low-level output voltage 2 Output source current 2 Output sink current 2 Oscillator block Output off threshold voltage Output 1 block Oscillation frequency 1 Output duty ratio 1 Output saturation voltage Output leak current Output 2 block Oscillation frequency 2 Output duty ratio 2 High-level output voltage Low-level output voltage Output source current Output sink current Pull-down resistance PWM1 block Output full-off input threshold voltage 1 Output full-on input threshold voltage 1 Input current 1 4 VT0-1 VT100-1 IDT1 Duty = 0% Duty = 100% VDT1 = 0.4 V  0.65 −1.1 0.28 0.72 − 0.5 0.30   V V µA fOUT2 Du2 VOH VOL IO = −10 mA, RB = 820 Ω IO = 10 mA, RB = 820 Ω VO = 0.7 V, RB = 820 Ω RT = 12 kΩ, CT = 330 pF 185 72 1.4  −40 20 20 205 77   −30  30 225 82  0.2 −20  40 kHz % V V mA mA kΩ fOUT1 Du1 VO(SAT) IOLE IO = 30 mA VCC = 14 V RT = 12 kΩ, CT = 330 pF 185 75   205 80   225 85 0.5 1 kHz % V µA VTH(OSC) 0.8 0.9 1.0 V VTH IB2 VEH2 VEL2 ISO(FB)2 ISI(FB)2 1.16  0.83  −61 33 1.19 0.2 0.93  −47 47 1.22 0.8 1.03 0.2 −33 61 V µA V V µA µA VIO VICR IB1 VEH1 VEL1 ISO(FB)1 ISI(FB)1 −6 0.3 − 0.6 0.83  −61 33   − 0.2 0.93  −47 47 +6 0.7  1.03 0.2 −33 61 mV V µA V V µA µA VUON 1.59 1.67 1.75 V Symbol Conditions Min Typ Max Unit ISO(OUT) VO = 0.7 V, RB = 820 Ω ISI(OUT) RO Voltage Regulators s Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C (continued) Parameter PWM2 block Output full-off input threshold voltage 2 Output full-on input threshold voltage 2 Input current 2 Unlatch circuit 1 block Input threshold voltage 1 Unlatch circuit 2 block Input threshold voltage 2 Short-circuit protection circuit block Input standby voltage Input threshold voltage 1 Input threshold voltage 2 Input latch voltage Charge current On/off control block Input threshold voltage Whole device Output off consumption current Latch mode consumption current Standby current • Design reference data Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. AN8018SA Symbol Conditions Duty = 0% Duty = 100% VDT2 = 0 V Min Typ Max  0.30  Unit VT0-2 VT100-2 IDT2 0.65  −1.1 0.72 0.28 − 0.5 V V µA VTHUL1 0.15 0.20 0.25 V VTHUL2 0.8  0.8 0.17  VSCP = 0 V −1.43 0.9 1.0 V VSTBY VTHPC1 VTHPC2 VIN ICHG 60 0.9 0.22 60 120 1.0 0.27 120 mV V V mV µA −1.1 − 0.77 VON(TH) RB = 820 Ω, duty = 0% RB = 820 Ω 0.8    1.0 1.3 V ICC(OFF) ICC(LA) ICC(SB) 5.7 5.6  8.0 7.8 1 mA mA µA Parameter Reference voltage block VREF temperature characteristics Over-current protection drive current U.V.L.O. block Reset voltage Error amplifier 1/2 blocks VTH temperature characteristics Open-loop gain Single gain bandwidth Output 1/2 blocks Frequency supply voltage characteristics Frequency temperature characteristics Symbol Conditions Ta = −30°C to +85°C Min −1   Typ  −11 Max +1   Unit VREFdT IOC % mA VR Ta = −30°C to +85°C 0.8  57 10   V VTHdT AV fBW fdV fdT − 0.3   −1 −3 + 0.3 mV/°C   +1 +3 dB MHz % % 5 AN8018SA Voltage Regulators s Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 µF, Ta = 25°C (continued) • Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Output 2 block RB terminal voltage Short-circuit protection block Comparator threshold voltage On/off control block Off terminal current Symbol Conditions Min    Typ Max    Unit VB 0.36 V VTHL 1.19 V µA IOFF 23 s Terminal Equivalent Circuits Pin No. 1 Equivalent circuit Description OSC: The terminal used for connecting a timing capacitor/resistor to set oscillation frequency. Use a capacitance value within the range of 100 pF to 10 000 pF and a resistance value within the range of 3 kΩ to 30 kΩ. Use an oscillation frequency in the range of 20 kHz to 1 MHz. When operating the circuit in parallel and synchronously, the channel 2 output stops when this pin becomes 0.9 V or more. (Refer to the "Application Notes, [7]" section.) S.C.P.: The terminal for connecting a capacitor to set the time constant of the timer latch short-circuit protection circuit. Use a capacitance value in the range of 1 000 pF or more. The charge current ICHG is 1.1 µA typical. IN+1: The noninverting input pin for error amplifier 1 block. IN−1: The inverting input pin for error amplifier 1 block. I/O O VCC Latch 0.2 V 1 S R Q 2 VCC 1.1 µA 2 kΩ Latch O S R 1.19 V 2 Q Output cut-off 3 VCC I 4 4 100 Ω 100 Ω 3 I 5 47 µA IN+1 IN−1 OSC 47 µA 5 PWM FB1: The output pin for error amplifier 1 block. The source current is −47 µA and the sink current is 47 µA. Correct the frequency characteristics of the gain and the phase by connecting a resistor and a capacitor between this terminal and GND. O 6 Voltage Regulators s Terminal Equivalent Circuits (continued) Pin No. 6 Equivalent circuit Description AN8018SA I/O I VCC FB1 OSC PWM 0.2 V 6 7 DT1: The pin for setting channel 1 output maximum duty ratio. If this terminal is set at a voltage of 0.20 V or less, FB1 terminal becomes low-level voltage and the protective function for channel 1 output shortcircuit will stop (Unlatch function). Out1: The pin is open-collector type output terminal. The absolute maximum rating of output current is +50 mA. VCC 7 O 8 8 GND: Grounding terminal VCC: 9 The supply voltage application terminal Use the operating supply voltage in the range of 1.8 V to 14 V. VCC RB2 ISO(OUT) 10 30 kΩ Out2: The pin is push-pull type output terminal. The absolute maximum rating of output source current is −50 mA. The absolute maximum rating of output sink current is +80 mA. A constant current output with less fluctuation with power supply voltage and dispersion can be obtained by the resistor externally attached to RB2 pin. VRB2 ISO(OUT)2 = 68 × [A] RB2 RB2: The pin for connecting a resistor for setting channel 2 output current. Use a resistance value in the range of 180 Ω to 1.1 kΩ. The terminal voltage is 0.36 V (at RB2 = 820 Ω).  9  10 O 11 VCC I Out2 120 Ω 11 7 AN8018SA s Terminal Equivalent Circuits (continued) Pin No. 12 Equivalent circuit VCC 0.9 V FB2 OSC PWM Description Voltage Regulators I/O I 0.9 V 13 12 DT2: The pin for setting channel 2 output maximum duty ratio. If this terminal is set at a voltage of 0.9 V or more, FB2 terminal becomes high-level voltage and the protective function for channel 2 output shortcircuit will stop (Unlatch function). FB2: The output pin for error amplifier 2 block. The source current is −47 µA and the sink current is 47 µA. Correct the frequency characteristics of the gain and the phase by connecting a resistor and a capacitor between this terminal and GND. IN+2: The noninverting input pin for error amplifier 2 block. O VCC IN+2 1.19 V 47 µA OSC 47 µA 13 PWM 14 VCC I 14 100 Ω 1.19 V 15 15 30 kΩ 60 kΩ Internal circuit start/stop Off: The terminal for on/off control. High-level input: Normal operation (VOFF > 1.3 V) Low-level input: Standby state (VOFF < 0.8 V) The total current consumption in the standby state can be suppressed to a value 1 mA or less. VREF: The output terminal for the internal reference voltage. The reference voltage is 1.19 V (allowance: ± 2%) at VCC = 2.4 V and IREF = − 0.1 mA. Connect a capacitor of 0.01 µF or more between VREF and GND for phase compensation. I 16 O VCC 16 8 Voltage Regulators s Usage Notes AN8018SA [1] The loss P of this IC increases in proportion to the supply voltage. Use the IC so as not to exceed the allowable power dissipation of package PD . Reference formula: P = VO(SAT)1 × IOUT1 × Du1 + (VCC − VBEQ2) × ISO(OUT) × Du2 + VCC × ICC < PD VO(SAT)1 : Out1 terminal saturation voltage (0.5 V maximum at IOUT1 = 30 mA) IOUT1 : Out1 terminal output current (= {VCC − VBEQ1− VO(SAT)1} / RO1) Du1 : Output1 duty ratio VBEQ2 : Base-emitter voltage of NPN transistor Q2 ISO(OUT) : Out2 terminal output source current (set by RB, ISO(OUT) = 40 mA maximum at RB2 = 820 Ω) Du2 : Output2 duty ratio ICC : VCC terminal current (8.0 mA maximum but at VCC = 2.4 V) [2] Since the output 2 of the AN8018SA is assuming the bipolar transistor driving, it is necessary to pay attention to the following points when directly driving n-channel MOSFET. 1. Select an n-channel MOSFET having a low input capacitance The AN8018SA is of the constant-current (50 mA maximum) output source-current type circuit assuming the bipolar transistor driving. Also, its sink current capability is around 80 mA maximum. For those reason, it is necessary to pay attention to the increase of loss due to the extension of the output rise time and the output fall time. If any problem arises, there is a method to solve it by amplifying with inverters as shown in figure 1. 2. Select an n-channel MOSFET having a low gate threshold value The output high-level voltage of Out2 pin of the AN8018SA is VCC −1.0 V minimum, so that it is necessary to select a low VT MOSFET having a sufficiently low on-state resistance in accordance with the using operating supply voltage. If a larger VGS is desired, there is a method to apply the double-voltage of the input to the IC's VCC pin by using the transformer as shown in figure 2. VIN 10 Out2 SBD VOUT Figure 1. Output boost circuit example VIN SBD VOUT VCC 9 10 Out2 SBD VCC ≈ 2 × VIN − VD Figure 2. Gate drive voltage increasing method [3] In order to realize a low noise and high efficiency, a care should be taken in the following points in designing the board layout. 1. The wiring for ground line should be taken as wide as possible and grounded separately from the power system. 2. The input filter capacitor should be arranged in a place as close to VCC and GND pin as possible so as not to allow switching noise to enter into the IC inside. 3. The wiring between the Out terminal and switching device (transistor or MOSFET) should be as short as possible to obtain a clean switching waveform. 4. In wiring the detection resistor of the output voltage, the wiring for the low impedance side should be longer. [4] There is a case in which this IC does not start charging to the S.C.P. capacitor when the output is short-circuited due to the malfunction of U.V.L.O. circuit biased by VCC that has ripples generated by turning on and off of the switching transistor. The allowable range of the VCC ripple is as shown in the following figure. Reduce the VCC ripple by inserting a capacitor near the VCC terminal and GND terminal of this IC so that the VCC ripple is in this allowable range. However, this allowable range is design reference value and not the guaranteed value. 9 AN8018SA s Usage Notes (continued) [4] (continued) 100 Voltage Regulators VCC ripple allowable range VCC ripple frequency (MHz) 10 2 1 0.5 Recommended operating range 0.1 0 0.3 0.5 1 1.5 s Application Notes [1] PD  Ta curves of SSOP016-P-0225A 700 VCC ripple width (V[p-p]) PD  T a 600 582 Glass epoxy board (50 × 50 × t0.8 mm3) Rth(j−a) = 171.8°C/W Power dissipation PD (mW) 500 400 338 300 233 200 135 100 Independent IC without a heat sink Rth( j−a) = 295.6°C/W 0 0 25 50 75 85 100 125 [2] Main characteristics VREF temperature characteristics 1.195 Ambient temperature Ta (°C) Frequency characteristics 1M CT = 100 pF CT = 330 pF 1.190 fOUT (Hz) VREF (V) 100k CT = 0.01 µF 1.185 −30 −10 10k 10 30 50 70 90 1k 10k 100k Ta (°C) RT (Ω) 10 Voltage Regulators s Application Notes (continued) [2] Main characteristics ISO(OUT)  RB 70 60 50 60 90 80 VCC = 2.4 V VCC = 14 V 70 VCC = 14 V VCC = 2.4 V 50 40 30 20 10 10 0 100 VCC = 1.8 V VCC = 7 V AN8018SA ISI(OUT)  RB ISO(OUT) (mA) 40 30 VCC = 1.8 V 20 VCC = 7 V 0 100 1k 10k 100k ISI(OUT) (mA) 1k 10k 100k RB (Ω) RB (Ω) Du1  VDT1 100 90 80 70 100 90 80 70 Du2  VDT2 Du1 (%) 50 40 30 20 10 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Du2 (%) 60 60 50 40 30 20 10 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VDT1 (V) VDT2 (V) ICC(OFF)  VCC 8 7 6 8 12 ICC(OFF)  RB 10 ICC(OFF) (mA) ICC(OFF) (mA) 0 2 4 6 8 10 12 14 5 4 3 2 6 4 2 1 0 0 100 1k 10k VCC (V) RB (Ω) 11 AN8018SA s Application Notes (continued) [3] Timing chart (inside waveform) Voltage Regulators VCC terminal voltage waveform 1.6 V 1.22 V Output short-circuit S.C.P. terminal voltage waveform FB1 Channel 1 OSC DT1 Out1 terminal voltage waveform Open-collector output Channel 2 FB2 Out 2 terminal voltage waveform Totem pole output OSC DT2 12 Voltage Regulators s Application Notes (continued) [4] Function descriptions AN8018SA 1. Reference voltage block This block is composed of the band gap circuit, and outputs the temperature compensated 1.19 V reference voltage. The reference voltage is stabilized when the supply voltage is 1.8 V or more. The reference voltage is also used as the reference voltage for the error amplifier 2 block. 2. Triangular wave oscillation block The sawtooth-waveform-like triangular wave having VOSCH ≈ 0.7 V a peak of approximately 0.7 V and a trough of approximately 0.2 V can be generated by connecting the timing capacitor CT and resistor RT to the OSC terminal (pin 1). The oscillation frequency can be freely set by the value of VOSCL ≈ 0.2 V CT and RT to be connected externally. The usable oscillation frequency is from 20 kHz to the maximum 1 MHz. t1 t2 The triangular wave is connected with the inverting input Boosting Discharging of PWM comparator for channel 1 side and the charge noninverting input of PWM comparator for channel 2 side T within the IC inside. Rough calculation of oscillation freFigure 1. Triangular wave oscillation waveform quency can be calculated by the following equation. 1 1 fOSC ≈ − ≈ 0.8 × [Hz] CT × RT × ln VOSCL CT × RT VOSCH However, boosting charge time, over-shoot and under shoot quantities are not considered in the above equation. And refer to the experimentally determined graph of the frequency characteristics provided in the main characteristics section. 3. Error amplifier 1 block The output voltage of DC-DC converter is detected by the PNP-transistor-input type error-amplifier and the amplified signal is input to the PWM comparator. Also, it is possible to perform the gain setting and the phase compensation arbitrarily by connecting a resistor and a capacitor from the FB1 terminal (pin 5) to GND in series. The output voltage VOUT1 can be set by making connection as shown in figure 2. Case of step-up output FB2 5 VREF VOUT1 R1 R3 IN+1 3 IN−1 4 Error amplifier 1 block VREF R1 R3 Error amplifier 1 block To PWM comparator input R1 + R2 + VREF R1 Case of inverting output FB2 5 IN+1 3 IN−1 4 R2 R4 To PWM comparator input R2 R4 VOUT1 = R3 + R4 R2 · · VREF R4 R1 + R2 VOUT1 VOUT1 = − (VREF − VIN−1) · VIN−1 = VREF · R4 R3 + R4 Figure 2. Connection method of error amplifier 1 block 4. Error amplifier 2 block The output voltage of DC-DC converter is detected by the NPN-transistor-input type error-amplifier and the amplified signal is input to the PWM comparator. The internal reference voltage 1.19 V is given to the noninverting input. 13 AN8018SA s Application Notes (continued) [4] Function descriptions (continued) 4. Error amplifier 2 block (continued) Also, it is possible to perform the gain setting and the phase compensation arbitrarily by connecting a resistor and a capacitor from the FB2 terminal (pin 13) to GND in series. The output voltage VOUT2 can be set by making connection as shown in figure 3. VOUT2 R1 R2 IN+2 FB2 13 Voltage Regulators Error amplifier 2 block 14 1.19 V VOUT2 = 1.19 × R1 + R2 R2 To PWM comparator input Figure 3. Connection method of error amplifier 2 block (step-up output) 5. Timer latch short-circuit protection circuit This circuit protects the external main switching devices, flywheel diodes, and choke coils, etc. from destruction or deterioration if overload or short-circuit condition of power supply output lasts for a certain time. The timer latch short-circuit protection circuit detects the output level of the error amplifier. When the output voltage of DC-DC converter drops and the FB1 terminal (pin 5) becomes 0.9 V or more, or the FB2 terminal (pin 13) becomes 0.22 V or less, the low-level output is given and the timer circuit is actuated to start the charge of the external protection-enable capacitor. If the output of the error amplifier does not return to a normal voltage range by the time when the voltage of this capacitor reaches 1.19 V, it sets the latch circuit, and cuts off the output drive transistor, and sets the dead-time to 100%. 6. Low input voltage malfunction prevention circuit (U.V.L.O.) This circuit protects the system from destruction or deterioration due to control malfunction when the supply voltage is low in the transient state of power on/off. The low input voltage malfunction prevention circuit detects the internal reference voltage which changes according to the supply voltage level. Until the supply voltage reaches 1.67 V during its rise time, it cuts off the output drive transistor, and sets the dead-time to 100%. At the same time, it holds the S.C.P. terminal (pin 2) and DT1 terminal (pin 6) to low-level, and the OSC terminal (pin 1) and DT2 terminal (pin 12) to high-level. 7. PWM comparator block The PWM comparator controls the on-period of the output pulse according to the input voltage. The PWM1 and PWM2 block are set in an opposite logic relation of each other and on-period of each output is staggered. The PWM1 block turns on the output transistor during the period when the triangular wave of OSC terminal (pin 1) is lower than any lower one of the FB1 (pin 5) terminal voltage and the DT1 (pin 6) terminal voltage. The PWM2 block turns on the output transistor during the period when the triangular wave of OSC terminal (pin 1) is higher than any higher one of the FB2 (pin 13) terminal voltage and the DT2 (pin 12) terminal voltage. The maximum duty ratio is variable from the outside. Also, the soft start which gradually extends on-period of the output pulse is activated by connecting a capacitor in parallel with the resistor-dividing for the maximum duty ratio setting. 8. Unlatch block The unlatch circuit 1 block fixes the FB1 terminal (pin 5) at low level at the DT1 terminal (pin 6) is 0.20 V or less. The unlatch circuit 2 block fixes the FB2 terminal (pin 13) at high-level at the DT2 terminal (pin 12) is 0.9 V or more. Consequently, by controlling the DT1 and the DT2 terminal voltages, it is possible to operate only one channel or to start and stop each channel in any required sequence. 9. Output 1 block This output circuit is open-collector type. The available output current is up to 50 mA. The breakdown voltage of output terminal is 15 V. 10. Output 2 block This block uses a totem pole type output circuit. By connecting the current setting resistor to the RB2 terminal, it is possible to arbitrarily set a constant-current source-output having a small fluctuation with the supply voltage. The available constant-current source-output is up to 50 mA. 14 Voltage Regulators s Application Notes (continued) AN8018SA [5] About logic of PWM block The logic for channel 1 and channel 2 of this IC is reversed. Thereby an input current flatness is realized. At the same time, noise can be suppressed to a lower level by staggering the turn on timing. The PWM1 block turns on the output transistor during the period when the triangular wave of the OSC terminal (pin 1) is lower than both of the FB1 (pin 5) terminal voltage and the DT1 (pin 6) terminal voltage. The PWM2 block turns on the output transistor during the period when the triangular wave of OSC terminal (pin 1) is higher than both of the FB2 (pin 13) terminal voltage and the DT2 (pin 12) terminal voltage. (Refer to figure 4.) OSC FB1 FB2 DT1 and DT2 are omitted Out1 (Open-collector output) Out2 (Totem pole output) Channel 1 Switching transistor emitter current IE1 Channel 2 Switching transistor collector current IC2 IE1 + IC2 SBD VIN 10 Out2 + IC2 IE1 SBD − Out1 7 Figure 4. PWM logic explanation chart 15 AN8018SA s Application Notes (continued) Voltage Regulators [6] Time constant setting method for timer latch short-circuit protection circuit The constructional block diagram of protection latch circuit is shown in figure 6. The comparator for short-circuit protection compares the error amplifier 1 output FB1 with the reference voltage of 0.9 V for channel 1 side, and the error amplifier 2 output FB2 with the reference voltage of 0.22 V for channel 2 side at all the time. When the load conditions of DC-DC converter output is stabilized, there is no fluctuation of error amplifier output and the short-circuit protection comparator also keeps the balance. At this moment, the output transistor Q1 is in the conductive state and the S.C.P. terminal is held to approximately 60 mV. When the load conditions for channel 1 side suddenly change and high-level signal (0.9 V or more) is input from the error amplifier 1 block to the short-circuit protection comparator, the short-circuit protection comparator outputs the low-level signal to cut off the output transistor Q1. Also, when the load conditions for channel 2 side suddenly change and low-level signal (0.22 V or less) is inputted from the error amplifier 2 block to the short-circuit protection comparator, the short-circuit protection comparator outputs the low-level signal to cut off the output transistor Q1. The capacitor CSCP connected to the S.C.P. terminal starts charging. When the external capacitor CSCP has been charged to approximately 1.19 V with the constant current of approximately 1.1 µA, the latch circuit is set, the output terminal is fixed to low level, and the dead-time is set to 100%. Once the latch circuit is set, the S.C.P. terminal is discharged to approximately 40 mV, However, the latch circuit is not reset unless the power for the latch circuit is turned off or restarted by the on/off control. tPE VSCP [V] 1.19 V = ICHG × CSCP ∴ tPE [s] = 1.08 × CSCP When the power supply is turned on, the output is considered to be short-circuited state so that the S.C.P. terminal voltage starts charging. It is necessary to set the external capacitor so as to start up the DC-DC converter output voltage before setting the latch circuit in the later stage. Especially, pay attention to the delay of the start-up time when applying the soft-start. 1.19 Short-circuit detection time tPE 0.06 t [s] Figure 5. S.C.P. terminal charging waveform FB1 5 IN+1 3 IN−1 4 FB2 13 IN+2 14 On/off control U.V.L.O. Error amp.1 1.1 µA 0.9 V Error amp.2 1.19 V 0.22 V S.C.P. comp. Q1 Latch R Q S Internal reference Output cut-off High-level detection comp. 1.19 V Figure 6. Short-circuit protection circuit 16 S.C.P. 2 Voltage Regulators s Application Notes (continued) AN8018SA [7] Parallel synchronous operation of multiple ICs Multiple instances of this IC can be operated in parallel. If the OSC terminals (pin 1) and Off terminals (pin 15) are connected to each other as shown in figure 7, the ICs will operate at the same frequency. It is possible to operate this IC (the AN8018SA) with the two-channel totem pole output IC AN8017SA in parallel synchronous mode. 1. Usage notes 1) The parallel synchronous operation with the single-channel AN8016SH/AN8016NSH is not possible. 2) The remote on/off with the single IC itself is not possible. Only the simultaneous remote on/off of all ICs is possible. H L Input 16 VREF IN+2 11 RB2 Out2 7 10 Out2 Out1 7 Out1 10 DT2 13 FB2 15 Off 9 VCC GND 8 9 VCC GND 8 14 Off terminals connected together OSC 1 S.C.P. 2 3 4 FB1 5 6 DT1 6 11 RB2 DT1 IN+1 0.1 µF 16 VREF 14 IN+2 12 DT2 FB1 5 15 Off FB2 OSC terminals connected together OSC 1 S.C.P. 2 IN+1 3 IN−1 4 Figure 7. Slave operation circuit example 13 IN−1 12 17 AN8018SA s Application Notes (continued) [7] Parallel synchronous operation of multiple ICs (continued) Voltage Regulators 2. About the operation of short-circuit protection at parallel synchronous operation In the case of the operation in parallel, if the single output (or multiple outputs) of them is short-circuited and the timer latch short circuit protection of the IC is operated, the output of other ICs will be also shut down, then enter into latch mode. In figure 8, if the IC-2 entered timer latch mode, Q1 turns on and the OSC terminal (pin 1) is fixed to approximately 1.1 V and the oscillator stops. Then channel 1 of IC-1 becomes low level than the DT1 terminal (pin 6) voltage or high-level voltage (0.9 V) of the FB1 terminal set by terminal voltage, and then output 2 stops by PWM1 circuit of inside. The channel 2 stops output 2 by oscillator high-level detection comparator. And then, the IC-1 becomes short-circuit state and enters latch mode after a certain time. It becomes the same operation in case of the IC-1 enters latch mode previously. 16 IC-1 0.9 V Channel 2 goes off at high Oscillator high-level detection comparator 16 1 IC-2 Q1 1 The IC entering to the lach mode, Q1 turns on and, VOSC = VREF − VCE(sat) = becomes approximately 1.1 V IC-2 side output short-circuited IC-2 latch 1.19 V IC-1 latch S.C.P. OSC DT1 FB1 Since the OSC terminal voltage becomes higher than the DT1 terminal voltage, the Out1 becomes fully off state. Out1 OSC FB2 DT2 Forced to be in off state inside the IC Out2 1.19 V S.C.P. Figure 8. Operation of short-circuit protection at parallel synchronous operation 18 Voltage Regulators s Application Notes (continued) [8] Setting of Off-terminal connection resistor The start circuit starts its operation when Q1 is turned on. In case of the resistor ROFF is connected externally as shown in figure 9, the input voltage VCTL at which the start circuit operates is obtained by the equation: VCTL > VBEQ1 × (ROFF + R1 + R2) / R2 Therefore, ROFF can be set by: ROFF < R2 · VCTL / VBEQ1 − R1 − R2 Set the value of ROFF according to above equations. (Typical value) ROFF < 25 kΩ including temperature characteristics and sample to sample variations at VCTL = 3 V. CTL ROFF Off 15 R1 30 kΩ R2 60 kΩ AN8018SA Start circuit Q1 Figure 9. Off terminal peripheral circuit [9] Sequential operation In the case of sequential operation is necessary for each channel at IC operation, it is possible to turn on/off the output of DC-DC converter individually by turning on/off Q1 and Q2 as shown in figure 10. In the channel 1 side, if Q1 turns on and the DT1 terminal (pin 6) becomes 0.2 V or less, the output transistor turns off due to lower voltage than the OSC terminal (pin 1). Simultaneously, unlatch circuit 1 block operates, and the timer latch short-circuit protection does not operate because the FB1 terminal (pin 5) becomes fixed to low even if output of channel 1 downs. In the channel 2 side, if Q1 turns on and the DT2 terminal (pin 12) becomes 0.9 V or more, the output transistor turns off due to higher voltage than the OSC terminal (pin 1). Simultaneously, unlatch circuit 2 block operates, and the timer latch short-circuit protection does not operate because the FB2 terminal (pin 13) becomes fixed to high even if output of channel 2 downs. Q2 16 VREF 10 Out2 Out1 7 11 RB2 12 DT2 13 FB2 9 VCC GND 8 Unlatch2 0.9 V 0.9 V Unlatch1 0.2 V FB1 5 DT1 6 1.19 V V2 Control block V1 Q1 Figure 10 19 AN8018SA s Application Notes (continued) [9] About sequential operation (continued) V1 V2 DT1 Out1 DT2 Voltage Regulators Out2 Out1 operation Out2 operation Operation when each channel single on/off [10] Error amplifier phase-compensation setting method The equivalent circuit of error amplifier is as shown in figure 11. The transfer function is: 1 / {S (CE1 + CO1)} 1 = RE1 + 1 / {S (CE1 + CO1)} SCO1 · RE1 + 1 (from CE1