MN101DF08G

MN101D08E Type Internal ROM type ROM (byte) RAM (byte) Package (Lead-free) MN101D08E Mask ROM 80K 2K MN101DF08G FLASH 128K 4K Minimum Instruction Execution Time LQFP080-P-1414A [With main clock operated] 0.1397 µs (at 4.0 V to 5.5 V, 14.32 MHz) 0.1397 µs (at 4.0 V to 5.5 V, 14.32 MHz) 71.5 µs (at 2.7 V to 5.5 V, 14.32 MHz internal 71.5 µs (at 2.7 V to 5.5 V, 14.32 MHz internal frequency di Vision) frequency di Vision) 61 µs (at 2.5 V to 5.5 V, 32.768 kHz) [When sub-clock operated] 61 µs (at 2.5 V to 5.5 V, 32.768 kHz)  Interrupts RESET, Runaway, External 0 to 4, Timer 0 to 3, Timer 6, Capstan FG, Control, HSW, Cylinder(Drum) FG, Servo V-sync, Synchronous output, OSD, XDS, Serial 1, Serial 2, PWM 4, OSD V-sync Timer counter 0 : 8-bit × 1 (timer function) Clock source................ 1/4, 1/16 of system clock frequency Interrupt source ........... overflow of timer counter 0 Timer counter 1 : 8-bit × 1 (timer function, linear timer counter function) Clock source................ 1/4 of system clock frequency; CTL signal Interrupt source ........... overflow of timer counter 1 Timer counter 2 : 16-bit × 1 (timer function, input capture (CTL specified edge), duty judgment of CTL signal) Clock source................ 1/4, 1/16, 1/24 of system clock frequency Interrupt source ........... overflow of timer counter 2; input of CTL specified edge; underflow of timer 2 shift register 4-bit counter; coincidence of timer 2 shift register with timer 2 shift register compare register Timer counter 3 : 16-bit × 1 (timer function) Clock source................ 1/4, 1/16 of system clock frequency Interrupt source ........... overflow of timer counter 3 Timer counter 5 : 19-bit × 1 (watchdog, stable oscillation waiting function) Clock source................ system clock Watchdog interrupt source ... 1/216, 1/219 of timer counter 5 frequency Clear by stable oscillation ... after 256 counts by timer counter 5 (218 counts of OSC oscillation clock) Timer counter 6 : 16-bit × 1 (clock function [max. 2 s]) Clock source................ 1/512 of OSC oscillation clock frequency; XI oscillation clock; 1/8, 1/128 of system clock frequency Interrupt source ........... 1/213, 1/214, 1/215 overflow of timer counter 6  Timer Counter  Serial interface Serial 1 : 8-bit × 1 (synchronous type) (transfer direction of MSB/LSB selectable, start condition function) Clock source................ 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency; NSBT1 pin input Serial 2 : 8-bit × 1 (I²C) (master transmission/reception, slave transmission/reception) Clock source................ 1/144 to 1/252 of system clock; SCK pin input MAD00032EEM MN101D08E  OSD Display mode ........................... Menu(Internal synchronized ) display, super impose(external synchronized) display Applicable broadcasting system.... NTSC, PAL, PAL-M, PAL-N Screen configuration ................ 24 characters × 2n rows (n = 1 to 6) Character type .......................... max. 128 character types (variable, include special characters) Character size ........................... 12 × 18 dots (Vertical direction : 1 dot for 2H at not enlargement.) Enlarged characters .................. each × 2 settings in horizontal and vertical Character interpolation............. none Line background color ............. 8-hue settable (settable in the row unit at menu display) Line background intensity........ 8 gradations settable in the row unit Screen background color.......... 8-hue settable at menu display Character color ......................... white Character intensity ................... 8 gradations settable in the row unit Frame function ......................... 1-dot frame in 4 directions Frame intensity......................... 4 gradations settable in the row unit Blinking.................................... none (covered by software) Inverted character..................... settable in the character unit Halftone.................................... none Input ......................................... composite video signal input (output level : 1 V[p-p] / 2 V[p-p]) Clamp method .......................... sync tip clamp, clamp level in 4 levels Output ...................................... composite video output Measure against image fluctuation...... built-in AFC circuit Dot clock .................................. 1/2 of OSC oscillation clock (automatic phase adjustment)  I/O Pins I/O Input 56 1 Common use : 45 Common use : 1  A/D converter  PWM 8-bit × 11-ch. (without S/H) 13-bit × 2-ch. (at repetition cycle 572 ms at 14.32 MHz), 8-bit × 1-ch. (at repetition cycle 71.5 ms, 0.572 ms, 1.14 ms, 2.29 ms at 14.32 MHz) 16-bit × 2-ch.(Speed system), 18-bit × 4-ch.(Phase system) 16-bit × 3 (Synchronous output × 2, Rec CTL × 1 ) 3-state output (PTO) VLP pin; CTL input; Capstan FG input; Cylinder(Drum) PG/FG inputs; HSW output; Head amp/ Rotary control outputs; output of 1/4 OSC oscillation clock (1 V[p-p]) Correcting address designation : up to 3 addresses possible Correction method : correction program being saved in internal RAM  ICR  OCR  Special Ports  ROM Correction MAD00032EEM  Electrical Charactreistics (Supply current) Parameter Symbol IDD1 Operating supply current Supply current at STOP Supply current at HALT IDD2 IDD3 IDSP IDHT0 IDHT1 Condition 14.32 MHz operation without load, VDD = 5 V 1/1024 of 14.32 MHz operation without load, VDD = 2.7 V Stop of 14.32 MHz oscillation, VDD = 2.7 V 32 kHz oscillation operation without load Stop of oscillation without load, VDD = 5 V 14.32 MHz oscillation without load, VDD = 5 V Stop of 14.32 MHz oscillation, VDD = 2.7 V 32 kHz oscillation operation without load Limit min typ 50 2 50 5 5 max 100 5 100 10 15 20 Unit mA mA µA µA mA µA (Ta = 25°C±2°C , VSS = 0 V)  Electrical Charactreistics (A/D converter characteristics) Parameter Conversion relative error A/D Conversion Time Analog Input Voltage Symbol ∆NLAD tAD fosc = 14.32 MHz 8 5 Condition Limit min typ max ±3 Unit LSB µs V (Ta = 25°C±2°C , VDD = 5.0 V , VSS = 0 V)  Development tools In-circuit Emulator PX-ICE101C/D + PX-PRB101D08-LQFP080-P-1414A  Pin Assignment AD9(↔PC1) AD10(↔PC2) C0 RCTLN RCTLP AVDD CTLA AVSS VRI VR0 AFG FGF YPG(↔PB7) YFG(PFG) FSCLPF(↔PB0) FSCI(↔PB1) AFCLPF(↔PB2) AFCC(↔PB3) VDD2 CVIN2(↔PB4) (↔PC0)AD8 (↔P87)AD7 (↔P86)AD6 (↔P85)AD5 (↔P84)AD4 (↔P83)AD3 (↔P82)AD2 (↔P81)AD1 (↔P80)AD0 P77 P76 P75 P74 P73 P72 P71 P70 (↔P67)ROTA (↔P66)HAMP (↔P65)DENV 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 MN101D08E (P64→)IRQ0 (P63↔)IRQ1 (P62↔)IRQ2 (P61↔)IRQ3 (P60↔)IRQ4 (P07↔)NSBT1 (P06↔)NSBI1 (P05↔)NSB01 P02 P01 P00 (P27↔)SDA (P26↔)SCK (P46↔)HBUFD6 (P44↔)HBUFD4 (P42↔)HBUFD2 (P40↔)HBUFD0 HSW VLP (P04←)NRST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CVIN (PB5↔) VSS2 CVOUT (PB6↔) SXI X0 (P23↔) XI (P24↔) VSS OSCI OSC0 VDD PWM4(P25↔) PWM0 PWM1 SBUFD1(P11↔) SBUFD2(P12↔) SBUFD3(P13↔) SBUFD4(TC60, P14↔) SBUFD5(P15↔) SBUFD6(P16↔) SBUFD7(OSCDIV, P17↔) LQFP080-P-1414A MAD00032EEM Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. 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