MN195001

For Communications Equipment MN195001 Single-Chip Fax Engine LSI Overview The MN195001 reduces to a single chip CPU functions related to facsimile control, peripheral device control functions, and modem functions. The last include complete fax/modem support for the ITU-T G3 recommandations V.29, V.27ter, and V.21 Channels 1 and 2. The MN195001 consists of the following blocks: digital signal processor (DSP), facsimile peripheral circuits, analog circuits, DTE interface, clock generator, and dualport RAM. Changing the contents of an external ROM tailors the chip for a wide variety of facsimile applications. Features Digital signal processor (DSP) block • Micro ROM: 4096 × 32 bits • Data RAM: 512 × 16 bits × 2 sets • Machine cycle: 90 ns • Parallel multiplier: 16 bits × 16 bits × → 32 bits • Arithmetic and logic unit (ALU): 32-bit Facsimile peripheral circuit block • Scanner/plotter interface • Two USART channels • Two motor control channels • One thermal head control channel • Programmable chip select Analog circuit block • Built-in 8-bit D/A converter, A/D converter, and filters DTE interface block • Built-in 8-bit I/O interface and serial interface Clock generator block • Sampling clock and baud rate clock generators Dual-port RAM block • 1024 × 8 bits Single 5 volt power supply Applications Facsimile equipment MN195001 Pin Assignment For Communications Equipment VIR VSEN UC0 UC1 UC2 UC3 A23 A22 A21 A20 A19 A18 A17 A16 A15 DVSS3 DVDD3 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSDA VSCK V8CK MOT MTA1 MTA2 MTA3 MTA4 VPDA VPCK VPST SH1 SH2 SH3 SH4 MTB1 MTB2 MTB3 MTB4 DVDD2 DVSS2 U2TCK U2SD U2RCK U2RD U2ST IRQ4 IRQ3 IRQ2 IRQ1 U1TCK U1SD U1RCK U1RD U1ST S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 MOD3 MOD2 MOD1 MOD0 VREFL VREFH AVDD IREF0 IREF1 TXLPIN AVSS TXOUT HVDD MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 SYNCA SCX2 CX HDRES DVDD1 DVSS1 WR RD RNW BA HALT EQMD ADCK EYCY PLSD DVSS4 DVDD4 SHIN AGCOUT AGCIN HPOUT RXLPIN IREF2 RXL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 QFH128-P-1818 For Communications Equipment Block Diagram MN195001 AVDD VREFH VREFL IREF2 to 0 TXLPIN TXOUT RXLPIN RXL HPOUT AGCIN AGCOUT SHIN HVDD 39 35 AVSS Analog front-end processor (AFP) Clock generator DTE I/F CX 11 SCX2 10 9 SYNCA 42-45 12 Digital signal processor and CPU core Facsimile peripheral control circuits MOD3 to 0 HDRES Dual-port RAM DVDD4 to 1 DVSS4 to 1 19 18 MTA4 to 1 MTB4 to 1 MOT SH4 to 1 VBCK VIR VSCK VSEN VSDA VPCK VPST VPDA S15 to 0 UC3 to 0 IRO4 to 1 ADCK EYSY EOMD PLSD UITCK U1SD U1RCK U1RD U1ST U2TCK U2SD U2RCK U2RD U2ST HALT BA A23 to 0, MD7 to 0, RD, WR, R/W MN195001 Pin Descriptions Functional Group For Communications Equipment Symbol A0 to 23 MD0 to 7 RD WR R/W CX SCX2 SYNCA HDRES MOD0 to 3 HALT BA IREF0 IREF1 TXLPIN TXOUT RXL IREF2 RXLPIN HPOUT AGCIN AGCOUT SHIN VREFH VREFL PLSD SO to 15 UC0 to 3 IRO1 to 4 U1ST U1RD U1RCK U1SD U1TCK U2ST U2RD U2RCK U2SD U2TCK SH1 to 4 MTA1 to 4 Pin No. 128 to 114, 111 to 103 8 to 1 16 15 17 11 10 9 12 42 to 45 19 18 38 37 36 34 32 31 30 29 28 27 26 40 41 23 46 to 61 99 to 102 67 to 70 62 63 64 65 66 71 72 73 74 75 85 to 82 92 to 89 I/O O I/O O O I I I O I I I O AI AI AI AO AI AI AI AO AI AO AI AI AI O I/O O I I I I O I/O I I I O I/O O O Function Descreption External memory address bus External memory data bus External memory read signal External memory write signal External memory read/write control Basic clock input Basic clock frequency selection System clock output Reset signal Mode setting inputs HALT signal for internal digital signal processor External memory bus available signal D/A converter input Reference voltage for transmit circuits Transmit low-pass filter input Analog transmit signal output Analog receive signal input Reference voltage for receive circuit Receive low-pass filter input Receive high-pass filter output Receive automatic gain control input Receive automatic gain control output A/D converter sample-and-hold circuit input A/D converter reference "H" level A/D converter reference "L" level External amplifier gain control signal General-purpose I/O port Programmable chip select External interrupts USART (CH1) external synchronization clock USART (CH1) receive data USART (CH1) receive clock USART (CH1) transmit data USART (CH1) transmit clock USART (CH2) external synchronization clock USART (CH2) receive data USART (CH2) receive clock USART (CH2) transmit data USART (CH2) transmit clock Thermal head control signals Motor A control signals Fax control Signals Analog Interface Control Interface Memory Interface For Communications Equipment Pin Descriptions (continued) Functional Group MN195001 Symbol MTB1 to 4 MOT Pin No. 81 to 78 93 86 87 88 94 95 96 97 98 21 22 20 13, 77, 114, 25 14, 76, 112, 24 39 35 33 I/O O O O O O O I I O I O O O DP DP AP AP AO Function Description Motor B control signals Motor synchronization signal Plotter data clock Plotter synchronization burst clock Plotter data Scanner clock Scanner data input clock Scanner data Scanner input ready Scanner data input enable Eye pattern data clock Eye pattern data synchronization signal Eye pattern data Power supply for digital circuits +5 V Power supply for digital circuits Power supply for analog circuits HVDD output GND GND Power supply for analog circuits +5 V Fax Control Signals VPST VPCK VPDA V8CK VSCK VSDA VIR VSEN ADCK EYSY EQMD DVDD1 to 4 DVSS1 to 4 AVDD AVSS HVDD EYE I/F Power Supply Interface MN195001 Package Dimensions (Unit: mm) QFH128-P-1818 For Communications Equipment 20.0±0.2 18.0±0.2 96 97 65 64 (1.25) 33 1 0.5 32 0.2±0.1 18.0±0.2 20.0±0.2 128 (1.25) 1.0±0.2 3.3±0.2 3.4±0.3 0.15–0.05 +0.10 0.1±0.1 0.1 SEATING PLANE 0.5±0.2 0 to 10°