MN3883S

CCD Delay Line Series MN3883S Full Multi-PAL-Compatible CCD Video Signal Delay Element Overview The MN3883S is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O blocks, 1/2nd frequency doubler, two switchable CCD analog shift registers, a clamp bias circuit, resampling output amplifiers, a mode selection circuit and booster circuits. When the switch input is "H" level, the MN3883S samples the input using the supplied clock signal with a frequency 7.15909 MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the NTSC system) each for the two lines. When the switch input is "M" level, the MN3883S samples the input using the supplied clock signal with a frequency 8.8672375 MHz of twice the PAL color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the NTSC system) each for the two lines. When the switch input is "L" level, the MN3883S samples the input using the supplied clock signal with a frequency 8.8672375 MHz of twice the PAL color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period for the PAL system) for the Y output and 2 H for the C output. Pin Assignment VBIASC VOC N.C. VDD –VBB N.C. VOY VBIASY 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VINC N.C. N.C. XI VSS SW N.C. VINY ( TOP VIEW ) SOP016-P-0225 Features Single 4.9 V power supply Single chip combining luminance signal delay element and delay element for color signal converted to low frequency Full Multi-PAL support, switchable between NTSC, 4.43 NTSC, and PAL systems Applications Full multi-PAL-compatible VCRs 1 MN3883S Block Diagram CCD Delay Line Series 12 4V DD VSS Bias circuit VINC 16 P Charge input block CCD 8 stages CCD 3.5 stages CCD 3 stages ø1 driver ø2 driver øR driver øSH driver øSH driver + CCD + CCD 108 stages 451 stages Charge detection block Resampling VOC output amplifier 2 443N Charge input block N Charge input block øS driver Timing adjustment N 443N XI 13 Waveform amplifier adjustment block P 1/2nd frequency doubler Timing adjustment øS driver ø1 driver ø2 driver øR driver øSH driver øSH driver Clamp circuit Charge input block 443N Charge 9 input block N Charge input block 5 -VBB P CCD + CCD + CCD 7.5 stages 108 stages 451 stages CCD 3.5 stages CCD 3 stages Mode selection circuit 11 Charge detection block 7 Resampling VOY output amplifier VINY Three input levels: H: NTSC M: 4.43 NTSC L: PAL 2 VBIASY SW 8 1 VBIASC CCD Delay Line Series Application Circuit Example MN3883S 10µF – + 1 VBIASC + (0.01µF) 12 VSS 0.1µF Bias circuit VINC 16 (0.01µF) Charge input block 443N Charge input block N Charge input block øS driver Timing adjustment N 443N XI 13 Waveform amplifier 1000pF adjustment block P 4 VDD CCD 8 stages CCD 3.5 stages CCD 3 stages + CCD 108 stages 2 VOC CCD Charge detecResampling 451 stages tion block output amplifier ø1 driver ø2 driver øR driver øSH driver øSH driver P 1/2nd frequency doubler Timing adjustment øS driver ø1 driver ø2 driver øR driver øSH driver øSH driver Clamp circuit Charge input block 9 443N Charge VINY input –+ block 0.47µF N Charge input block -VBB 5 P CCD + CCD 7.5 stages 108 stages CCD 3.5 stages CCD 3 stages + CCD 451 stages Charge detection block 7 VOY Resampling output amplifier Mode selection circuit 11 8 VBIASY (0.01µF) Three input levels: H: NTSC M: 4.43 NTSC L: PAL SW (0.01µF) Note: When an electlytic capacitor is attached to pin 5, connect the negative pole to pin 5. 3 MN3883S Package Dimensions (Unit:mm) SOP016-P-0225 CCD Delay Line Series 10.10±0.20 16 9 1.10±0.20 4.30±0.20 6.50±0.20 1 8 0.15 -0.05 +0.10 0 to 10° 1.50±0.20 (0.6) 1.27 0.40±0.10 SEATING PLANE 4 0.10±0.10 1.60 -0.20 +0.50 0.40min.