MN3890S

CCD Delay Line Series MN3890S NTSC-Compatible CCD 1 H Video Signal Delay Element Overview The MN3890S is a 1 H image delay element of a 4 fSC CMOS CCD and suitable for video signal processing applications. It contains such components as a frequency-doubler circuit, a shift register clock driver, a 906-stage CCD analog shift register, and a resampling output amplifier. The MN3885S drives and samples the 906-stage analog shift register using a redoubled version of the supplied clock signal with a frequency 7.16 MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces a delay of 1 H (the horizontal scan period). Pin Assignment VIN VBB VDD VSS 1 2 3 4 8 7 6 5 VO VGC PCOUT & VCOIN XI ( TOP VIEW ) SOP008-P-0225A Features Single 5.0 V power supply Energy-saving design based on CMOS process Low EMI levels from clock during driving Applications VCRs, Video cameras Structure and Operation The MN3890S consists of the operational blocks shown in the block diagram. Frequency-doubler circuit When the 7.16 MHz of the doubled NTSC color signal subcarrier frequency is inputted from the clock input pin XI, 14.32 MHz clock of fourfold frequency of color signal subcarrier is generated by this circuit. Clock driver This block generates two transfer clock signals, ø1 and ø2, synchronized with the 14.32 MHz clock signal from the frequency-doubler circuit. It also generates the sampling clock signals øS and øS', resampling clock signal øSH, and reset clock signal øR that have adjusted timing relations with ø1 and ø2. CCD analog shift register This block first converts the analog signal from the VIN input signal pin into a voltage signal, and inputs it into 906-stage analog shift register. The shift register samples the shift register input with the sampling clock øS, and converts the results to charges, and uses transfer clocks ø1 and ø2 to transfer the results to the following block, the charge detection block, where the charges is converted into a voltage signal. Resampling output amplifier In the output amplifier, this voltage signal is done Sample-and-Hold by resampling, and Y-signal as it is outputted at Vo. Operation The following is an explanation of delay line operation. The waveforms driving the shift registers are as shown in the timing chart on page 622. The input signal voltage sampled during the interval between t=0 and t=τc (where τc is one-half the sampling interval) appears at the V O o utput pin at the point t=1813τc. 1 MN3890S Block Diagram CCD Delay Line Series VDD 3 Bias circuit Booster circuit 7V GC VIN 1 Charge input block CCD 906 stages Charge detection block Resampling output amplifier 8 VO øS driver Waveform adjustment block øR driver ø1 driver øSH driver Timing adjustment ø2 driver øSH driver XI 5 Waveform amplifier adjustment block Phase comparator 1/2nd frequency doubler VCO Substrate bias generator 6 4 VSS 2 PCOUT & VCOIN VBB 2 CCD Delay Line Series Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 Symbol VIN VBB VDD VSS XI PCOUT & VCOIN VGC VO Function Description Signal input pin Substrate connection pin Power supply Ground 7.16 MHz clock input pin Phase comparator output and voltage controlled oscillator input Output gate connection pin Signal output pin MN3890S Remarks Negative voltage pin Operating Conditions Parameter Power supply voltage Input clock frequency Signal bandwidth Input clock amplitude (sine wave) Ambient temperature Symbol VDD fck Vck Ta 0.2 –20 min 4.75 typ 5.00 7.15909 0.3 1.0 60 max 5.25 Unit V MHz VP–P ˚C Electrical Characteristics VDD=5.0V, Vck=0.3VP-P (sine wave), Vin=0.5VP-P (sine wave), fck=7.15909MHz, fsig=200kHz, Ta=25˚C Parameter Power supply current Signal bandwidth Insertion gain Total harmonic distortion Signal-to-noise ratio Clock leak 1 Clock leak 2 Delay Output impedance Input bias voltage Output bias voltage Substrate voltage Symbol Conditions –3 dB for 200 kHz value fsig=200kHz fsig=200kHz Signal output (VP-P)/noise output (rms) 7.16 MHz component/main output signal 14.32 MHz component/main output signal min 2.5 –1.5 48 IDD BW IG THD S/N NC1 NC2 τD Zo VBIN VBO –VBB Applied to input from VIN signal input pin Applied to output from VO signal output pin typ 23 5.5 1.5 1 56 –50 –20 63.32 0.5 2.85 2.85 –2.8 max 46 4.5 4.5 –40 –10 0.9 Unit mA MHz dB % dB dB dB µs kΩ V V V 3 MN3890S Timing Chart CCD Delay Line Series 906 stages t=0 t=τc t=1813τc ø1 ø2 øS øSH øR VIN A1 A2 A2 VO A1 4 CCD Delay Line Series Application Circuit Example MN3890S 5V + – 10µF 0.1µF Bias circuit Booster circuit 7 VGC 0.01µF 3 VDD Signal input – + VIN 0.47µF 1 Charge input block CCD 906 stages Charge detection block Resampling output amplifier Signal output 8 VO 330Ω øS driver Waveform adjustment block Timing adjustment Clock input øR driver ø1 driver øSH driver ø2 driver øSH driver XI 5 Waveform amplifier adjustment block 1000pF 1/2nd frequency doubler Phase comparator VCO Substrate bias generator PCOUT & 6 VCOIN VSS 4 VBB 0.01µF 0.01µF 820Ω 4700pF 2 5 MN3890S Package Dimensions (Unit:mm) SOP008-P-0225A CCD Delay Line Series 0.4 0.4±0.25 1 8 1.27 4 5 0.1±0.1 0.3 4.2±0.3 6.5±0.3 6 0.15 0.65 1.5±0.2 5.0±0.3