MN39571PT

CCD Area Image Sensor MN39571PT 9.2mm (type-1/2) 2,310k pixel CCD Area Image Sensor s Overview The MN39571PT is a super high resolution CCD area image sensor which includes 2,310k pixels in type-1/2 image format size. Adopting RGB Bayer arrangement in primary color filter array on chip provides excellent color reproduction. As the aspect ratio of image area is 3:2 which is the same as that of 35mm film, pictures can be taken in similar framing manner to use of a usual film camera. As The MN39571PT has also a skipping readout mode for image monitoring by LCD panel,you can fix the composition in real time. Part Number Size System IS Color or B/W Color MN39571PT 9.2mm(type-1/2) s Features • Photographic grade super high resolution by 2,310k pixels in type-1/2 format • Responds to 5:1 skipping readout mode for LCD monitoring • The same aspect ratio of 3:2 as a 35mm film • Newly developed small plastic package Outline dimensions : 14.0mm(W) × 1 2.4mm(D) × 3.4mm(t)(Without lead pins) s Applications • Digital still camera • FA, OA cameras s Device Configuration Diagram Vertical dummy bit (No PD) Al shielding (PD exists) For transient (PD exists) Valid pixels 2 OB part 8 81 2 1200 4 2 2 8 1800 2 4 Vertical dummy bit (No PD) 1901 Effective horizontal CCD 1 13 Horizontal dummy bit 4 Horizontal dummy bit 1 MN39571PT s Pin Assignments PW RG RD OD VO LG OG φH1 φH2 Sub 1 2 3 4 5 6 7 8 9 10 (Top View) 20 19 18 17 16 15 14 13 12 11 φV1 φV2 φV3 φV4 φV5 φV6 φV7 φV8 PT IS CCD Area Image Sensor s Pin Descriptions Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 PW RG RD OD VO LG OG φH1 φH2 Sub IS PT φV8 P-well Reset gate Reset drain Output drain Video output Output load transistor gate Output gate Horizontal register clock pulse (1) Horizontal register clock pulse (2) Substrate Horizontal CCD input source P-well for protection circuit Vertical shift register clock pulse 8 20 φV1 19 φV2 18 φV3 17 φV4 16 φV5 15 φV6 Descriptions Pin No. Symbol 14 φV7 Descriptions Vertical shift register clock pulse 7 Vertical shift register clock pulse 6 Vertical shift register clock pulse 5 Vertical shift register clock pulse 4 Vertical shift register clock pulse 3 Vertical shift register clock pulse 2 Vertical shift register clock pulse 1 2 CCD Area Image Sensor s Absolute Maximum Ratings and Operating Conditions Rating Parameter Output drain voltage Reset drain voltage Input source voltage Protection P-well voltage P-well voltage Output load transistor gate voltage Output gate voltage Reset  pulse voltage Horizontal register clock pulse voltage 1 Horizontal register clock pulse voltage 2 Vertical shift register clock pulse voltage 1,5 H-L Bias Symbol VOD VRD VIS VPT *2 VPW VLG VOG VφRG(H-L) *3 VφRG(Bias)*3 VφH1(H) VφH1(L) VφH2(H) VφH2(L) VφV1,5(H) *2 VφV1,5(M) *2 VφV1,5(L) *2 Vertical shift register clock pulse voltage 3,7 VφV3,7(H) *2 VφV3,7(M) *2 VφV3,7(L) *2 Vertical shift register clock pulse voltage 2,6 Vertical shift register clock pulse voltage 4,8 Substrate voltage VφV2,6(M) *2 VφV2,6(L) *2 VφV4,8(M) *2 VφV4,8(L) *2 VSub*2 φVSub *4,*5 Operating temperature Storage temperature Topr Tstg − 0.2 − 10 − 30 min − 0.2 − 0.2 − 0.2 − 10.0    − 0.5  − 0.2  − 0.2   − 10.0   − 10.0  − 10.0  − 10.0 max 18.0 18.0 18.0 0.2   8.0  8.0  8.0  18.0   18.0   15.0  15.0  MN39571PT Operating condition min 15.2 15.2 15.2 − 9.3  typ 15.5 15.5 15.5 − 9.0 0 Supplied internally Supplied internally 3.0 3.3 3.6 max 15.8 15.8 15.8 − 8.7  Unit V V V V V V V V V V Reference voltage Supplied internally 3.0 − 0.2 3.0 − 0.2 15.2 − 0.2 − 9.3 15.2 − 0.2 − 9.3 − 0.2 − 9.3 − 0.2 − 9.3 3.3 0 3.3 0 15.5 0 − 9.0 15.5 0 − 9.0 0 − 9.0 0 − 9.0 3.6 0.2 3.6 0.2 15.8 0.2 − 8.7 15.8 0.2 − 8.7 0.2 − 8.7 0.2 − 8.7 V V V V V Supplied internally 45.0 60 70 26.5   27.0 25  27.5   V °C °C Note)1. Standard light input defines Standard light input is the one when the exposure is done at a lens aperture of F8, using a light source of 2856 K and 1050 nt, and placing a color temperature conversion filter LB-40 (HOYA) and an IR cutting filter CAW-500 (t = 2.5 mm) in the light path.   2. *1: VSub internal settings guarantee blooming at 400 times light input of the standard light input. 3. *2: VPT is set so that the following conditions are set for VL of the vertical shift clock. VPT < VL = 4. *3: VφR(H) 5. *4: VSub when using electronic shutter function H-L VφR(L) Bias (Internally) E φVSub "H" φVSub "L" E φVSub(V) VSub(V) 6. *5: Separate powor supply is recommended for φVSub 3 MN39571PT s Optical Characteristics Part Number MN39571PT Color or B/W Color Effective S/N Saturation Sensitivity output F8 pixels  typ typ typ H V (dB) (mV) (mV)  500 340 Vertical smear Sm typ(%) 0.01 CCD Area Image Sensor Image lag Horizontal Vertical resolution resolution typ typ typ (%) (TV-lines) (TV-lines)    1816 1208 Note)1. 1/7.5 sec frame storage. Horizontal register clock frequency 24 MHz   2. *1: Mechanical shutter saturation output s Package Dimensions (Unit : mm) • WDIP020-P-0500A 14.00±0.08 7.00±0.08 20 6.20±0.08 3.40±0.30 11 3.90±0.15 (0.38) 12.40±0.08 11.60±0.10 0.015 1.71±0.10 0.25 1 10 3.40±0.15 2.60±0.15 12.60±0.10 (0.60) R0.15 ns 3.90±0.15 (0.80) 0.30±0.05 0.46 M 1.27 4 (1.30) 12.95±0.25 (12.77)