MN6152

For Communications Equipment MN6152U PLL LSI with Built-In Prescaler Overview The MN6152U is a CMOS LSI for a phase-locked loop (PLL) frequency synthesizer with serial data input. It consists of a two-coefficient prescaler, variable frequency divider, phase comparator, and charge pump. It offers high-speed operation on a low power supply voltage (1.8 to 2.5 V) and low power consumption (5 mW for VDD=2.0 V, F IN=100 MHz). Other features include intermittent operation by the power save (PS) control signal and high-speed pull-in that rapidly corrects the phase differences occurring at the start of operation. Pin Assignment XIN XOUT FV VDD DOP VSS LD FIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OR OV LC FR PS LE DATA CLK Features Low power supply voltage: VDD =1.8 to 2.5V Low power consumption: 5mW (VDD =2.0V, FIN =100MHz) High-speed operation: FIN =175MHz F requency dividing ratios in reference frequency dividing stage: 5 to 131,071 Frequency dividing ratios in comparator stage: 272 to 262,143 Lock detector output pin Two types of phase comparator output - Internal charge pump output - Output for external charge pump Output monitor pins for both comparator and reference frequency dividing stages (TOP VIEW) SSOP016-P-0225 MN6152U Block Diagram Amplifier XIN 17-bit programmable counter XOUT 17-bit latch CLK 9 Control 2 1 Phase matching 13 FR 14 LC DATA 18-bit shift register 10 Data control 7 LD 15 OV 16 OR 5 DOP Phase comparator LE 18-bit latch PS Amplifier FIN 8 Prescaler and phase matching Swallow counter 12 11 For Communications Equipment 14-bit programmable counter 3 FV For Communications Equipment Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 Symbol XIN XOUT FV V DD D OP V SS LD FIN CLK Function Description Crystal oscillator connection pins: XIN =Oscillator circuit input pin; XOUT=Oscillator circuit output pin. Frequency divider output signal in comparator stage. Phase comparator input monitor. Power supply Low-pass filter connection pin. Use a passive filter. Ground Phase comparator output pin: "H" level for locked; "L"level for unlocked. Frequency divider input pin in comparating stage. Shift register clock input pin. The chip latches data at the rising edge of the CLK signal. Shift register data input pin. 10 DATA The final two bits in the data select the write latch: "11" for R-latch; "01" for N-latch. Load enable signal input pin. 11 LE This is the latch-write-enable signal. It is at "H" level for write. Power save control signal input pin. MN6152U "H" level input starts the frequency divider and places the chip in operational mode. 12 PS "L" level input places the chip in standby mode, which saves power. The chip switches the internal charge pump output to the H-z state and the loop is opened. 13 FR Reference frequency divider output signal. Phase comparator input monitor. Charge pump control signal output pin. 14 15 16 LC OV OR When frequency divider operation is stopped, this pin is at "L" level, the internal charge pump output is in the high-impedance state, and the loop is opened. Phase comparator output pin for external charge pump. MN6152U MN6152 Frequency Dividing Data Settings For Communications Equipment The following formula shows frequency divider operation. FIN ={ (16 × N) + A} × (XIN ÷ R) where FIN : VCO output frequency N : Setting for 14-bit programmable counter on comparator side A : Setting for 4-bit swallow counter on comparator side XIN : Reference oscillator frequency R : Setting for 17-bit programmable counter on reference side Note that N should be greater than A. N-Side Latch Data MSB 14 bits Programmable counter setting (N) 4 bits LSB Swallow counter setting (A) For Communications Equipment Absolute Maximum Ratings Parameter Power supply voltage Input pin voltage Output pin voltage Power dissipation Operating ambient temperature Storage temperature Symbol VDD VI VO PD Topr Tstg Rating – 0.3 to +3.5 VSS – 0.3 to V DD +0.3 VSS – 0.3 to V DD +0.3 20 –20 to +60 –55 to +125 MN6152U Unit V mW ˚C Operating Conditions VSS=0V, Ta=–20 to +60˚C Parameter Power supply voltage Symbol VDD Test Conditions min 1.8 typ 2.0 max 2.5 Unit V Electric Characteristics VDD=2V, Ta=–20 to +60˚C Parameter Power supply voltage Symbol IDD IDstop Test Conditions FIN =100MHz, XIN =20MHz, PS="H" PS ="L" (at power save operation) VDD=1.8 to 2.5V min typ max 2.5 10 Unit mA µA Input Pins CLK, DATA, LE, and PS VIH VIL ILI VDD=1.8 to 2.5V "H" level input voltage "L" level input voltage Input leakage current Input Pin Input voltage Input current Input leakage current Maximum operating frequency Minimum operating frequency Input Pin Input voltage Input current Input leakage current Maximum operating frequency XIN FIN VDD – 0.2 VSS VDD 0.2 ±1.0 V µA Vp-p µA VIN IIF ILIF FINMAX FINMIN VIN IIX VLIX XINMAX Pull-up resistor present (PS="L") VIN =0 or 2V VIN =0.4 Vp-p Pull-up resistor present (PS="L") VIN =0 or 2V (PS="H") VIN =0.4 Vp-p VIN =0.4 Vp-p 0.4 –100 ±20 175 10 0.4 2.5 5.0 20 µA MHz MHz Vp-p mA µA MHz VDD=1.8 to 2.5V MN6152U Electrical Characteristics VDD=2V, Ta=–20 to +60˚C For Communications Equipment Parameter Symbol Test Condition Crystal Oscillator Pins X IN, X OUT VDD=1.8 to 2.5V Crystal oscillator frequency Output Pins "H" level output voltage "L" level output voltage Output Pin "H" level output voltage "L" level output voltage Output Pin DOP "H" level output voltage "L" level output voltage Output Pin OR "L" level output voltage Setup time *1 Hold time * 1 fXtal VDD =1.8 to 2.5V min 20 typ max Unit MHz FV, FR, LC, OV VOH VOL VXOH VXOL VDD=1.8 to 2.5V IOH = –100µA IOL= 100µA IXOH= –500µA IXOL= 500µA VDop=1.6V VDop=0.4V VOR=0.4V VDD– 0.3 V SS VDD– 0.3 V SS –100 100 100 500 500 500 VDD 0.3 VDD 0.3 V XOUT VDD=1.8 to 2.5V V IDOH IDOL VDD=1.8 to 2.5V µA IORL tsul tsu2 tH µA ns ns ns Note*1: The following timing chart shows the setup and hold times. DATA 50% tsu1 tH CLK tsu2 LE For Communications Equipment Frequency Divider Setting MN6152U R-side latch CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 LSB 18 19 DATA LE MSB N-side latch CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 LSB 19 20 DATA LE MSB · I nput the data MSB first. · The data is read at the rising edges of the CLK signal. · Drive the LE pin at "L" level when writing data. Usage Note Be particularly careful with this product as it is more sensitive on the static electricity damage than most of our other products. MN6152U Package Diemnsions (Unit: mm) SSOP016-P-0225 For Communications Equipment 6.5±0.2 16 9 1.0±0.1 4.3±0.2 6.3±0.2 0.15 -0.05 +0.10 0 to 10° 0.5±0.1 (0.45) 1.45±0.20 0.1±0.1 SEATING PLANE 1.55±0.30 1 8 0.8 0.15 0.35±0.10