MN6474A

For Audio Equipment MN6474A D/A Converter for Digital Audio Equipment Overview The MN6474A is a CMOS digital-to-analog converter with a built-in 16-bit digital filter for pulse code modulation (PCM) digital audio equipment. It uses noise shaping technology to convert a digital signal into a PWM signal. It contains a 4-fold oversampling digital filter that permits simplification of the low pass filter after the D/A converter, thus greatly reducing the power consumption of the entire D/A conversion system. The chip provides both regular and inverted phase outputs for both channels. The chip contributes to cost and size reductions for CD players and other digital audio equipment. Pin Assignment LRPOL LRCLK BCLK SRDATA DVSS3 DVDD 384FS PD MDATA MCLK 33 34 35 36 37 38 39 40 41 42 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 192FS ZFLGB NSUB DVSS2 DVDD2 N.C. X1 X2 DVSS1 DVDD1 AVDD1 Built-in 4-fold oversampling digital filter (ripple of only ±0.0072 dB within the supported band and attenuation of 62.7 dB within the cutoff band) Internal resolution of 18 bits Two's complement input (I2S input code also supported) Built-in overflow limiter No zero cross distortion Sample-and-hold circuit is unnecessary Output pin for detecting zero input Single 5V power supply Applications CD players and other digital audio equipment MLD RSTB IE TP1 TP2 TEST1 TEST2 N.C. N.C. AVDD4 Features 1 2 3 4 5 6 7 8 9 10 OUTR(–) AVSS1 AVSS2 OUTR(+) AVDD2 N.C. AVDD3 OUTL(+) AVSS3 AVSS4 OUTL(–) (TOP VIEW) QFP042-P-1414A MN6474A Block Diagram For Audio Equipment ZFLGB TEST2 TEST1 384FS 192FS TP2 TP1 X1 7 6 5 4 31 39 32 26 Timing Generator 33 34 35 36 3 Noise Shaping Logics PWM Logics (L) S/P Converter FIR 1 FIR 2 PWM Logics (R) 21 Analog Block 18 (R) OUTR(–) OUTR(+) LRPOL LRCLK BCLK SRDATA IE Microcomputer Interface 14 Analog Block 11 (L) 25 X2 OUTL(+) OUTL(–) 40 41 42 MCLK MDATA MLD PD 1 For Audio Equipment Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol MLD RSTB IE TP1 TP2 TEST1 TEST2 N.C. N.C. AV DD4 OUTL(–) AV SS4 AV SS3 OUTL(+) AV DD3 N.C. AV DD2 OUTR(+) AV SS2 AV SS1 OUTR(–) AV DD1 DV DD1 DV SS1 X2 X1 N.C. DV DD2 DV SS2 NSUB ZFLGB 192FS LRPOL LRCLK Function Description Microcomputer command load input ("L" level to load) Reset pin (active "L"). Always pull this pin low after applying the power. Input format selection pin. Digital filter test output pin 1. Digital filter test output pin 2. Digital filter test input pin 1. Digital filter test input pin 2. No connection No connection "H" level; I 2S format MN6474A "L" level; signal processing LSI format. Leave this pin open. Leave this pin open. Keep this pin at "L" level. Keep this pin at "L" level. Leave these pins open. Leave these pins open. (+5V) Power supply pin 4 for analog circuits. Ground pin 4 for analog circuits. Ground pin 3 for analog circuits. Left channel inverted phase PWM output pin. Left channel normal phase PWM output pin. Power supply pin 3 for analog circuits. No connection Leave this pin open. (+5V) Power supply pin 2 for analog circuits. Ground pin 2 for analog circuits. Ground pin 1 for analog circuits. Right channel inverted phase PWM output pin. Power supply pin 1 for analog circuits. Power supply pin 1 for digital circuits. Ground pin 1 for digital circuits. Crystal oscillator pin. Crystal oscillator pin. (External clock input pin) No connection Leave this pin open. (+5V) Power supply pin 2 for analog circuits. Ground pin 2 for digital circuits. Connect to D-VDD. (Silicon substrate potential fixing pin) Max. load capacity: 30 pF. "H" level; selects the left channel "L" level; the right channel. LRCLK pin. When the LRPOL pin is at "H" level, "H" level in this pin indicates left channel data input; "L" level indicates right channel data input. When the LRPOL pin is at "L" level, "L" level in this pin indicates left channel data input; "H" level input indicates right channel data input. Output pin for detecting zero input. 192fs(=9.216 MHz)output pin. LRCLK polarity selection pin. (+5V) (+5V) (Power supply for oscillator circuit) (Ground for oscillator circuit) (+5V) Right channel through phase PWM output pin. 35 36 37 BCLK SRDATA DV SS3 Serial input bit clock Serial input data (digital) input pin. Ground pin 3 for digital circuits. MN6474A Pin Descriptions (continued) Pin No. 38 39 40 41 42 Symbol DVDD 384FS PD MDATA MCLK For Audio Equipment Function Description Power supply pin for digital circuits. (Silicon substrate potential fixing pin.) (+5V) 384fs (=18.432 MHz) Power down pin. output pin. (active "H") Max. load capacitance: 30 pF. Microcomputer command data input pin. Clock input pin for microcomputer command. Conversion Characteristics DV DD=5.0V, DVSS=0V, AVDD=5.0V, AVSS=0V, f=33.8688MHz, Ta=25˚C Parameter Analog characteristics Signal-to-noise ratio Dynamic range Total harmonic distortion Crosstalk Output level *1 Symbol S/N D.R. THD+N Test Conditions EIAJ (1kHz) EIAJ (1kHz) EIAJ (1kHz) EIAJ (1kHz) 1kHz F.S. min 95 90 90 1.4 typ 106 98 0.003 98 1.7 max Unit dB dB 0.005 % dB Vrms Note*1: These analog characteristics are for circuits equivalent to the suggested application circuit. DVSS AVDD AVSS –15 E 15 DVDD R1 10W C14 47µF + *C1 100µF R4 330W R5 1kW R7 1kW 7th order L.P.F(HAF 0079) 1 2 3 4 5 6 7 8 9 10 R3 330W + R6 1kW R8 1kW For Audio Equipment R32 470W C15 47µF + R23 22W + *C6 0.56µF + + + C28 220µF Application Circuit Example 22 23 *C5 10µF 24 5pF R24.7kW 25 C4 26 33.8688 C3 5pF 27 MHz 28 29 30 31 32 + C10 22µF R9 47kW C16 C17 47pF 1–+ IC2 R14 1–+ 8 –+ 8 –+ IC4 R10 47kW R11 47kW + + C11 C12 22µF 22µF 47pF AVDD1 DVDD1 DVSS1 X2 X1 N.C. DVDD2 DVSS2 NSUB ZFLGB 192fs R32 470W OUTR(–) AVSS1 AVSS2 OUTR(+) C13 C26 2200pF 22µF C22 47pF R19 R17 220W N 10µF R34 R13 47kW C24 470kW 33kW R24 C29 C32 22W 220µF 10µF + + N R27 330W R ch R29 100kW C34 330pF C35 330pF R26 22W C31 220µF R28 N C33 330W 10µF R30 100kW L ch C2 470W C18 47pF C19 47pF R12 47kW MN6474A + R33 AVSS3 AVSS4 OUTL(–) 100µF 33 34 35 36 37 38 39 40 41 42 AVDD2 N.C. AVDD3 OUTL(+) LRPOL LRCLK BCLK SRDATA DVSS3 DVDD 384FS PD MDATA MCLK 21 20 19 18 C7 + 17 16 330µF 15 14 13 C8 330µF 12 11 33kW C20 47pF C27 2200pF R21 47pF 47kW C23 R20 R35 220W N 470kW R15 33kW R18 47kW 10µF C25 + C32 AVDD4 10 N.C. 9 N.C. 8 TEST2 7 TEST1 6 TP2 5 TP1 4 IE 3 RSTB 2 MLD 1 *C9 0.56µF 8 1–+ –+ R25 22W 8 IC1 1–+ C21 47pF R16 33kW IC1 to 4 AN6558 R22 47kW –+ IC3 220µF S2 S3 S1 S4 S5 S6 1 2 3 4 5 6 7 8 9 10 7th order L.P.F(HAF 0079) VDD VSS *C1,C5,C6 and C9 are attached to the rear of the P base. PD(S3) Signal processing LSI format I2S format RSTB(S1) IE(S4) "L" – Reset MN6474A "H" Power down mode – MN6474A Package Dmensions (Unit: mm) QFP042-P-1414A For Audio Equipment 18.7±0.4 14.0±0.2 32 22 21 (0.65) 14.0±0.2 42 11 1 (1.92) 1.27 10 2.6max. 2.2±0.2 0.4±0.1 (2.35) 18.7±0.4 33 0.15 -0.05 +0.10 0.1±0.1 0.15 SEATING PLANE (1.5±0.2) 0 to 10°