MN65543

A/D, D/C Converters for Image Signal Processing MN65543S Low Power 8-Bit CMOS A/D Converter for Image Processing Overview The MN65543S is an 8-bit CMOS analog-to-digital converter with a maximum conversion rate of 15 MSPS. It uses a half flash structure based on chopper comparators and achieves both high speed and low power consumption with multiplex processing. Pin Assignment Features Maximum conversion rate: 15 MSPS (min.) Linearity error: ±0.5 LSB (typ.) Differential linearity error: ±0.3 LSB (typ.) Power supply voltage: 4.40 to 5.25 V Power consumption: 90 mW (typ.) Applications Digital television receivers Digital video equipment Digital image processing equipment NOE DVSS (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 DVDD CLK 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DVSS VRB VRBS AVSS AVSS VIN AVDD VRT VRTS AVDD AVDD DVDD (TOP VIEW) SOP024-P-0375 1 MN65543S Block Diagram A/D, D/C Converters for Image Signal Processing AVDD 14 11 DVDD 13 AVDD DVSS AVSS AVSS 23 21 22 20 19 18 17 24 16 Lower Comparator (4-bit) 15 Reference Resistor Encoder (4-bit) AVDD Lower Comparator (4-bit) Encoder (4-bit) Lower Comparator (4-bit) Clock Generator Encoder (4-bit) Data Latch 10 D1 D7(MSB) D0(LSB) D3 D5 2 DVSS NOE CLK D2 D4 D6 12 2 3 4 1 5 6 7 8 9 DVDD VRBS VRTS VRB VRT VIN A/D, D/C Converters for Image Signal Processing Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol NOE DVSS D0 D1 D2 D3 D4 D5 D6 D7 DVDD CLK DVDD AVDD AVDD VRTS VRT AVDD VIN AVSS AVSS VRBS VRB DVSS Function Description Output enable Ground for digital circuits Digital output (LSB) Digital output Digital output Digital output Digital output Digital output Digital output Digital output (MSB) Power supply for digital circuits Sampling clock Power supply for digital circuits Power supply for analog circuits Power supply for analog circuits Power supply for reference voltage (TOP) Reference voltage (TOP) Power supply for analog circuits Analog input Ground for analog circuits Ground for analog circuits Power supply for reference voltage (BOTTOM) Reference voltage (BOTTOM) Ground for digital circuits Ta=25˚C MN65543S Absolute Maximum Ratings Parameter Power supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Symbol VDD VI VO Topr Tstg Rating – 0.3 to +7.0 AVSS – 0.3 to AVDD +0.3 DVSS – 0.3 to DVDD +0.3 –20 to +70 –55 to +125 Unit V V V ˚C ˚C 3 MN65543S A/D, D/C Converters for Image Signal Processing VDD=AVDD=DVDD=5.0V, VSS=AVSS=DVSS=0V, Ta=25˚C Recommended Operating Conditions Parameter Power supply voltage Digital input voltage Reference voltage Symbol VDD VIH VIL VRT VRB tWH tWL VAIN min 4.50 2.4 VSS 3.5 VSS typ 5.00 max 5.25 VDD 0.8 VDD 1.5 Unit V V V V V ns ns "H" level "L" level "H" level "L" level "H" level pulse width "L" level pulse width Clock 30 30 VSS VDD Analog input voltage V Electrical Characteristics Parameter Power supply current Resolution Linearity error Differential linearity error Maximum conversion rate Clock frequency Analog input dynamic range VDD=AVDD=DVDD=5.0V, AVSS=DVSS=0V, Ta=25˚C Symbol IDD RES EL ED Fc(max.) fCLK DR IOH IOL td CI Conditions fCLK = 15 MHz (includes reference power supply) min typ 18 8 max 26 Unit mA bit fCLK=15MHz VRT=3.5V VRB=1.5V 15 1 2 VOH=VDD – 0.8V VOL=0.4V CL=50pF 2 ±0.5 ±0.4 ±1.3 ±0.8 15 VRT –VRB –2 LSB LSB MSPS MHz V mA mA ns pF Output current "H" level "L" level Output delay time Analog input capacitance 25 18 40 4 A/D, D/C Converters for Image Signal Processing Timing Chart MN65543S The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital output 2.5 clock cycles later at the rising edge of the clock signal. Clock Analog input N N+1 N–2 td(25ns) N+2 N–1 N+3 N N+4 N+1 Data output N–3 Note: The circles indicate analog signal sampling points. 5 MN65543S Package Dimensions (Unit:mm) SOP024-P-0375 A/D, D/C Converters for Image Signal Processing 15.30±0.20 24 13 1.10±0.20 7.20±0.20 9.40±0.30 0.15 -0.05 +0.10 0 to 10° 0.30min. 1 12 2.40max. 2.00±0.20 (0.67) 1.27 0.40±0.10 SEATING PLANE 6 0.10±0.10