MN65742

A/D, D/C Converters for Image Signal Processing MN65742 6-Bit, 2-Channel CMOS A/D Converter Overview The MN65742 is a 6-bit, 2-channel CMOS analog-todigital converter. It uses a totally parallel structure based on differential comparators to achieve high-speed operation. Pin Assignment CLK AVDD AVSS VRT N.C. VINA AVSS AVDD POWD VRM VINB VRB AVSS AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DA5 DA4 DA3 DA2 DA1 DA0 AVSS AVDDL DB5 DB4 DB3 DB2 DB1 DB0 Features Resolution: 6 bits Maximum conversion rate: 60 MSPS (min.) Linearity error: ±1.3 LSB (typ.) Differential linearity error: ±1.3 LSB (typ.) Analog input voltage level: 1.5 Vp-p (typ.) (1.0 to 2.5 V) Power supply voltage: 5.0 ±0.25 V 3.0 to 5.25 V (power supply for output pins) Power consumption: 250 mW (typ.) (FC= 60 MSPS, not including reference current) Applications Digital satellite broadcasting receivers Digital video equipment Multimedia equipment Communications equipment (TOP VIEW) SOP028-P-0375 1 MN65742 Block Diagram A/D, D/C Converters for Image Signal Processing AVDD AVDD AVDD AVSS AVSS 13 AV SS 22 AV SS 10 VRM VINA VINB 14 12 Channel B (Bch.) Channel A (Ach.) Comparator Encoder Encoder Comparator Reference resistor array Clock generator Output logic circuits Output logic circuits Clock generator 11 Reference resistor array 15 16 17 18 19 20 23 24 25 26 27 28 POWD 9 CLK DA0 DA1 DA2 DA3 DA4 DA5 DB0 DB1 DB2 DB3 DB4 DB5 2 AVDDL 21 1 5 N.C. 2 8 3 7 4 VRB VRT 6 A/D, D/C Converters for Image Signal Processing Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol CLK AVDD AVSS VRT N.C. VINA AVSS AVDD POWD VRM VINB VRB AVSS AVDD DB0 DB1 DB2 DB3 DB4 DB5 AVDDL AVSS DA0 DA1 DA2 DA3 DA4 DA5 Function Descriptions Clock input Power supply for analog circuits Ground for analog circuits Reference voltage (top) No connection Analog signal input pin Ground for analog circuits Power supply for analog circuits Power-down selection pin Intermediate reference voltage Analog signal input pin Reference voltage (bottom) Ground for analog circuits Power supply for analog circuits Digital output pin Digital output pin Digital output pin Digital output pin Digital output pin Digital output pin Power supply pin for digital output circuits Ground for analog circuits Digital output pin Digital output pin Digital output pin Digital output pin Digital output pin Digital output pin Ta=25˚C MN65742 Absolute Maximum Ratings Parameter Power supply voltage Symbol AVDD AVDDL VI VO Topr Tstg Rating – 0.3 to +7.0 – 0.3 to AVDD +0.3 – 0.3 to AVDD +0.3 – 0.3 to AVDD +0.3 –20 to +70 –55 to +125 Unit V V V V ˚C ˚C Power supply voltage for output circuits Input voltage Output voltage Operating ambient temperature Storage temperature 3 MN65742 A/D, D/C Converters for Image Signal Processing AVDD=5.0V, AVDDL=3.3V, AVSS=0V, Ta=25˚C Recommended Operating Conditions Parameter Power supply voltage Power supply voltage for digital outputs Digital input voltage Reference voltage Clock "H" level "L" level "H" level "L" level "H" level pulse width "L" level pulse width Analog input voltage Symbol VDD DVDDL VIH VIL VRT VRB tWH tWL VAIN min 4.75 3.00 2.2 AVSS 2.0 0.5 7 7 AVSS typ 5.00 3.30 max 5.25 5.25 AVDD 0.8 Unit V V V V V V ns ns 2.5 1.0 3.5 2.0 AVDD V Electrical Characteristics Current Parameter AVDD AVDDL Resolution Linearity error Differential linearity error Maximum conversion rate Clock frequency Analog input dynamic range Output current "H" level "L" level AVDD=5.0V, AVDDL=3.3V, AVSS=0V, VRT=2.5V, VRB=1.0V, Ta=25˚C Symbol Conditions IDD fCLK= 60 MSPS (not including reference current) IDDL RES EL ED FC(max.) fCLK DR IOH IOL td CI VOH=DVDDL– 0.8V VOL=0.4V CL=20pF fCLK=60MSPS min typ 47 3 6 ±0.7 ±0.7 max 80 6 ±1.3 ±1.3 60 VRT–VRB –2.0 Unit mA mA bit LSB LSB MSPS MHz V mA mA ns pF consumption 60 1 1.4 2.0 3 7 20 11 Output delay time Analog input capacitance 4 A/D, D/C Converters for Image Signal Processing Timing Chart MN65742 The chip samples the analog input at the rising edge of the clock signal and provides the corresponding digital output one clock cycle later at the rising edge of the clock signal. tWH tWL Analog input N tsd N+1 N+2 N+3 Clock 1.5V Data output N-2 N-1 N N+1 N+2 N+3 1.5V td Note: The circles indicate analog signal sampling points. 5 MN65742 Package Dimensions (Unit:mm) SOP028-P-0375 A/D, D/C Converters for Image Signal Processing 17.80±0.20 28 15 1.10±0.20 7.20±0.20 9.40±0.30 0.15 -0.05 +0.10 0 to 10° 0.30min. 1 14 2.40max. 2.00±0.20 (0.65) 1.27 0.40±0.10 SEATING PLANE 6 0.10±0.10