MN6761

For Video Equipment MN6761S External Synchronization Control LSI for Color Video Cameras Overview The MN6761S is an external synchronization control LSI for color video cameras. When used in combination with a synchronizing signal generator (MN67601NS or MN67602PS), it provides external synchronization control for NTSC and PAL video systems. Pin Assignment SCPSW1 SCPSW2 WHD N/P BGP GLBSC VSS2 VDD2 GLSYNC TEST2 fHP HPCO XfHOSCI XfHOSCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 4fSC 4fSCOSCO 4fSCOSCI SOPCO SC1 VDD1 VSS1 TEST1 HBLK EXT/INT LSWCONT LSW VR XfH Features Synchronization of both the video camera and the VCR External synchronization inputs: Composite synchronizing signal and burst subcarrier External synchronization techniques • Horizontal synchronization: phase-locked loop • Vertical synchronization: reset technique • Subcarrier synchronization: phase-locked loop Support for both NTSC and PAL systems Built-in feature for automatically switching between external and internal synchronization Built-in horizontal phase adjustment circuit (TOP VIEW) SOP028-P-0375 Applications Color video cameras MN6761S XfH OSCO XfH OSCI XfH HPCO WHD Block Diagram VR fHP 3 11 12 16 13 14 fV V separation Monostable multivibrator XfH oscillator Phase comparator 15 GLSYNC fH H separation 8 7 Internal/external synchronization switch 9 VDD2 VSS2 19 EXT/INT 20 N/P 4 HBLK and BGP pulse generator HBLK CK Line switch control pulse generator SC1 24 D Shift register 18 23 22 LSWCONT VDD1 VSS1 SCPSW1 Selector 1 0˚ 90˚ Gate Line switch SCPSW2 2 TEST2 17 10 Phase comparator 4fSC generator TEST1 21 26 27 25 28 5 BGP 6 4fSC For Video Equipment LSW 4fSC OSCO 4fSC OSCI SCPCO GLBSC For Video Equipment Pin Descriptions Pin No. 23 22 8 7 9 6 3 11 24 1 2 17 Symbol VDD1 VSS1 VDD2 VSS2 GLSYNC CLBSC WHD fHP SC1 SCPSW1 SCPSW2 LSW Pin Name Power supply Power supply Power supply Power supply External synchronizing signal input External burst subcarrier input Horizontal synchronization input Monostable multivibrator input Subcarrier input Subcarrier phase switch inputs Line switch input MN6761S Function Description "H" level (5V) power supply for subcarrier circuits "L" level (GND) power supply for subcarrier circuits "H" level (5V) power supply for synchronizing signal circuits "L" level (GND) power supply for synchronizing signal circuits Input pin for composite synchronizing signal derived from video signal (reference for horizontal and vertical signals) Input pin for burst subcarrier signal derived from video signal (reference for subcarrier signals) Input pin for WHD signal from synchronizing signal generator Pin for connecting CR circuit for adjusting delay for analog monostable multivibrator (thus adjusting horizontal phase) Input pin for SC1 signal from synchronizing signal generator Pin selecting which of the four phase signals generated from the SC1 signal goes to the phase comparator For a PAL system, supply the LSW signal from the synchronizing signal generator. For an NTSC system, keep this pin at "H" level. 4 12 N/P HPCO NTSC/PAL selection input Horizontal phase comparator output "H" level selects NTSC operation; "L" level, PAL operation. This pin is at "L" level when the WHD signal, after passing through the monostable multivibrator, leads the rising edge of the HSYNC signal derived by separating off the horizontal component of the GLSYNC signal and is at "H" level when the signal lags. At all other times, it is in the high-impedance state. 13 XfHOSCI Oscillator input for the synchronization circuits Clock oscillator pins for the synchronization circuits. Connect these pins to an inductor, capacitor, and variable capacitor. (The pins have built-in feedback resistors.) The circuit oscillates during external synchronization mode. The oscillation stops for internal synchronization mode. The oscillator frequency, XfH is 14.31818 MHz (910fH) for NTSC and 4.406 MHz (282fH) for PAL. Clock output pin for synchronizing signal circuits. This pin provides the clock (XfH) for the external synchronization mode and stays at "L" level for the internal synchronization mode. Connect to the EX910fHI pin of the synchronizing signal generator for NTSC operation and to the EX282fHI pin for PAL operation. 14 XfHOSCO Oscillator output for the synchronization circuits 15 XfH Clock output for synchronizing signal circuits MN6761S Pin Descriptions (continued) Pin No. 16 Symbol VR Pin Name Vertical reset output For Video Equipment Function Description This pin generates a vertical reset pulse for the V-SERATION interval detected in the GLSYNC signal. Connect it to the VR pin of the synchronizing signal generator. 25 SCPCO Subcarrier phase comparator output This pin is at "L" level when the SC1 signal leads the GLBSC signal and is at "H" level when the signal lags. At all other times, it is in the high-impedance state. Clock oscillator pins for the subcarrier circuits. Connect these pins to a crystal oscillator, capacitor, and variable capacitor. (The pins have built-in feedback resistors.) The circuit oscillates during external synchronization mode. The oscillation stops for internal synchronization mode. The oscillator frequency, 4fSC , is 14.31818 MHz for NTSC and 14.734 MHz for PAL. 26 4f SCOSCI Oscillator input for subcarrier circuits 27 4fSCOSCO Oscillator output for subcarrier circuits 28 4fSC Subcarrier clock output Clock output from subcarrier circuits. In external synchronization mode, this pin provides the (4f SC) clock signal; in internal synchronization mode, it remains at "L" level. Connect this pin to the EX4fSCI pin on the synchronizing signal generator. 18 LSWCONT Line switch polarity control output During PAL operation, this pin emits an error detection pulse if the LSW polarity is wrong, and the chip reverses the LSW polarity. During internal synchronization mode, this pin remains at "L" level. Connect this pin to the LSWCONT pin on the synchronizing signal generator. 19 EXT/INT Automatic internal/ external switching output If the chip detects GLSYNC input, it switches to external synchronization mode and drives this pin at "H" level. Otherwise, it switches to internal synchronization mode and drives this pin at "L" level. Connect this pin to the EXT/INT pin on the synchronizing signal generator. 5 BGP Burst gate pulse output These pulses have a width of 2.5 µs (NTSC) or 2.3 µs (PAL) and trail the rising edge of the HSYNC signal by 5.3 µs (NTSC) or 5.6 µs. They are generated for only 10 H to 256 H (NTSC) or 304 H (PAL) after the VR pulse. 20 21 10 HBLK TEST1 TEST2 Horizontal blanking output Test inputs These pulses have a width of 8.9 µs (NTSC) or 8.8 µs (PAL) and follow the rising edge of the HSYNC signal. Leave these test inputs open. (The pins include built-in pull-up resistors.) For Video Equipment Timing Chart 1. Horizontal synchronization block MN6761S This block compares the phases of the HSYNC signal derived by separating off the horizontal component of the GLSYNC input and the WHD signal from the synchronizing signal generator after it has passed through the monostable multivibrator. It is thus possible to adjust the horizontal phase by adjusting the CR integral circuit's time constant. GLSYNC HSYNC WHD DELAY WHD Timing chart for horizontal pulse phase comparison 2. Vertical synchronization block This block detects the V-SERATION interval in the GLSYNC input and generates a vertical reset (VR) pulse with 0.5 H of the start of that interval. It then issues no pulses for 256 H (NTSC) or 304 H (PAL) after this VR pulse. GLSYNC VR 2.2µs (NTSC) 1.8µs (PAL) 14.0µs (NTSC) 11.2µs (PAL) Vertical reset pulse timing chart MN6761S 3. Subcarrier synchronization block For Video Equipment This block converts the SC1 output from the synchronizing signal generator into four signals with the same frequency as the burst subcarrier, but different phases. In this phase-locked loop circuit, the phase of GLBSC is compared with the phase selected by 2 bits (SCPSW1 and SCPSW2). During PAL operation, if the LSW polarity is wrong, this block sends an error detection pulse (LSWCONT) to the synchronizing signal generator and reverses the LSW polarity. It also adjusts the relationship between fields 1 through 4. 4. Oscillator blocks The Xf H and 4fSC oscillator blocks operate only during external synchronization mode. Connecting a variable capacitor creates voltage-controlled oscillators that generate the synchronization signal circuit clock (XfH) and subcarrier circuit clock (4f SC) for output to the synchronization signal generator. 5. Automatic internal/external switching block If it detects a minimum of ten edges from the GLSYNC input, this block switches the chip to the external synchronization mode and drives the EXT/INT pin at "H" level. If there are no edges in the GLSYNC input for 10 H, this block switches the chip to the internal synchronization mode and drives this pin at "L" level. HBLK and BGP plus generator GLSYNC HBLK BGP 5.3µs (NTSC) 5.6µs (PAL) 2.5µs (NTSC) 2.3µs (PAL) 8.9µs (NTSC) 8.8µs (PAL) HBLK and BGP pulse timing chart There is an HBLK pulse for each H. BGP pulses are generated for only 10 H to 256 H (NTSC) or 304 H (PAL) after the VR pulse. 5V VBS 2.2µH 2.2µH 2.2µH For Video Equipment 2.2µH 100kΩ 10µF 10000pF 100kΩ + 10µF + Application Circuit Example 1. External synchronization for NTSC system Burst Sep. 10000pF 1kΩ 1kΩ Sync Sep. X1 330pF 330pF 100kΩ X2 1kΩ 18pF 100kΩ + 100kΩ 100kΩ 10µF 10000pF D3 1kΩ D4 10pF 20pF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCPSW1 4fSC SCPSW2 4fSCOSCO WHD 4fSCOSCI N/P SCPCO BGP SC1 VDD1 GLBSC VSS2 VSS1 VDD2 TEST1 HBLK GLSYNC TEST2 EXT/INT LSWCONT fHP LSW HPCO XfHOSCI VR XfHOSCO XfH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD1 VSS1 EX4fSCI 4fSCOSCI 4fSCOSCO SC1 SC2 BSC VPCO EXT/INT CP1 TEST VR EX910fHI VDD2 VSS2 SYNC VP WHD BLK CP1V CP2 WBLK BF SW1 SW2 SW3 SW4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SYNC VP WHD BLK CP1V CP2 WBLK BF 10kΩ 50kΩ 100kΩ 1kΩ 10000pF SC1 + 22Ω 220kΩ 10000pF 330pF 1000pF 100pF 39000pF 10kΩ MN6761S 3kΩ MN67601NS 180pF 47pF 10µF 330pF 100kΩ 3kΩ 43kΩ + 2.2µF 10kΩ D2 D1 2SK128 2SK198 14.31818MHz X1,2 D1 to 4 1SV153 MN6761S MN6761S 5V VBS 2.2µH 2.2µH 2.2µH 2.2µH 100kΩ 10µF 10000pF 10µF + 100kΩ + Application Circuit Example 2. External synchronization for PAL system Burst Sep. 10000pF 1kΩ 330pF 330pF 7.5kΩ 1kΩ Sync Sep. X1 X2 1kΩ 18pF 100kΩ 100kΩ 100kΩ + D4 20pF 10pF 100kΩ 10µF 10000pF D3 SYNC VP WHD BLK CP1V CP2 WBLK BF 10kΩ 50kΩ 12pF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 330pF SCPSW1 4fSC SCPSW2 4fSCOSCO WHD 4fSCOSCI N/P SCPCO BGP SC1 VDD1 GLBSC VSS2 VSS1 VDD2 TEST1 HBLK GLSYNC TEST2 EXT/INT LSWCONT fHP LSW HPCO XfHOSCI VR XfHOSCO XfH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD1 VDD2 VSS1 VSS2 SYNC EX4fSCI VP 4fSCOSCI WHD 4fSCOSCO BLK SC1 SC2 CP1V BSC CP2 WBLK VPCO BF EXT/INT LSWCONT SCBLK HPCO LSW VR 282fHOSCI EX282fHI 282fHOSCO 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1000pF 1kΩ 10kΩ 15pF Q3 10000pF 1kΩ 1kΩ 100kΩ Q1 1200pF + 22Ω 220kΩ 3kΩ 1kΩ 1kΩ 10000pF 330pF 330pF 1000pF 3kΩ 100pF 39000pF 10kΩ MN6761S Q2 MN67602PS D5 180pF 180pF 2.2µF 47pF 10µF 100kΩ 43kΩ+ 2.2µF 10kΩ D2 D1 SC2 SC1 D1 to 5 1SV153 Q1 to 3 2SK198 17.734MHz X1,2 For Video Equipment 3kΩ For Video Equipment Package Dimensions (Unit: mm) SOP028-P-0375 MN6761S 17.80±0.20 28 15 1.10±0.20 0.15 -0.05 +0.10 7.20±0.20 9.40±0.30 0 to 10° 0.30min. 1 14 2.40max. 2.00±0.20 (0.65) 1.27 0.40±0.10 SEATING PLANE 0.10±0.10