2N7002_R1_00001

2N7002 60V N-Channel Enhancement Mode MOSFET 0.120(3.04) 0.110(2.80) • Advanced Trench Process Technology • Specially Designed for Battery Operated Systems, Solid-State Relays 0.103(2.60) • High Density Cell Design For Ultra Low On-Resistance 0.056(1.40) 0.047(1.20) Drivers : Relays, Displays, Lamps, Solenoids, Memories, etc. • In compliance with EU RoHS 2002/95/EC directives 0.079(2.00) 0.008(0.20) 0.070(1.80) 0.003(0.08) MECHANICALDATA 0.044(1.10) 0.004(0.10)MAX. • Case: SOT-23 Package 0.086(2.20) • RDS(ON), VGS@10V,IDS@500mA=5Ω • RDS(ON), VGS@4.5V,IDS@75mA=7.5Ω 0.006(0.15)MIN. FEATURES 0.035(0.90) • Terminals : Solderable per MIL-STD-750,Method 2026 0.020(0.50) 0.013(0.35) • Marking : S72 Maximum Ratings and Thermal Characteristics (TA=25OC unless otherwise noted ) PA RA ME TE R S ymb o l L i mi t Uni t s D ra i n-S o urc e Vo lt a g e V DS 60 V G a t e - S o urc e Vo lt a g e V GS +20 V C o nt i nuo us D r a i n C urr e nt ID 250 mA P uls e d D ra i n C urr e nt ID M 1300 mA PD 350 210 mW T J ,T S TG -5 5 to + 1 50 R θJ A 357 1) M a xi mum P o we r D i s s i p a t i o n O p e ra t i ng J unc ti o n a nd S t o ra g e Te mp e ra t ur e Ra ng e Junction-to Ambient Thermal Resistance(PCB mounted)2 T A = 2 5 OC T A = 7 5 OC O O C C /W Note: 1. Maximum DC current limited by the package 2. Surface mounted on FR4 board, t < 10 sec PAN JIT RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE November 01,2010-REV.02 PAGE . 1 2N7002 ELECTRICALCHARACTERISTICS P a r a me te r S ym b o l Te s t C o nd i ti o n M i n. Typ . Ma x. Uni ts D ra i n- S o urc e B re a k d o wn Vo lta g e B V DSS V G S = 0 V, I D = 1 0 μA 60 - - V Ga te Thr e s ho ld Vo lta g e V G S ( th) V D S = V GS , I D =2 5 0 μ A 1 - 2.5 V D ra i n- S o urc e On-S ta te Re s i s ta nc e R D S ( o n) VGS=4.5V, I D=75mA - - 7 .5 D ra i n- S o urc e On-S ta te Re s i s ta nc e R D S ( o n) VGS=10V, I D=500mA - - 5 Ze ro Ga te Vo lt a g e D r a i n C urr e nt ID S S VDS=60V, VGS=0V - - 1 μA Gate Body Leakage IG S S V GS = +2 0 V, V D S = 0 V - - +100 nA Forward Transconductance g fS V D S = 1 5 V, ID = 2 5 0 m A 200 - - mS - 0 .6 0 .7 - 0 .1 - - 0 .0 8 - - 9 15 - 21 26 - - 50 - - 25 - - 5 S ta ti c Ω Dynamic To ta l Ga te C ha r g e Qg Ga t e -S o ur c e C ha r g e Q gs Ga te -D ra i n C ha r g e Q gd Tur n-On Ti me ton Tur n-Off Ti me t o ff Inp ut C a p a c i ta nc e C i ss Outp ut C a p a c i ta nc e C oss Re ve rs e Tra ns fe r C a p a c i ta nc e C rs s V D S = 1 5 V, ID = 5 0 0 m A VDD=4.5V VDD=10V , RL=20Ω ID=500mA , VGEN=10V RG=10Ω V D S = 2 5 V, V G S = 0 V f = 1 .0 M H Z nC ns pF S o ur c e -D r a i n D i o d e M a x. D i o d e F o rwa r d C ur re nt D i o d e F o rwa r d Vo lta g e Is - - - 250 mA V SD I S = 2 5 0 mA , V G S = 0 V - 0 .9 3 1 .2 V VDD Switching Test Circuit VIN VDD Gate Charge Test Circuit RL VGS RL VOUT RG 1mA RG November 01,2010-REV.02 PAGE . 2 2N7002 O Typical Characteristics Curves (TA=25 C,unless otherwise noted) 1.2 V GS= 6.0~10V 1 ID - Drain Source Current (A) ID - Drain-to-Source Current (A) 1.2 5.0V 4.0V 0.8 0.6 0.4 3.0V 0.2 0 0 1 2 3 4 0.8 0.6 0.4 0 0 5 1 2 3 4 5 6 VGS - Gate-to-Source Voltage (V) Fig. 1-TYPICAL FORWARD CHARACTERISTIC FIG.1- Output Characteristic FIG.2- Transfer Characteristic 10 RDS(ON) - On-Resistance ( W ) 5 RDS(ON) - On-Resistance ( W ) o T J=25 C 0.2 VDS - Drain-to-Source Voltage (V) 4 3 V GS = 4.5V 2 1 VGS=10V 0 I D =500mA 8 6 T J=125 oC 4 2 o T J=25 C 0 0 0.2 0.4 0.6 0.8 1 1.2 FIG.3- On Resistance vs Drain Current 2 1.8 2 3 4 5 6 7 8 9 10 V GS - Gate-to-Source Voltage (V) ID - Drain Current (A) RDS(ON) - On-Resistance(Normalized) VDS =10V 1 FIG.4- On Resistance vs Gate to Source Voltage VGS =10V ID =500mA 1.6 1.4 1.2 1 0.8 0.6 0.4 -50 -25 0 25 50 75 100 125 150 o TJ - Junction Temperature ( C) FIG.5- On Resistance vs Junction Temperature November 01,2010-REV.02 PAGE . 3 2N7002 Qg Qsw Vgs(th) 10 V GS - Gate-to-Source Voltage (V) Vgs 8 6 4 2 0 Qg(th) Qgs 0 Qg Qgd VDS=15V ID=500mA 0.2 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 125 150 73 71 70 69 68 67 66 65 64 -50 -25 C - Capacitance (pF) IS - Source Current (A) T J=-55 oC 0.1 1 1.2 1.4 1.6 125 150 60 50 1.8 VSD - Source-to-Drain Voltage (V) Fig.10 - Source-Drain Diode Forward Voltage Ciss 40 30 20 10 0.8 100 f = 1MHz V GS = 0V 70 TJ =125 oC November 01,2010-REV.02 75 80 o T J=25 C 0.6 50 Fig.9 - Breakdown Voltage vs Junction Temperature VGS = 0V 0.4 25 TJ - Junction Temperature ( C) Fig.8 - Threshold Voltage vs Temperature 0.01 0.2 0 o TJ - Junction Temperature ( C) 1 1 I D = 250 m A 72 o 10 0.8 Fig.7 - Gate Charge BVDSS - Breakdown Voltage (V) Vth - G-S Th r esh o l d Vo l tag e (NORMA L IZED) ID =250 m A 0.6 Qg - Gate Charge (nC) Fig.6 - Gate Charge Waveform 1.2 0.4 0 Coss Crss 0 5 10 15 20 25 VDS - Drain-to-Source Voltage (V) Fig.11 - Capacitance vs Drain to Source Voltage PAGE . 4 2N7002 MOUNTING PAD LAYOUT SOT-23 ORDER INFORMATION • Packing information T/R - 12K per 13" plastic Reel T/R - 3K per 7” plastic Reel LEGAL STATEMENT Copyright PanJit International, Inc 2011 The information presented in this document is believed to be accurate and reliable. The specifications and information herein are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its produ cts for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any license under its patent rights or rights of others. November 01,2010-REV.02 PAGE . 5