PJDLC05C-02

PJDLC05C-02 VOLTAGE 5.0 Volts POWER 200 Watts 0.006(0.15)MIN. 0.008(0.20) 0.003(0.08) 0.044(1.10) 0.035(0.90) 0.020(0.50) 0.013(0.35) ULTRA LOW CAPACITANCE DUAL TRANSIET VOLTAGE SUPPRESSOR FOR HIGH SPEED DATA LINES This transient overvoltage suppressor is intended to protect sensitive equipment against electrostatic discharge events as well to offer a minimum insertion loss in data transmission lines in communications ports used in portable consumer, computing and networking applications. This dual transient voltage suppressor comes in a single SOT-23, offering board space reduction, where the application requires it. This device comes with two pairs of high speed switching diodes connected in series, where both pairs are electrically isolated, offering a very low capacitance, minimizing the insertion losses in data transmission lines. 0.056(1.40) 0.047(1.20) 0.120(3.04) 0.110(2.80) 0.079(2.00) 0.070(1.80) FEATURES • Maximum capacitance @ 0 Vdc Bias of 1.0 pF between terminals 1-3 or terminals 2-3 • IEC61000-4-2 esd 15kV Air, 8kV contact compliance • In compliance with EU RoHS 2002/95/EC directives 0.004(0.10)MAX. MECHANICAL DATA • Case: SOT-23, plastic • Terminals: solderable per MIL-STD-750, Method 2026 • Approx. Weight: 0.0003 ounce, 0.0084 gram • Marking : DAA Fig.21 MAXIMUM RATINGS PARAMETER Op e ra ti ng J unc ti o n S to ra g e Te m p e ra ture Ra ng e SYMBOL TJ T S TG VALUE -55 to +150 -55 to +150 UNITS O C C O ELECTRICAL CHARACTERISTICS PJDLC05C-02 PARAMETER Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Junction Capacitance Peak Pulse Current Max Clamping Voltage SYMBOL VRWM VBR IR CJ I PP VC CONDITIONS I T=1mA VRWM = 5V, T = 25OC Between pin1.2 to 3 VR=0V,f=1MHz t P=8/20 μsec t P=8/20 μsec Min. 6 Typ. Max. 5 20 1.0 10 20.5 UNITS V V μA pF A V PAN JIT RESERVES THE RIGHT TO CHANGE THE SPECIFICATION ANY TIME WITHOUT NOTICE IN ORDER TO IMPROVE THE DESIGN AND SUPPLY THE BEST POSSIBLE PRODUCT. February 16,2010-REV.02 PAGE . 1 PJDLC05C-02 0.7 18 0.65 Peak Pulse Current Ipp , A Cap ac i tan c e CJ , p F 5 7 9 11 13 15 17 19 21 23 25 16 14 12 10 8 6 4 2 0 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0 1 2 3 4 5 Clamping Voltage V C, V FIG.1- TYPICAL CLAMPING VOLTAGE Reverse Bias Voltage, V FIG.2- TYPICAL JUNCTION CAPACITANCE UNDER BIAS I R, Reverse Leakage Current( m A) 1 VR =5V 0.1 0.01 20 40 60 80 100 120 140 160 T J , Junction Temperature (°C) FIG.3- TYPICAL LEAKAGE CURRENT JUNCTION TEMPERATURE February 16,2010-REV.02 PAGE . 2 PJDLC05C-02 MOUNTING PAD LAYOUT SOT-23 ORDER INFORMATION • Packing information T/R - 12K per 13" plastic Reel T/R - 3K per 7” plastic Reel LEGAL STATEMENT Copyright PanJit International, Inc 2011 The information presented in this document is believed to be accurate and reliable. The specifications and information herein are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any license under its patent rights or rights of others. February 16,2010-REV.02 PAGE . 3