PJESD6V8LCQ5G

PJESD5V6LCQ5G Series 5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION This 5-TVS array has been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry, operating at 3.3V and 5V Systems. This TVS array offers an integrated solution to protect up to 5 data lines where the board space is a premium. 6 5 4 SPECIFICATION FEATURES 15W Power Dissipation (8/20µs Waveform) Low Leakage Current, Maximum of 0.5µA @ V WRM Very low Off-State Capacitance, Maximum of 10pF at 1MHz 0Vdc IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance 100% Tin plated finish (LEAD FREE) RoHS Compliant New SMT package QFN 1.6mm x 1.6mm; Max Height of 0.75mm Same Footprint compared to the SOT563 1 2 3 6 5 4 1 2 3 APPLICATIONS Personal Digital Assistant (PDA) MP3 Players Portable Global positioning Systems Port Mobile Phones and Accessories Memory Card Port Protection 1 3 2 QFN 2X2 6 5 4 QFN 1.6x1.6 sq mm Package MAXIMUM RATINGS (Per Device) Rating Peak Pulse Power (8/20µs Waveform) ESD Voltage (HBM) Operating Temperature Range Storage Temperature Range Symbol P pp V ESD TJ Tstg Value 15 >25 -55 to +150 -55 to +150 Units W kV °C °V ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C PJESD5V6LCQ5G Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20µs) Clamping Voltage (8/20µs) Off State Junction Capacitance Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj Cj I BR = 1mA VR = 3.3V I pp = 1 A I pp = 2 A 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 3.3 Vdc Bias f = 1MHz Between I/O pins and pin 2 Conditions Min Typical Max 3.3 Units V V µA V V pF pF 5.3 5.6 5.88 0.5 7.0 8.0 9.6 6.2 10 8 10/5/2006 Page 1 www.panjit.com PJESD5V6LCQ5G Series ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C PJESD6V8LCQ5G Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20µs) Clamping Voltage (8/20µs) Off State Junction Capacitance Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj Cj I BR = 1mA VR = 5.0V I pp = 1 A I pp = 2 A 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 5 Vdc Bias f = 1MHz Between I/O pins and pin 2 Conditions Min Typical Max 5.0 Units V V µA V V pF pF 6.2 6.8 7.2 0.5 9 10 9.1 5.0 10 6 TYPICAL CHARACTERISTICS 25°C unless otherwise noted Surge Pulse Waveform Definition Pulse Waveform 110 100 90 80 70 60 50 40 30 20 10 0 0 Clamping Voltage vs. Peak current 10 Percent of Ipp 50% of Ipp @ 20µs Clamping voltage, V 9 6V8 8 7 6 5V6 Rise time 10-90% - 8µs 5 10 15 time, µsec 20 25 30 1 1.2 1.4 1.6 1.8 2 Ipp, A (8/20µsec) Off-State junction Capacitance 0.1000 Typical Leakage Current vs Temperature 12 10 Capacitance, pF Current, µA 8 6 4 2 0 0 1 2 6V8 5V6 0.0100 5V 0.0010 3V 0.0001 3 4 5 25 50 75 Temp,°C 100 125 150 Bias Voltage, Vdc 10/5/2006 Page 2 www.panjit.com PJESD5V6LCQ5G Series TYPICAL APPLICATION EXAMPLE I/O Data lines Ground (Pin 2) Marking Code Information Device Marking Code PJESD5V6LCQ5G QE PJESD6V8LCQ5G QG 10/5/2006 Page 3 www.panjit.com PJESD5V6LCQ5G Series PACKAGE DIMENSIONS AND SUGGESTED BOND PAD LAYOUT TOP VIEW 1.60 ± 0.05 mm BOTTOM VIEW 0.50 ± 0.05 mm 0.20 ± 0.05 mm 1.60 ± 0.05 mm QE 0.20 ± 0.05 mm 1.1 ± 0.05 mm 0.6 ± 0.05 mm SIDE VIEW 0.203 ± 0.05 mm 0.75 ± 0.05 mm PREFERRED 0.25 ± 0.05 mm ALTERNATE 0.25 ± 0.05 mm 0.40 ± 0.05 mm 0.40 ± 0.05 mm 0.90 ± 0.05 mm 0.55 mm 1.0 ± 0.05 mm 0.50 ± 0.05 mm 1.00 ± 0.05 mm 0.50 ± 0.05 mm © Copyright PanJit International, Inc 2006 The information presented in this document is believed to be accurate and reliable. The specifications and information herein are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any license under its patent rights or rights of others. 10/5/2006 Page 4 www.panjit.com