PJQMS05 SERIES
QUAD TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This Quad TVS/Zener Array family have been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry operating at 5V, 12V, 15V and 24V. This TVS array offers an integrated solution to protect up to 4 data lines where the board space is a premium.
7
SPECIFICATION FEATURES
350W Power Dissipation (8x20µsec Waveform) Low Leakage Current, Maximum of 5µA at rated voltage Very Low Clamping Voltage IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance New SMT package QFN 2mm x 2mm (Height 0.75mm) Compatible with the SOT363 footprint.
4 5 6
3 2 1
7
7
4 5
APPLICATIONS
Personal Digital Assistant (PDA) SIM Card Port Protection (Mobile Phone) Portable Instrumentation Mobile Phones and Accessories Memory Card Port Protection
6 3 2 1
QFN 2X2 Bottom View
MAXIMUM RATINGS (Per Device)
Rating Peak Pulse Power (8x20µsec Waveform) ESD Voltage (HBM) Operating Temperature Range Storage Temperature Range Symbol P pp V ESD TJ Tstg Value 350 >25 -50 to +125 -50 to +150 Units W kV °C °C
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
PJQMS05
Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8x20µsec) Clamping Voltage (8x20µsec) Off State Junction Capacitance Off State Junction Capacitance Symbol VWRM VBR IR Vcl Vcl Cj Cj I BR = 1mA VR = 5V I pp = 5A I pp = 24A
0 Vdc Bias f = 1MHz Between I/O pins and pin 7 5 Vdc Bias f = 1MHz Between I/O pins and pin 7
Conditions
Min
Typical
Max 5
Units V V
6 5 9.8 13 225 125
µA V V pF pF
4/19/2005
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PJQMS05 SERIES
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
PJQMS12
Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8x20µsec) Clamping Voltage (8x20µsec) Off State Junction Capacitance Symbol VWRM VBR IR Vcl Vcl Cj I BR = 1mA VR = 12V I pp = 5A I pp = 15A
0 Vdc Bias f = 1MHz Between I/O pins and pin 7
Conditions
Min
Typical
Max 12
Units V V
13.3 1 20 25 100
µA V V pF
PJQMS15
Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8x20µsec) Clamping Voltage (8x20µsec) Off State Junction Capacitance Symbol VWRM VBR IR Vcl Vcl Cj I BR = 1mA VR = 15V I pp = 5A I pp = 12A
0 Vdc Bias f = 1MHz Between I/O pins and pin 7
Conditions
Min
Typical
Max 15
Units V V
16.7 1 24 29 80
µA V V pF
PJQMS24
Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8x20µsec) Clamping Voltage (8x20µsec) Off State Junction Capacitance Symbol VWRM VBR IR Vcl Vcl Cj I BR = 1mA VR = 24V I pp = 5A I pp = 8A
0 Vdc Bias f = 1MHz Between I/O pins and pin 7
Conditions
Min
Typical
Max 24
Units V V
26.7 1 40 44 60
µA V V pF
4/19/2005
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PJQMS05 SERIES
TYPICAL CHARACTERISTICS
TJ = 25°C unless otherwise noted
Surge Pulse Waveform Definition
N on-R epetitive Peak Pulse Power vs Pulse Time
Pulse Waveform
Peak Pulse Power - Ppp (W)
110 100 90 80 70 60 50 40 30 20 10 0 0
1000 100 10 1 0.1 0.01 1 10 100 1000 Pulse D uration, µsec
Percent of Ipp
50% of Ipp @ 20µs
Rise time 10-90% - 8µs
5
10
15 tim e, µsec
20
25
30
Clamping Voltage vs. Peak current 45 40 35 30 25 20 15 10 5 0 0 5
Off-State Capacitance per Device - 1MHz 200 180 160 140 120 100 80 60 40 20 0 0
Clamping voltage, V
PJS 24 MS PJQMS24
PJQMS05 PJSMS05
PJS 15 MS PJQMS15 PJS 12 MS PJQMS12
PJQMS05 PJS 05 MS
Capacitance, pF
PJQMS12 PJSMS1 2
PJQMS15 PJSMS1 5
PJQMS24 PJSMS24
10
15
20
25
30
1
2
3
4
5
Ipp, A (8/20µsec)
Bias, Vdc
4/19/2005
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PJSMS05 SERIES
TYPICAL APPLICATION EXAMPLE AND PACKAGE DIMENSIONS (in mm)
4
7
7
5 6 3
4
5
3
2
1
2
SUGGESTED PAD LAYOUT
6
1
7
I/O Data Line 1 I/O Data Line 2 I/O Data Line 3 I/O Data Line 4
Note: pin 2 and pin 7 could be fused with the pin 7 in order to make ground connection to these pins.
0.35 ± 0.05 mm
2.0 ± 0.05mm
0.25 ± 0.05mm
0.65mm
0.8 ± 0.05 mm
0.75 ± 0.025 mm
0.203 ± 0.025 mm
4/19/2005
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1.550mm Ref.
1.4 ± 0.05mm
2.0 ± 0.05 mm
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