PJSRV05-4

PJSRV05-4, PJSRV05W-4 Low Capacitance TVS and Diode Array This diode array is configured to protect up to four data transmission lines acting as a line terminator, minimizing overshoot and undershoot conditions due to bus impedance as well as protect against over-voltage events as electrostatic discharges. Additionaly the TVS Device offers overvoltage transient protection between the operating voltage bus and ground plane. 4 6 3 SPECIFICATION FEATURES 1 Peak Power Dissipation of 350W 8/20µs Maximum Capacitance of 5pF at 0Vdc 1MHz Line-to-Ground Maximum Leakage Current of 5µA @ VRWM Available in SOT23-6L and SOT363 packages IEC61000-4-2, IEC61000-4-4 and IEC61000-4-5 Full Compliance 100% Tin Matte finish (LEAD-FREE PRODUCT) 6 SOT26 4 3 1 APPLICATIONS USB 2.0 and Firewire Port Protection LAN/WLAN Access Point terminals Video Signal line protection I C Bus Protection Touch Panel Controller lines protection I/O4 I/O3 SOT363 4 3 I/O2 REF1 5 2 REF2 2 6 1 I/O1 Device PJSRV05-4 PJSRV05W-4 Marking Code 054 W5 MAXIMUM RATINGS Tj = 25°C Unless otherwise noted Rating Peak Pulse Power (8/20µs Waveform) Peak Pulse Current (8/20µs Waveform) Operating Junction Temperature Range Storage Temperature Range Soldering Temperature, t max = 10s Symbol P PPM I PP TJ Tstg TL Value 350 20 -55 to +150 -55 to +150 260 Units W A °C °C °C 9/1/2006 Page 1 www.panjit.com PJSRV05-4, PJSRV05W-4 ELECTRICAL CHARACTERISTICS Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20µs) Clamping Voltage (8/20µs) Clamping Voltage (8/20µs) Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Vc Cj I BR = 1mA VR = 5V I pp = 3A I pp = 12A I pp = 20A 0 Vdc Bias f = 1MHz Between I/O pins and GND 0 Vdc Bias f = 1MHz Between I/O pins Tj = 25°C unless otherwise noted Conditions Min Typical Max 5 6.2 5 10 15 18 4 2 5 3 Units V V µA V V V pF pF TVS Clamping Voltage vs Ipp 8/20µs Surge Pulse Waveform Definition Pulse Waveform 110 100 90 80 70 60 50 40 30 20 10 0 0 30 Peak Surge Current, A 25 20 15 10 5 0 8 10 12 14 16 18 20 Clamping Voltage, V TA = 25°C Percent of Ipp 50% of Ipp @ 20µs Rise time 10-90% - 8µs 5 10 15 time, µsec 20 25 30 Off-State Capacitance vs Vdc @ 1MHz (L-GND) 6 5 Capacitance, pF 4 3 2 1 0 0 1 2 3 4 5 Bias Voltage, Vdc 9/1/2006 Page 2 www.panjit.com PJSRV05-4 PACKAGE DIMENSIONS TYPICAL APPLICATION CONFIGURATION D + (1) D - (1) USB2.0 Port1 I/O3 4 3 I/O2 Vbus + REF1 5 2 REF2 Gnd PJSRV05-4 I/O4 6 1 I/O1 D + (2) USB2.0 Port2 D - (2) © Copyright PanJit International, Inc 2006 The information presented in this document is believed to be accurate and reliable. The specifications and information herein are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any license under its patent rights or rights of others. 9/1/2006 Page 3 www.panjit.com