3341-56

Product Specification PE3341 2700 MHz Integer-N PLL with Field-Programmable EEPROM Product Description Features The PE3341 is a high performance integer-N PLL with embedded EEPROM capable of frequency synthesis up to 2700 MHz with a speed-grade option to 3000 MHz. The EEPROM allows designers to permanently store control bits, allowing easy configuration of self-starting synthesizers. The superior phase noise performance of the PE3341 is ideal for applications such as sonet, wireless base stations, fixed wireless, and RF instrumentation systems. • Field-programmable EEPROM for self- starting applications • Standard 2700 MHz operation, 3000 MHz speed-grade option • ÷10/11 dual modulus prescaler • Internal charge pump • Serial programmable The PE3341 features a ÷10/11 dual modulus prescaler, counters, a phase comparator, and a charge pump as shown in Figure 1. Counter values are programmable through a threewire serial interface. • Low power — 20 mA at 3 V • Ultra-low phase noise e • Available in 20-lead 4x4 mm QFN package ol et The PE3341 UltraCMOS™ Phase Locked-Loop is manufactured in Peregrine’s patented Ultra Thin Silicon (UTSi®) CMOS process, offering excellent RF performance with the economy and integration of conventional CMOS. Fin Fin O Prescaler ÷10/11 ENH Enhancement Register (8-bit) E_WR Data Clock bs Figure 1. Block Diagram Serial Interface Mux Primary Register (20-bit) 20 EE Register (20-bit) EELoad Secondary Register (20-bit) M Counter ÷2 to ÷512 13 PD_U CP PD_D 20 6 20 LD Transfer Logic 2k Cext 6 VPP S_WR fr Charge Pump Phase Detector EEPROM R Counter ÷1 to ÷64 EESel FSel Document No. 70-0053-05 │ www.psemi.com ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Figure 2. Pin Configuration (Top View) Figure 3. Package Type ENH VDD fr EESel NC 20 19 18 17 16 20-lead QFN 1 15 CP Data 2 VDD Clock 3 20-lead QFN 4x4 mm 14 13 4 Exposed Solder Pad (Bottom Side) Dout FSel 12 LD E_WR 5 11 EELoad 7 8 9 FIN FIN CEXT 6 VPP VDD 10 S_WR Table 2. Pin Descriptions Pin No. Pin Name Type Description Secondary Register WRITE input. Primary Register contents are copied to the Secondary Register on S_WR rising edge. Also used to control Serial Port operation and EEPROM programming. Binary serial data input. Input data entered LSB (B0) first. S_WR Input 2 Data Input 3 Clock Input Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit EE Register, or the 8-bit Enhancement Register on the rising edge of Clock. Also used to clock EE Register data out Dout port. 4 FSel Input Frequency Register selection control line. Internal 70 kW pull-down resistor. 5 E_WR Input 6 VPP Input 7 VDD (Note 1) Enhancement Register write enable. Also functions as a Serial Port control line. Internal 70 kW pulldown resistor. EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass capacitor connected to GND. Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required. 8 Fin Input Prescaler input from the VCO. 9 Fin Input 10 CEXT Output 11 EELoad Input 12 LD Output, OD 13 Dout Output Data out function. Dout is defined with the Enhancement Register and enabled with ENH. 14 VDD (Note 1) Same as pin 7. 15 CP Output Charge pump output. Sources current is when fc leads fp and sinks current when fc lags fp. 16 N/C 17 EESel Input Control line for Frequency Register selection, EE Register parallel loading, and EEPROM programming. Internal 70 kW pull-up resistor. 18 fr Input Reference frequency input. 19 VDD (Note 1) Same as pin 7. 20 ENH Input Enhancement mode control line. When asserted LOW, enhancement register bits are functional. Internal 70 kW pull-up resistor. bs ol et e 1 O Prescaler complementary input. A series 50 W resistor and DC blocking capacitor should be placed as close as possible to this pin and connected to the ground plane. Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2 kW series resistor. Connecting CEXT to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. Control line for Serial Data Port, Frequency Register selection, EE Register parallel loading, and EEPROM programming. Internal 70 kW pull-down resistor. Lock detect output, an open-drain logical inversion of C EXT. When the loop is in lock, LD is high impedance; otherwise, LD is a logic LOW. No connection. Notes 1: VDD pins 7, 14 and 19 are connected by diodes and must be supplied with the same positive voltage level. 2: Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation. ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0053-05 │ UltraCMOS™ RFIC Solutions Page 2 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Table 5. ESD Ratings Table 3. Absolute Maximum Ratings Symbol VDD VI TStg Parameter/Conditions Min Max Units Symbol Parameter/Conditions Supply voltage –0.3 +4.0 V VESD –0.3 VDD+0.3 V –65 +85 °C ESD voltage human body model (Note 1) ESD voltage human body model (Note 1) Voltage on any digital input Storage temperature range VESD (VPP) VDD Supply voltage 2.85 3.15 V TA Operating ambient temperature range -40 85 °C 200 V When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating in Table 4. e Units V Latch-Up Avoidance et Max 1000 Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. O bs ol Min Units Electrostatic Discharge (ESD) Precautions Table 4. Operating Ranges Parameter/Conditions Max Note 1: Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Symbol Min Document No. 70-0053-05 │ www.psemi.com ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Table 6. DC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol IDD Parameter Conditions Operational supply current; Prescaler enabled Min VDD = 2.85 to 3.15 V Typ Max Units 20 30 mA Digital Inputs: S_WR, Data, Clock VIH High-level input voltage VDD = 2.85 to 3.15 V VIL Low-level input voltage VDD = 2.85 to 3.15 V IIH High-level input current VIH = VDD = 3.15 V IIL Low-level input current VIL = 0, VDD = 3.15 V -1 µA 0.7 x VDD V 0.7 x VDD V 0.3 x VDD +1 V µA Digital inputs: ENH, EESel (contains a 70 kΩ pull-up resistor) High-level input voltage VDD = 2.85 to 3.15 V VIL Low-level input voltage VDD = 2.85 to 3.15 V IIH High-level input current VIH = VDD = 3.15 V IIL Low-level input current VIL = 0, VDD = 3.15 V Digital inputs: FSel, EELoad, E_WR (contains a 70 kΩ pull-down resistor) High-level input voltage VDD = 2.85 to 3.15 V VIL Low-level input voltage VDD = 2.85 to 3.15 V IIH High-level input current VIH = VDD = 3.15 V IIL Low-level input current VIL = 0, VDD = 3.15 V VPP_ERASE EEPROM erase voltage IPP_WRITE EEPROM write cycle current IPP_ERASE EEPROM erase cycle current O Reference Divider input: fr ol EEPROM write voltage +1 µA µA IIHR High-level input current VIH = VDD = 3.15 V IILR Low-level input current VIL = 0, VDD = 3.15 V 0.7 x VDD V 0.3 x VDD V +100 µA µA -1 12.5 bs VPP_WRITE V -100 et VIH EE Memory Programming Voltage and Current: VPP, IPP 0.3 x VDD e VIH V -8.5 V 30 -10 mA mA +100 µA µA -100 Counter output: Dout VOLD Output voltage LOW Iout = 6 mA VOHD Output voltage HIGH Iout = -3 mA 0.4 VDD - 0.4 V V Lock detect outputs: (CEXT, LD) VOLC Output voltage LOW, CEXT VOHC Output voltage HIGH, CEXT Iout = -0.1 mA VOLLD Output voltage LOW, LD Iout = 1 mA Iout = 0.1 mA 0.4 VDD - 0.4 V V 0.4 V Charge Pump output: CP ICP – Source Drive current VCP = VDD / 2 -2.6 -2 -1.4 mA ICP – Sink Drive current VCP = VDD / 2 1.4 2 2.6 mA Leakage current 1.0 V < VCP < VDD – 1.0 V -1 1 µA Sink vs. source mismatch VCP = VDD / 2, TA = 25° C 15 % 1.0 V < VCP < VDD – 1.0 V 15 % ICPL ICP - Source VS. ICP – Sink ICP VS. VCP Output current magnitude variation vs. voltage TA = 25° C ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0053-05 │ UltraCMOS™ RFIC Solutions Page 4 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Table 7. AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Max Units 10 MHz Control Interface and Registers (see Figure 4) fClk Serial data clock frequency tClkH Serial clock HIGH time (Note 1) 30 ns tClkL Serial clock LOW time 30 ns tDSU Data set-up time to Clock rising edge 10 ns tDHLD Data hold time after Clock rising edge 10 ns tPW S_WR pulse width 30 ns tCWR Clock rising edge to S_WR rising edge 30 ns Clock falling edge to E_WR transition 30 ns tCE tWRC tEC S_WR falling edge to Clock rising edge 30 ns E_WR transition to Clock rising edge 30 ns 500 ns EELoad rising edge to V PP rising edge tEEPW VPP pulse width tVPP VPP pulse rise and fall times et tEESU (Note 2) FIn Operating frequency PFIn Input level range Main Divider (Prescaler Bypassed) FIn Operating frequency PFIn Input level range O Reference Divider Speed-grade option (Note 3) bs Operating frequency ol Main Divider (Including Prescaler) FIn e EEPROM Erase/Write Programming (see Figures 5 & 6) ms µs 1 300 2700 MHz 300 3000 MHz -5 5 dBm (Note 4) 50 270 MHz External AC coupling (Note 4) -5 5 dBm 100 MHz fr Operating frequency (Note 5) Reference input power (Note 4) Single ended input Comparison frequency (Note 6) fc 30 External AC coupling Pfr Phase Detector 25 -2 dBm 20 MHz 100 Hz Offset -75 dBc/Hz 1 kHz Offset -85 dBc/Hz SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, V DD = 3.0 V, Temp = -40° C) Note 1: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fClk Note 2: specification. Rise and fall times of the VPP programming voltage pulse must be greater than 1 µs. Note 3: The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14, Note 4: Ordering Information, for ordering details. CMOS logic levels can be used to drive FIn input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum Note 5: frequency limit exists when operated in this mode. CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum Note 6: phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. Parameter is guaranteed through characterization only and is not tested. Document No. 70-0053-05 │ www.psemi.com ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M counter with the minimum value of 1 will result in a minimum M counter divide ratio of 2. Functional Description The PE3341 consists of a dual modulus prescaler, three programmable counters, a phase detector with charge pump and control logic with EEPROM memory (see Figure 1). Programming the M and A counters with their maximum values provides a divide ratio of 5135. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the state of the internal modulus select logic. The R and M counters divide the reference and prescaler outputs by integer values stored in one of three selectable registers. The modulus select logic uses the 4-bit A counter. Prescaler Bypass Mode Setting the PB bit of a frequency register HIGH allows Fin to bypass the ÷10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. The following equation relates Fin to the reference frequency fr: The phase-frequency detector generates up and down frequency control signals that direct the charge pump operation, and are also used to enable a lock detect circuit. (3) e Fin = (M + 1) x (fr / (R+1)) where 1 ≤ M ≤ 511 et Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. ol Frequency control data is loaded into the device via the Serial Data Port, and can be placed in three separate frequency registers. One of these registers (EE register) is used to load from and write to the non-volatile 20-bit EEPROM. O Main Counter Chain bs Various operational and test modes are available through the enhancement register, which is only accessible through the Serial Data Port (it cannot be loaded from the EEPROM). The main counter chain divides the RF input frequency, Fin, by an integer derived from the user-defined values in the M and A counters. It operates in two modes: High Frequency Mode Setting PB (prescaler bypass) LOW enables the ÷10/11 prescaler, providing operation to 2.7 GHz. In this mode, the output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: fp = Fin / [10 x (M + 1) + A] where 0 ≤ A ≤ 15 and A ≤ M + 1; 1 ≤ M ≤ 511 (1) When the loop is locked, Fin is related to the reference frequency, fr, by the following equation: Fin = [10 x (M + 1) + A] x (fr / (R+1)) where 0 ≤ A ≤ 15 and A ≤ M + 1; 1 ≤ M ≤ 511 ©2005-8 Peregrine Semiconductor Corp. All rights reserved. (2) The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) where 0 ≤ R ≤ 63 (4) Note that programming R with 0 will pass the reference frequency, fr, directly to the phase detector. Phase Detector and Charge Pump The phase detector is triggered by rising edges from the main counter (fp) and the reference counter (fc). It has two outputs, PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses LOW. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses LOW. The width of either pulse is directly proportional to the phase offset between the fp and fc signals. The signals from the phase detector are also routed to an internal charge pump. PD_U controls a current source at pin CP, and PD_D controls a current sink at pin CP. When using a positive Kv VCO, PD_U pulses (current source) will increase the VCO frequency, and PD_D pulses (current sink) will decrease VCO frequency. Document No. 70-0053-05 │ UltraCMOS™ RFIC Solutions Page 6 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Lock Detect Output Serial Data Port A lock detect signal is provided at pin LD, via the pin CEXT (see Figure 1). CEXT is the logical “NAND” of PD_U and PD_D waveforms, driven through a series 2k ohm resistor. When the loop is locked, this output will be HIGH with narrow pulses LOW. Connecting CEXT to an external shunt capacitor provides integration of this signal. The Serial Data Port allows control data to be entered into the device. This data can be directed into one of three registers: the Enhancement register, the Primary register, and the EE register. Table 7 defines the control line settings required to select one of these destinations. The CEXT signal is sent to the LD pin through an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. Input data presented on pin 5 (Data) is clocked serially into the designated register on the rising edge of Clock. Data is always loaded LSB (B0) first into the receiving register. Figure 4 defines the timing requirements for this process. EELoad Register Loaded 0 0 0 Primary Register 0 1 0 Enhancement Register 0 X 1 EE Register O Data bs Figure 4. Serial Interface Timing Diagram et E_WR ol S_WR e Table 8. Serial Interface E_WR EELoad tEC tCE Clock S_WR tDSU Document No. 70-0053-05 │ www.psemi.com tDHLD tClkH tClkL tCWR tPW tWRC ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Frequency Registers EE Register There are three independent frequency registers, any one of which can be selected to control the operation of the device. Each register is 20 bits in length, and provides data to the three counters and the prescaler bypass control. Table 8 defines these bit assignments. The EE Register is a serial/parallel-in, serial/ parallel-out register, and provides the interface to the EEPROM. It is loaded from the Serial Data Port to provide the parallel data source when writing to the EEPROM. It also accepts stored data from the EEPROM for controlling the PLL. Primary Register Serial loading of the EE Register is done as shown in Table 7 and Figure 4. Parallel loading of the register from EEPROM is accomplished as shown in Table 10. The Primary Register is a serial shift register, loaded through the Serial Data Port. It can be selected to control the PLL as shown in Table 9. It is not buffered, thus when this register is selected to control the PLL, its data is continuously presented to the counters during a load operation. e The EE register can be selected to control the PLL as shown in Table 9. Note that it cannot be selected to control the PLL using data that has been loaded serially. This is because it must first go through one of the two conditions in Table 10 that causes the EEPROM data to be copied into the EE Register. The effect of this is that only EEPROM data is used when the EE Register is selected. et This register is also used to perform a parallel load of data into the Secondary Register. Secondary Register The contents of the EE register can also be shifted out serially through the Dout pin. This mode is enabled by appropriately programming the Enhancement Register. In this mode, data exits the register on the rising edge of Clock, LSB (B0) first, and is replaced with the data present on the Data input pin. Tables 7 and 12 define the settings required to enable this mode. O bs ol The Secondary Register is a parallel-load register. Data is copied into this register from the Primary Register on the rising edge of S_WR, according to the timing diagrams shown in Figure 3. It can be selected to control the PLL as shown in Table 9. Table 9. Primary / Secondary / EE Register Bit Assignments R5 R4 M8 M7 PB M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Table 10. Frequency Register Selection EESel FSel EELoad Register Selected 0 1 0 Primary Register 0 0 0 Secondary Register 1 X 0 EE Register ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Table 11. EE Register Load from EEPROM EESel EELoad Function _⁄ ¯ 0 EEPROM → EE Register 1 ¯\_ EEPROM → EE Register Document No. 70-0053-05 │ UltraCMOS™ RFIC Solutions Page 8 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Enhancement Register The Enhancement Register is buffered to prevent inadvertent control changes during serial loading. Data that has been loaded into the register is captured in the buffer and made available to the PLL on the falling edge of E_WR. The Enhancement Register is a buffered serial shift register, loaded from the Serial Data Port. It activates special test and operating modes in the PLL. The bit assignments for these modes are shown in Table 11. A separate control line is provided to enable and disable the Enhancement mode. Functions are enabled by taking the ENH control line LOW. Note: The enhancement register bit values are unknown during power up. To avoid enabling the enhancement mode during power up, set the ENH pin high (“1”) until the enhancement register bit values are programmed to a known state. et Table 12. Enhancement Register Bit Assignments e The functions of these Enhancement Register bits are shown in Table 12. A function becomes active when its corresponding bit is set HIGH. Note that bits 1, 2, 5, and 6 direct various data to the Dout pin, and for valid operation no more than one should be set HIGH simultaneously. EE Register Output fp output Power down Counter load MSEL output fc output Reserved B0 B1 B2 B3 B4 B5 B6 B7 bs ol Reserved Table 13. Enhancement Register Functions Description O Bit Function Bit 0 Reserved Program to 0 Bit 1 EE Register Output Bit 2 fp output Bit 3 Power down Powers down all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Provides the internal dual modulus prescaler modulus select (MSEL) at Dout. Bit 6 fc output Bit 7 Reserved Allows the contents of the EE Register to be serially shifted out Dout, LSB (B0) first. Data is shifted on rising edge of Clock. Provides the M counter output at Dout. Provides the R counter output at Dout. Program to 0 Document No. 70-0053-05 │ www.psemi.com ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Write Cycle EEPROM Programming Frequency control data that is present in the EE Register can be written to the non-volatile EEPROM. All 20 bits are written simultaneously in a parallel operation. The EEPROM is guaranteed for at least 100 erase/write cycles. Using the Serial Data Port, the EE Register is first loaded with the desired data. The EEPROM is then programmed with this data by taking the S_WR input HIGH and EESel input LOW, then applying one WRITE programming voltage pulse to the VPP input. The voltage source for this operation must be capable of supplying the EEPROM write cycle current (IPP_WRITE, Table 5). The timing diagram of this operation is shown in Figure 6. Programming is completed by taking the EELoad input LOW. Erase Cycle The EEPROM should be taken through an erase cycle before writing data, since the write operation performs a logical AND of the EEPROM’s current contents with the data in the EE Register. Erasing the EEPROM is accomplished by holding the S_WR, EESel, and EELoad inputs HIGH, then applying one ERASE programming voltage pulse to the VPP input (see Table 13). The voltage source for this operation must be capable of supplying the EEPROM erase cycle current (IPP_ERASE, Table 5). The timing diagram is shown in Figure 5. et e Note that it is possible to erroneously overwrite the EE Register with the EEPROM contents before the write cycle begins by unneeded manipulation of the EELoad bit (see Table 10). ol Table 14. EEPROM Programming EESel EELoad 1 1 1 25ms @ −8.5V VPP Erase cycle Function 1 0 1 25ms @ +12.5V Write cycle bs S_WR O Figure 5. EEPROM Erase Timing Diagram EELoad S_WR EESel tEESU tVPP tVPP tEESU 0V tEEPW VPP_ERASE 8 5V Figure 6. EEPROM Write Timing Diagram EESel 0V EELoad 3V S_WR tEESU tVPP tVPP tEESU tEEPW 12.5V VPP_WRITE 0V ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0053-05 │ UltraCMOS™ RFIC Solutions Page 10 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Gross EEPROM Programming Timing Grid between the Vpp_ERASE and Vpp_WRITE pulse has to be at least 100 ms if mechanical relays are used to avoid both being on at the same time. After EE programming, the contents of the EEPROM cells can be verified by setting Enhancement Register Bit 1. A procedure shown in Figure 8 is applied twice. The first time is to load the EE Register from EEPROM and the second time is to shift out the EE Register contents through Dout pin. Figure 7 shows a gross PE3341 EEPROM programming timing grid although each individual step has been described thoroughly in previous sections. It starts with EE Register load, and then together with other parameters a Vpp_ERASE negative pulse is applied to Vpp pin to erase the EEPROM contents and followed by a Vpp_WRITE pulse for EEPROM write cycle. The separation Figure 7. Gross PE3341 EEPROM Programming Timing Grid >=100 ms EELoad e 3V 0V 3V et EESel 0V 3V ol S_WR 0V 3V bs E_WR 0V 3V Data CHA NNEL CODE 0V O 3V ENH code sets Dout mux to EE Clock 0V 3V The final set of Dout is EEPROM content Dout 0V 0V Vpp_ERASE 25 ms -8.5V 25 ms 12.5V Vpp_WRITE EE PROM Write EE PROM Erase Rough time scale 40 ms Note: ENH/ (Pin 20) is at low (0) for this process. Document No. 70-0053-05 │ www.psemi.com EE verify EE Register load EE Programming 0V EE Register load from EEPROM EE Register shifted out through Dout ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Figure 8. Details of EE register contents loaded from EEPROM and then shifted out Serially through Dout pin - The procedure is performed twice. EELoad 3V 0V 3V EESel 0V S_WR 0V 3V e E_WR 0V 3V et Data 0V 3V ol Clock 0V (example) 0 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1 3V bs Dout 0V Enhancement Register Programming O EE Register load from EEPROM EE Register shifted out through Dout Rough time scale 20 us Note: ENH/ (Pin 20) is at low (0) for this process. In Figure 8, the first step is to program Enhancement Register to set Bit 1 high (“1”) to access EE Register Output Bit Function. Subsequent action, which includes pulses, allows the existing EE Register contents to be shifted out the Dout pin and the EEPROM contents are loaded to the EE Register. Since the initial data existing in the EE Register could be anything, the data must be flushed out before clocking the ©2005-8 Peregrine Semiconductor Corp. All rights reserved. contents of the EEPROM register out. After the same procedures are duplicated, the Dout output is the EEPROM content. Note that only 19 Clock pulses are enough for the 20-bit EE Register because the first bit data is already present at Dout pin. Also ENH/ (Pin 20) is set to low (“0”) to access the Enhancement mode. Document No. 70-0053-05 │ UltraCMOS™ RFIC Solutions Page 12 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Application Information Evaluation and Programming Kit Support The PE3341 has been designed to allow a selfstarting PLL synthesizer to be built, removing the need to have a micro-controller or other programming source load data into the device on power-up. It can be used as a remotely controllable PLL as well, since the EEPROM circuitry has been added to a complete PLL core (PE3339). To provide easy evaluation of the PE3341 and to also enable programming of small evaluation quantities, Peregrine has developed complete evaluation kits and programming kits for the PE3341 EEPROM PLLs. Evaluation Kits The evaluation kits consist of an evaluation board and support software enabling the user to evaluate the full functionality of the part. The EEPROM can be loaded with user specified values and then placed in a self start-up mode. Please refer to Table 14, Ordering Information, for the specific order codes. The PE3341’s EEPROM can be programmed incircuit, or prior to assembly using a socketed fixture. It can be reprogrammed a minimum of 100 times, but is not designed to support constant reprogramming of the EEPROM by an application. e Large production quantities can be special programmed at Peregrine for an additional charge. Please contact Peregrine Sales for pricing and leadtime at sales@psemi.com. O bs ol In self-starting applications, the EE Register is used to control the device and must be selected per Table 9. Additionally, the contents of the EEPROM must be copied to the EE Register per Table 10, and device power must be stable for this transfer to be reliably accomplished. These requirements can be met by connecting a capacitor of 50pF-10uF (evaluation design uses 3.3uF) from the EESel pin to ground. The delay of the rising edge on EESel, created by the RC time constant of its 70k ohm internal pull-up resistor and the external capacitor, will allow device power to stabilize first, ensuring proper data transfer. This edge is adaptable by capacitor value selection. The Vcc applied to the IC must be settled first. The programming kits consist of a programming board and support software that enables the user to program small quantities of devices for prototype evaluation and for small pre-production runs. Please refer to Table 14, Ordering Information, for the specific order codes et Self-Starting Mode Programming Kits Document No. 70-0053-05 │ www.psemi.com ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Figure 9. Package Drawing 20-lead QFN 4.00 INDEX AREA 2.00 X 2.00 2.00 4.00 2.00 -B- 0.25 C 0.90 -A- e 0.10 C 0.08 C 0.20 REF bs 10 5 11 DETAIL A O 0.18 2.00 4.00 0.435 0.18 6 1.00 1.00 TYP 0.55 2.00 TYP 0.50 0.435 -C- 2.00 ol 0.020 et SEATING PLANE EXPOSED PAD & TERMINAL PADS 1 15 EXPOSED PAD 16 20 DETAIL A 2 0.23 1 0.10 C A B 1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP. 2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. Document No. 70-0053-05 │ www.psemi.com ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Figure 10. Marking Specifications 3341 YYWW ZZZZZ et e YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number O bs ol Figure 11. Tape and Reel Drawing Table 15. Ordering Information Order Code Part Marking Description Package Shipping Method 3341-53 PE3341 PE3341G-20QFN4x4-92A Green 20-lead QFN Tape or loose 3341-54 PE3341 PE3341G-20QFN4x4-3000C Green 20-lead QFN 3000 units / T&R 3341-55 PE3341 PE3341-20QFN4x4-92A (3GHz grade) Green 20-lead QFN Tape or loose 3341-56 PE3341 PE3341-20QFN4x4-3000C (3GHz grade) Green 20-lead QFN 3000 units / T&R 3341-05 PE3341-EK PE3341-20QFN4x4-EK Evaluation Kit 1 / Box 3341-07 PE3341-PK PE3341-20MLP4x4-PK Programming Kit 1 / Box ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0053-05 │ UltraCMOS™ RFIC Solutions Page 15 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE3341 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corporation Peregrine Semiconductor K.K. 9380 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor, Korea Peregrine Semiconductor Europe #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 e South Asia Pacific Peregrine Semiconductor, China Americas: Tel: 505-881-0438 Fax: 505-881-0443 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 bs ol et Space and Defense Products For a list of representatives in your area, please refer to our Web site at: www.psemi.com Advance Information O Data Sheet Identification The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0053-05 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. ©2005-8 Peregrine Semiconductor Corp. All rights reserved. Page 16 of 17 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com