4257-00

Product Specification PE4257 50Ω SPDT Absorptive UltraCMOS™ 10 MHz – 3.0 GHz RF Switch Product Description The PE4257 is a high-isolation UltraCMOS™ switch designed for wireless applications, covering a broad frequency range from near 10 MHz up to 3000 MHz. This single-supply SPDT switch integrates a two-pin CMOS control interface. It also provides low insertion loss with extremely low bias requirements while operating on a single +3 volt supply. In a typical wireless application, the PE4257 provides unprecedented isolation and integration. Features  50Ω characteristic impedance  Integrated 50Ω terminations  High input IP3 > +55 dBm  High isolation 64 dB at 1000 MHz  Low insertion loss: typically 0.75 dB at 1000 MHz and 0.95 dB at 2000 MHz The PE4257 is manufactured on pSemi’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram  LV CMOS two-pin control  Single +3 volt supply operation  Low current consumption: 8 μA Figure 2. Package Type RFC ESD 20-Lead 4x4 mm QFN 50 RF2 RF1 ESD ESD 50 CMOS Control Driver 50 CTRL CTRL2 Table 1. Electrical Specifications @ +25 °C, VDD = 3.0 V (ZS = ZL = 50 Ω ) Parameter Condition 1 Minimum Typical 10 Operating Frequency Units 3000 MHz 0.95 1.15 1.4 dB Insertion Loss 1000 MHz 2000 MHz 3000 MHz Isolation Input to Output 1000 MHz 2000 MHz 3000 MHz 61 46 40 64 50 44 dB Isolation Output to Output 1000 MHz 2000 MHz 3000 MHz 57 54 42 63 60 48 dB 80 dBm Input IP2 10 MHz - 1000 MHz Input IP3 Input 1dB Compression Switching Time Video Feedthrough 0.75 0.95 1.2 Maximum 2 10 MHz - 1000 MHz 50 55 dBm 1000 MHz 29 31 dBm 2 µs 50% CTRL to 10 / 90 RF 3 10 MHz - 1000 MHz 15 mVpp Notes: 1. Device linearity will begin to degrade below 5 MHz 2. Note Absolute Maximum ratings in Table 3. 3. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth. Document No. 32714-2 │ www.psemi.com ©2004-2022 pSemi Corporation All rights reserved. Page 1 of 6 PE4257 Product Specification CTRL2 VI 16 CTRL1 VDD GND 1 GND 2 15 GND 14 GND RF1 3 13 GND, RF1 Term. 4 12 GND, RF2 Term. GND 5 11 GND 7 8 9 GND RFC GND RF2 GND 10 6 GND GND 4x4mm 20-Lead QFN Table 2. Pin Descriptions Pin Number Name 1 GND RF Ground Description 2 GND RF Ground 31 RF1 RF I/O 4 GND RF Ground 5 GND RF Ground 6 GND RF Ground 7 GND RF Ground 81 RFC RF Common 9 GND RF Ground 10 GND RF Ground 11 GND RF Ground 12 GND RF Ground 131 RF2 RF I/O 14 GND RF Ground 15 GND RF Ground 162 CTRL2 17 2 CTRL1 183 VSS / GND 19 GND 20 VDD Pad GND Table 3. Absolute Maximum Ratings Symbol 17 18 VSS/GND 19 GND 20 VDD Figure 3. Pin Configuration (Top View) Min Max Units Power supply voltage Parameter/Condition -0.3 4.0 V Voltage on any DC input -0.3 VDD + 0.3 V 33/24 dBm PRF RF power on RFC, RF1, RF2 on port/terminated port TST Storage temperature -65 +150 °C TOP Operating temperature -40 +85 °C VESD ESD voltage (Human Body Model) 1000 V Exceeding absolute maximum ratings may cause permanent damage. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Table 4. Operating Ranges @ 25 °C1 Parameter VDD Power Supply Min Typ Max Units 2.7 3.0 3.3 V 8 20 μA 0.30 VDD V IDD Power Supply Current (VDD = 3V, VCNTL = 3V) Control Voltage High 0.70 VDD Control Voltage Low 0 V Note: 1. Operation should be restricted to the limits in the Operating Ranges table Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Supply Switching Frequency The PE4257 has a maximum 25 kHz switching rate when the internal negative voltage generator is used (pin 18=GND). The rate at which the PE4257 can be switched is only limited to the switching time if an external -3V supply is provided at (pin 18=VSS ). RF Ground Pad Table 5. Truth Table Control 2 Control 1 Negative Supply Option Digital Ground Notes: 1. RF pins 3, 8, and 13 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is met. 2. Pins 16 and 17 are the CMOS controls that set the four operating states. 3. Connect pin 18 to GND to enable the negative voltage generator. Connect pin 18 to VSS (-3V) to bypass and disable internal -3 V supply generator. See paragraph “Switching Frequency.” CTRL1 CTRL2 RFC – RF1 RFC – RF2 OFF Low Low OFF Low High OFF ON High Low ON OFF High High N/A1 N/A1 Note: The operation of the PE4257 is not supported or characterized in the C1=VDD and C2=VDD state. ©2004-2022 pSemi Corporation All rights reserved. Page 2 of 6 Document No. 32714-2 │ UltraCMOS™ RFIC Solutions PE4257 Product Specification Typical Performance Data @ 25°C (unless otherwise noted) (50 Ω impedance) Figure 4. Insertion Loss – Input - Output Figure 5. RF1 to RF2 Isolation Figure 6. Isolation – RFC to RF1/RF2 Figure 7. Return Loss Document No. 32714-2 │ www.psemi.com ©2004-2022 pSemi Corporation All rights reserved. Page 3 of 6 PE4257 Product Specification Figure 8. Evaluation Board Layouts Evaluation Kit The SPDT switch evaluation kit board was designed to ease customer evaluation of the PE4257 SPDT switch. The RF common port is connected through a 50 Ω transmission line to J2. Port 1 and Port 2 are connected through 50Ω transmission lines to J1 and J3. A through transmission line connects SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a four metal layer FR4 material with a total thickness of 0.031”. The transmission lines were designed using a coplanar waveguide with ground plane (28 mil core, 47.6 mil width, 30 mil gap). Note the number of vias surrounding the device in the layout shown in Figure 8. These vias are critical for obtaining the specified isolation performance for the device shown in this datasheet. J6 provides a means for controlling DC and digital inputs to the device. The provided jumpers short the package pin to ground for logic low. When the jumper is removed, the pin is pulled up to VDD for logic high. When the jumper is in place, 3 µA of current will flow through the 1 MΩ pull up resistor. This extra current should not be attributed to the requirements of the device. 101/0151 Figure 9. Evaluation Board Schematic J6 HEADER7X2 1 3 5 7 9 11 13 R2 1M C2 DNI C3 DNI 2 4 6 8 10 12 14 GND 12 GND GND 11 50 OHM T-Line J3 1 10 GND 2 GND 6 R1 1M 2 4 6 8 10 12 14 16 C2 17 13 GND 5 18 14 RF2 U1 PE4255/PE4257/PE42551 9 4 C1 15 GND RFC RF1 19 GND 8 3 VSS/GND VDD GND GND GND 2 GND 2 1 1 7 50 OHM T-Line J1 GND 20 C1 DNI 1 3 5 7 9 11 13 50 OHM T-Line J2 1 50 OHM T-Line J5 2 J4 ©2004-2022 pSemi Corporation All rights reserved. Page 4 of 6 1 2 2 1 102/0198 Document No. 32714-2 │ UltraCMOS™ RFIC Solutions PE4257 Product Specification Figure 10. Package Drawing 20-Lead 4x4 QFN Figure 12. Marking Specifications 4257 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number Moisture Sensitivity Level The moisture sensitivity level rating for the PE4257 in the 20-lead 4 x 4 mm QFN package is MSL1. Document No. 32714-2 │ www.psemi.com ©2004-2022 pSemi Corporation All rights reserved. Page 5 of 6 PE4257 Product Specification Figure 11. Tape and Reel Drawing Tape Feed Direction Bump 1 Nominal Tolerance Ao 4.35 ±0.05 Bo 4.35 ±0.05 Ko 1.10 ±0.05 bump side down Device Orientation in Tape Table 6. Ordering Information Order Code Part Marking Description Package Shipping Method 4257-00 PE4257-EK PE4257-20QFN 4x4mm-EK Evaluation Kit 1 / Box 4257-51 4257 PE4257G-20QFN 4x4mm-75A Green 20-lead 4x4mm QFN 75 units / cut tape from reel 4257-52 4257 PE4257G-20QFN 4x4mm-3000C Green 20-lead 4x4mm QFN 3000 units / T&R Sales Contact and Information For sales and contact information please visit www.psemi.com. ©2004-2022 pSemi Corporation All rights reserved. Page 6 of 6 Document No. 32714-2 │ UltraCMOS™ RFIC Solutions