4309-51

Product Specification PE4309 Product Description This product is a high linearity, 6-bit RF Digital Step Attenuator (DSA) covering a 31.5 dB attenuation range in 0.5 dB steps. The Peregrine 50Ω RF DSA provides a parallel CMOS control interface and it operates on 3-volt to 5-volt supply. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. This Peregrine DSA is available in a 4x4 mm 24 lead QFN footprint with an exposed ground paddle. The PE4309 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Switched Attenuator Array RF Input RF Output 50 Ω RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHz Features • Best in class 2.0 kV HBM ESD tolerance • Low Insertion Loss: 1.6 dB typical • Attenuation: 0.5 dB steps to 31.5 dB • High Linearity: Typical 52 dB IP3 • Best in Class Attenuation accuracy • Parallel programming interface • Single supply, 3V to 5V operation • Standard 3V or 5V CMOS control logic independent of supply voltage • Very low power consumption • RoHS-compliant 24-lead 4x4 mm QFN Figure 2. Package Type 4x4 mm 24-Lead QFN Parallel Control 6 Control Logic Interface Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V - 5.0 V Parameter Operation Frequency Insertion Loss Any Bit or Bit Combination Any Bit or Bit Combination 0.5 - 7.5 dB States 3 8.0 - 15.5 dB States 3 16.0 - 31.5 dB States3 DC - 2.2 GHz 2.2 - 4.0 GHz DC ≤ 1.0 GHz 1.0 < 2.2 GHz 2.2 < 3.8 GHz 2.2 < 3.8 GHz 2.2 < 3.8 GHz 1 MHz - 2.2 GHz 2.2 - 4.0 GHz Two-tone inputs +18 dBm 1 MHz - 2.2 GHz 2.2 - 4.0 GHz DC - 2.2 GHz 2.2 - 4.0 GHz 50% of control voltage to 90% of final attenuation level Test Conditions4 Frequency Min DC 30 15 10 - Typ 1.6 2.2 0.15 0.7 1.2 32 32 52 45 20 20 - Maximum 4000 2 3.4 ±(0.10 + 3% of atten setting), not to exceed +0.20 dB ±(0.15 + 3% of atten setting) 1 Units MHz dB dB dB dB dB dB dB dBm dBm dBm dBm dB dB µs Attenuation Accuracy 1 dB Compression2 Input IP31 Return Loss Switching Speed Notes: 1. 2. 3. 4. Device Linearity will begin to degrade below 5 MHz. Note Absolute Maximum in Table 4. See Figures 12 and 13 for typical attenuation error. Measurements made in a 50 ohm system (see Figure 4, Test Circuit Block Diagram). Resistors (R2, R3, R5, R6, R7) with a value of 10K-ohm are used to decouple the RF path from the control inputs. ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 9 Document No. 70-0218-06 │ www.psemi.com PE4309 Product Specification Figure 3. Pin Configuration (Top View) C 0.5 C16 C2 C1 C4 C8 24 23 22 21 Table 3. Operating Ranges Parameter VDD Power Supply Voltage Min 3.0 Typ 3.3 100 Max 5.5 250 +24 Units V µA dBm 20 N/C VDD N/C RF1 N/C ACG 19 1 2 3 4 5 6 11 10 12 7 8 9 Exposed Ground Paddle 18 17 16 15 14 13 N/C N/C N/C RF2 N/C ACG IDD Power Supply Current PIN Input power (50Ω) Table 4. Absolute Maximum Ratings Symbol VDD Parameter/Conditions Power supply voltage Voltage on any DC input Storage temperature range Operating temperature range Input power (50Ω) ESD voltage (Human Body Model) Min -0.3 -0.3 -65 -40 Max 6.0 6.0 150 85 30 2000 Units V V °C °C dBm V ACG ACG ACG ACG ACG N/C VI TST Table 2. Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Paddle Pin Name N/C VDD N/C RF1 N/C5 ACG6 ACG6 ACG6 ACG6 ACG6 ACG6 N/C 7 Description No Connect Power supply pin No Connect RF port No Connect AC Ground connection AC Ground connection AC Ground connection AC Ground connection AC Ground connection AC Ground connection No Connect AC Ground connection No Connect RF port No Connect No Connect No Connect Attenuation control bit, 16 dB Attenuation control bit, 8 dB Attenuation control bit, 4 dB Attenuation control bit, 2 dB Attenuation control bit, 1 dB Attenuation control bit, 0.5 dB Ground for proper operation TOP PIN VESD Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 4. ACG6 N/C5 RF2 N/C5 N/C5 N/C5 C16 C8 C4 C2 C1 C0.5 GND Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 5. Control Voltage State Low High Bias Condition 0 to +1.0 Vdc at 2 µA (typ) +2.0 to +5 Vdc at 10 µA (typ) The standard 3V or 5V CMOS control logic is independent of supply voltage. Table 6. Truth Table C16 1 1 1 1 1 1 0 0 Notes: 5. For improved RF performance these No Connect pins can be connected to RF ground. 6. Pins can either be grounded directly or through coupling capacitors 7. Pin can either be grounded or No Connect C8 1 1 1 1 1 0 1 0 C4 1 1 1 1 0 1 1 0 C2 1 1 1 0 1 1 1 0 C1 1 1 0 1 1 1 1 0 C0.5 Attenuation State 1 0 1 1 1 1 1 0 Reference Loss (IL) 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 9 Document No. 70-0218-06 │ U ltraCMOS™ RFIC Solutions PE4309 Product Specification Figure 4. Test Circuit Block Diagram Peregrine Specification 102-0371 J1 CWN-350-14-0000 14 12 10 8 6 4 2 GND GND GND GND GND GND GND DB7 DB6 DB5 DB4 DB3 DB2 DB1 13 11 9 7 5 3 1 C16 C8 C4 C2 C1 C0.5 10K 10K 10K 10K 10K R7 20 C8 R2 R3 R5 R6 VDD C1 0.1µF C2 100pF R1 0 OHM 23 22 21 24 C1 C2 C4 1 2 C0.5 C16 19 R8 R4 DNI 10K VDD NC VDD NC RF1 NC ACG U1 MLPQ4X4_24L NC NC NC RF2 NC ACG 18 17 16 15 14 13 C4 100pF J2 SMASM 1 Z=50 Ohm C3 100pF 3 4 5 6 Z=50 Ohm 1 J3 SMASM 2 ACG ACG ACG ACG ACG 7 8 9 10 11 ECT BP050-0024UJ03 4x4 MLP 24 Ld Socket Document No. 70-0218-06 │ www.psemi.com 12 NC ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 9 2 PE4309 Product Specification Evaluation Kit The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE4309 Digital Step Attenuator. Connect J2 by mini clip to Vdd to power the IC. Connect J8 by mini clip to power the evaluation board support circuits. The control bits for the six parallel data inputs (C0.5 to C16) are controlled using S2-S7 to select bits or bit combinations. This allows any attenuation setting to be specified as shown in Table 6. The de-embed trace (J6 to J7) estimates the PCB insertion loss for removal from the evaluation board measurement data. To evaluate using customer software, J1 can be installed using a standard 0.100 IDC header (some circuit modification required, see schematic). The ability to supply different voltages for the Control circuitry (using J8) and IC Vdd (using J2) circuits allows for evaluation of circuits using different control vs. supply voltages. Figure 5. Evaluation Board Layout Peregrine Specification 101/0299 Figure 6. Evaluation Board Schematic Peregrine Specification 102/0366 ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 9 Document No. 70-0218-06 │ U ltraCMOS™ RFIC Solutions PE4309 Product Specification Typical Performance Data Figure 7. Insertion Loss, Vdd = 3.0 V Figure 8. Attenuation at Major Steps 31.5 dB 16 dB 8 dB 2 dB 4 dB 1 dB 0.5 dB Figure 9. Input Return Loss at Major Attenuation Steps Figure 10. Output Return Loss at Major Attenuation Steps 0 dB 0 dB 16 dB 16 dB 31.5 dB 31.5 dB Document No. 70-0218-06 │ www.psemi.com ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 9 PE4309 Product Specification Typical Performance Data Figure 11. Attenuation Error Vs. Frequency 16 dB 8 dB 31.5 dB Figure 12. Attenuation Error vs. Setting: Low Frequency Figure 13. Attenuation Error vs. Setting: High Frequency ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 9 Document No. 70-0218-06 │ U ltraCMOS™ RFIC Solutions PE4309 Product Specification Figure 16. Package Drawing QFN 4x4 mm MAX 0.900 0.850 0.800 A NOM MIN Document No. 70-0218-06 │ www.psemi.com ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 9 PE4309 Product Specification Figure 17. Tape and Reel Drawing Figure 18. Marking Specifications 4309 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of Lot Number Table 7. Ordering Information Order Code 4309-00 4309-51 4309-52 Part Marking PE4309-EK 4309 4309 Description PE4309-24QFN 4x4mm-EK PE4309G-24QFN 4x4mm-75A PE4309G-24QFN 4x4mm-3000C Package Evaluation Kit Green 24-lead 4x4mm QFN Green 24-lead 4x4mm QFN Shipping Method 1 / Box 75 units / Tube 3000 units / T&R ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 9 Document No. 70-0218-06 │ U ltraCMOS™ RFIC Solutions PE4309 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Space and Defense Products Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP and MultiSwitch are trademarks of Peregrine Semiconductor Corp. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0218-06 │ www.psemi.com ©2007 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 9