EK29102-03

PE29102 Document Category: Product Specification UltraCMOS® High-speed FET Driver, 40 MHz Features Figure 1 • PE29102 Functional Diagram • High- and low-side FET drivers LI FE • Dead-time control • Fast propagation delay, 9 ns • Tri-state enable mode • Sub-nanosecond rise and fall time • 2A/4A peak source/sink current • Package – flip chip Applications • Class D audio • DC–DCconversions • AC–DC conversions • Wireless charging F • Envelope tracking O • LiDAR Product Description D The PE29102 is an integrated high-speed driver designed to control the gates of external power devices, such as enhancement mode gallium nitride (GaN) FETs. The outputs of the PE29102 are capable of providing switching transition speeds in the sub-nanosecond range for switching applications up to 40 MHz. The PE29102 is optimized for matched dead time and offers best-in-class propagation delay to improve system bandwidth. High switching speeds result in smaller peripheral components and enable innovative designs for applications such as class D audio and wireless charging. The PE29102 is available in a flip chip package. EN The PE29102 is manufactured on Peregrine’s UltraCMOS process, a patented advanced form of silicon-oninsulator (SOI) technology, offering the performance of GaAs with the economy and integration of conventional CMOS. ©2018, pSemi Corporation. All rights reserved. • Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-81227-7 – (11/2018) www.psemi.com PE29102 High-speed FET Driver Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions Latch-up Immunity LI FE When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 • Absolute Maximum Ratings for PE29102 Parameter/Condition Min Max Unit –0.3 7 V –0.3 7 V Input signal –0.3 7 V HSS to LSS –100 100 V -1 100 V -1 100 V 500 V Low-side bias (LSB) to low-side source (LSS) F High-side bias (HSB) to high-side source (HSS) HSS to GND ESD voltage HBM(*), all pins O LSS to GND EN D Note: * Human body model (JEDEC JS–001, Table 2A). Page 2 of 16 DOC-81227-7 – (11/2018) www.psemi.com PE29102 High-speed FET Driver Recommended Operating Conditions Table 2 lists the recommended operating conditions for the PE29102. Devices should not be operated outside the recommended operating conditions listed below. Table 2 • Recommended Operating Conditions for PE29102 Min Typ Max Unit LI FE Parameter Supply for driver front-end, VDD Supply for high-side driver, HSB Supply for low-side driver, LSB HIGH level input voltage, VIH LOW level input voltage, VIL HSS range LSS range Operating temperature 5.0 6.0 V 4.0 5.0 6.0 V 4.0 5.0 6.0 V 1.6 6.0 V 0 0.6 V 0 60 V 0 60 V –40 +105 °C –40 +125 °C EN D O F Junction temperature 4.0 DOC-81227-7 – (11/2018) Page 3 of 16 www.psemi.com PE29102 High-speed FET Driver Electrical Specifications Table 3 provides the key electrical specifications @ +25 °C, VDD = 5V, 100 pF load, HSB and LSB bootstrap diode included unless otherwise specified. Table 3 • DC Characteristics Condition DC Characteristics VDD quiescent current VDD = 5V HSB quiescent current VDD = 5V LSB quiescent current VDD = 5V Total quiescent current VDD = 5V VDD quiescent current VDD = 6V HSB quiescent current VDD = 6V LSB quiescent current VDD = 6V Total quiescent current VDD = 6V Min Typ Max Unit LI FE Parameter 1.3 mA 2.7 mA 2.7 mA 6.7 9.0 mA 1.6 mA 3.6 mA 3.6 mA 9.0 11.6 mA Under voltage release (rising) 3.6 3.8 V Under voltage hysteresis 400 mV 1.9 Ω 1.3 Ω Gate Drivers HSGPU/LSGPU pull-up resistance O HSGPD/LSGPD pull-down resistance F Under Voltage Lockout HSGPU/LSGPU leakage current HSB–HSGPU = 5V, LSB–LSGPU = 5V 10 µA HSGPD/LSGPD leakage current HSGPD–HSS = 5V, LSGPD–LSS = 5V 10 µA 80 kΩ resistor to GND 1.3 V RDHL = 30 kΩ 1.9 ns RDHL = 80.6 kΩ 7.0 ns RDHL = 150 kΩ 13.6 ns RDHL = 255 kΩ 23.5 ns RDLH = 30 kΩ 1.8 ns RDLH = 80.6 kΩ 6.7 ns RDLH = 150 kΩ 13.2 ns RDLH = 255 kΩ 22.7 ns LSG turn-off propagation delay At min dead time 9.1 ns HSG rise time 10 - 90% with 100pF load 0.9 ns LSG rise time 10 - 90% with 100pF load 0.9 ns HSG fall time 90 - 10% with 100pF load 0.8 ns LSG fall time 90 - 10% with 100pF load 0.9 ns Dead-time Control D Dead-time control voltages EN Dead-time from HSG going low to LSG going high Dead-time from LSG going low to HSG going high Switching Characteristics Page 4 of 16 DOC-81227-7 – (11/2018) www.psemi.com PE29102 High-speed FET Driver Table 3 • DC Characteristics (Cont.) Parameter Condition Min Minimum output pulse width Max switching frequency @ 50% duty RDHL = RDLH = 80 kΩ cycle Max Unit 2.8 5.0 ns 40 MHz LI FE Control Logic Typ Table 4 provides the control logic truth table for the PE29102. Table 4 • Truth Table for PE29102 IN HSGPU–HSS L L Hi–Z L H H H L Hi–Z H H Hi–Z HSGPD–HSS LSGPU–LSS LSGPD–LSS L H Hi–Z Hi–Z Hi–Z L L Hi–Z L L Hi–Z L EN D O F EN DOC-81227-7 – (11/2018) Page 5 of 16 www.psemi.com PE29102 High-speed FET Driver Typical Performance Data Figure 2 through Figure 4 show the typical performance data @ +25 °C, VDD = 5V, load = 2.2Ω resistor in series with 100 pF capacitor, HSB and LSB bootstrap diode included, unless otherwise specified. VDD = 4V Total Quiescent Current (mA) 10 9 8 7 6 5 4 3 2 LI FE Figure 2 • Total Quiescent Current (mA) VDD = 5V VDD = 6V 0 -40 F 1 25 105 EN D O Temperature (°C) Page 6 of 16 DOC-81227-7 – (11/2018) www.psemi.com PE29102 High-speed FET Driver Figure 3 • UVLO Threshold (V) UVLO Rising UVLO Falling 3.7 LI FE UVLO Threshold (V) 3.6 3.5 3.4 3.3 3.2 3.1 3 2.9 2.8 -40 25 105 F Temperature (°C) O Figure 4 • Dead-time (ns) 30k 25 80.6k 150k 255k D Dead-time (ns) 20 15 EN 10 5 0 -40 25 105 Temperature (°C) DOC-81227-7 – (11/2018) Page 7 of 16 www.psemi.com PE29102 High-speed FET Driver Test Diagram Figure 5 • Test Circuit for PE29102 LI FE Figure 5 shows the test circuit used for obtaining measurements. The two bootstrap diodes shown in the schematic are used for symmetry purposes in characterization. In practice, only the HSB diode is required. Removing the LSB diode will result in higher low-side supply voltage since the diode drop is eliminated. As a result, the dead-time resistor can be adjusted to compensate for any changes in propagation delay. VDD VDD VIN HSB HSGPU Level Shifter UVLO Q1 Output Driver HSGPD IN Dead Time Controller Logic Phase Control VSW HSS LSB LSGPU EN RDHL LSGPD LSS O RDLH Q2 Output Driver F Level Shifter PHCTL EN D GND Page 8 of 16 DOC-81227-7 – (11/2018) www.psemi.com PE29102 High-speed FET Driver Theory of Operation General LI FE The PE29102 is intended to drive both the high-side (HS) and the low-side (LS) gates of external power FETs, such as enhancement mode GaN FETs, for power management applications. The PE29102 is suited for applications requiring higher switching speeds due to the reduced parasitic properties of the high resistivity insulating substrate inherent with Peregrine’s UltraCMOS process. The driver uses a single-ended pulse width modulation (PWM) input that feeds a dead-time controller, capable of generating a small and accurate dead-time. The dead-time circuit prevents shoot-through current in the output stage. The propagation delay of the dead-time controller must be small to meet the fast switching requirements when driving GaN FETs. The differential outputs of the dead-time controller are then level-shifted from a low-voltage domain to a high-voltage domain required by the output drivers. Each of the output drivers includes two separate pull-up and pull-down outputs allowing independent control of the turn-on and turn-off gate loop resistance. The low impedance output of the drivers improves external power FETs switching speed and efficiency, and minimizes the effects of the voltage rise time (dv/dt) transients. Under-voltage Lockout Dead-time Adjustment F An internal under-voltage lockout (UVLO) feature prevents the PE29102 from powering up before input voltage rises above the UVLO threshold of 3.6V (typ), and 400 mV (typ) of hysteresis is built in to prevent false triggering of the UVLO circuit. The UVLO must be cleared and the EN pin must be released before the part will be enabled. O The PE29102 features a dead-time adjustment that allows the user to control the timing of the LS and HS gates to eliminate any large shoot-through currents, which could dramatically reduce the efficiency of the circuit and potentially damage the GaN FETs. Two external resistors control the timing of outputs in the dead-time controller block. The timing waveforms are illustrated in Figure 6. EN D The dead-time resistors only affect the rising edge of the low-side gate (LSG) and high-side gate (HSG) outputs. Dead-time resistor RDLH will delay the rising edge of HSG, thus providing the desired dead-time between LSG falling and HSG rising. Likewise, dead-time resistor RDHL will delay the rising edge of LSG, thus providing the desired dead-time between HSG falling and LSG rising. Figure 7 shows the resulting dead-time versus the external resistor values with both HS and LS bias diode/capacitors installed as indicated in Figure 5. The LS bias diode and capacitor are included for symmetry only and are not required for the part to function. Removing the LS bias diode will increase the LSG voltage by approximately 0.3V, resulting in a wider separation of the tDHL and tDLH curves in Figure 7. Phase Control Pin 10 (PHCTL) controls the polarity of the gate driver outputs. When PHCTL is low, the HSG will be in phase with the input signal. When PHCTL is high, the LSG will be in phase with the input signal. The PHCTL pin includes an internal pull-down resistor and can be left floating. DOC-81227-7 – (11/2018) Page 9 of 16 www.psemi.com PE29102 High-speed FET Driver Figure 6 and Figure 7 provide the dead-time description for the PE29102. Figure 6 • Dead-time Description IN tHON tDHL HSG-HSS tDLH tLON LSG-LSS F Figure 7 • Dead-time between HSG and LSG (ns) LI FE tIN O 25 RDHL 20 15 10 D Dead-time between HSG and LSG (ns) RDLH 5 EN 0 0 50 100 150 200 250 300 Dead-time Resistance (kΩ) Page 10 of 16 DOC-81227-7 – (11/2018) www.psemi.com PE29102 High-speed FET Driver Application Circuit LI FE Figure 8 shows a class-D audio amplifier application diagram using two PE29102 gate drivers in a full-bridge configuration. The full-bridge circuit comprises two half bridge topologies that share a common supply and load. The low-level logic circuitry is powered by the gate drive regulator that supplies the PE29102 drivers, logic buffer and phase splitter. The PWM input signal feeds a single logic buffer, which drives a common logic X-OR gate Phase Splitter that provides phase inverted signals to each driver. VIN is designed to operate at 60V DC (max.) to provide between 100 — 120W of power into an 8Ω load. Figure 8 • PE29102 Class D Audio Amplifier Block Diagram Gate Drive Regulator VIN PE29102 Gate Driver #1 VIN L1 C VSW1 L2 VSW2 PE29102 Gate Driver #2 F L.S. GND O Logic Phase Splitter EN D Logic Buffer DOC-81227-7 – (11/2018) Page 11 of 16 www.psemi.com PE29102 High-speed FET Driver Evaluation Board The PE29102 evaluation board (EVB) allows the user to evaluate the PE29102 gate driver in either a full-bridge configuration or two independent half-bridge configurations. The EVB is assembled with two PE29102 FET drivers and four GS61004B E-mode GaN FETs. Refer to Peregrine Semiconductor DOC-82956 for more information. LI FE Because the PE29102 is capable of generating fast switching speeds, the printed circuit board (PCB) layout is a critical component of the design. The layout should occupy a small area with the power FETs and external bypass capacitors placed as close as possible to the driver to reduce any resonances associated with the gate loops, common source and power loop inductances. Since the maximum allowable gate-to-source voltage for the GS61004B FETs is 7V, resonance in the gate loops can generate ringing that can degrade the performance and potentially damage the power devices due to high voltage spikes. Additionally, it is important to keep ground paths short. The PCB is fabricated on FR4 material, with a total thickness of 0.062 inches. A minimum copper thickness of 1.5 ounces or more is recommended on the PCB outer layers to limit resistive losses and improve thermal spreading. EN D O F Figure 9 • PE29102 Evaluation Board Assembly Page 12 of 16 DOC-81227-7 – (11/2018) www.psemi.com PE29102 High-speed FET Driver Pin Configuration 5 RDLH 4 3 2 1 NC HSB HSS HSGPD 8 7 6 IN EN HSGPU 10 9 GND PHCTL LSGPU 16 15 14 13 12 RDHL VDD LSB LSS LSGPD Pin Name 1 HSGPD 2 HSS High-side source 3 HSB High-side bias 4 NC 5 RDLH Dead-time control resistor sets LSG falling to HSG rising delay (external resistor to GND) 6 HSGPU High-side gate drive pull-up 7(*) EN Enable active low, tri-state outputs when high 8(*) IN Control input 9 LSGPU Description High-side gate drive pull-down No connection (ground or float) Low-side gate drive pull-up Controls the polarity of the gate driver outputs 10(*) PHCTL 11 GND 12 LSGPD 13 LSS Low-side source 14 LSB Low-side bias 15 VDD +5V supply voltage 16 RDHL Ground Low-side gate drive pull-down Dead-time control resistor sets HSG falling to LSG rising delay (external resistor to ground) Note: * Internal 100k pull down resistor EN D O 2040 µm (−20 / +30 µm) Pin No. F 11 1640 µm (−20 / +30 µm) Figure 10 • Pin Configuration (Top View–Bumps Down) Table 5 • Pin Descriptions for PE29102 LI FE This section provides pin information for the PE29102. Figure 10 shows the pin map of this device for the available package. Table 5 provides a description for each pin. DOC-81227-7 – (11/2018) Page 13 of 16 www.psemi.com PE29102 High-speed FET Driver Die Mechanical Specifications This section provides the die mechanical specifications for the PE29102. Table 6 • Die Mechanical Specifications for PE29102 Min Die size, singulated (x,y) Typ Max 2040 × 1640 Wafer thickness 180 200 Wafer size Test Condition Including sapphire, max tolerance = –20/+30 µm 220 µm µm Bump pitch 400 Bump height 85 Bump diameter 110 Figure 11 • Recommended Land Pattern for PE29102 2.040+0.03 -0.02 µm µm µm max tolerance = ±17 0.40 0.22 (x14) F 0.40 O 1.640+0.03 -0.02 Ø0.110±0.017 (x16) BUMPS DOWN 0.20±0.02 Unit LI FE Parameter BUMPS UP Ø0.090±0.008 (x16) RECOMMENDED LAND PATTERN D 0.085±0.013 EN SIDE VIEW Page 14 of 16 DOC-81227-7 – (11/2018) www.psemi.com PE29102 High-speed FET Driver Tape and Reel Specification This section provides tape-and-reel information for the PE29102. Figure 12 • Tape and Reel Specifications for PE29102. P1 SEE NOTE 1 D1 P0 P2 D0 LI FE T SEE NOTE 3 A E Bo Ao Ko F SEE NOTE 3 Wo A Direction of Feed Tolerance +/- 0.05 +/- 0.05 +/- 0.05 +/- 0.1 +0.3 / -0.1 +/- 0.05 +/- 0.05 + 0.1 / - 0 +/- 0.1 +/- 0.1 +/- 0.05 +/- 0.05 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2. 2. Camber in compliance with EIA 481. 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. F Nominal 1.9 2.3 0.4 4.0 8.0 3.5 0.5 1.5 1.8 4.0 2.0 0.2 Pin 1 Device Orientation in Tape EN D O Pocket Ao Bo Ko P1 Wo F D1 D0 E P0 P2 T DOC-81227-7 – (11/2018) Page 15 of 16 www.psemi.com PE29102 High-speed FET Driver Ordering Information Table 7 lists the available ordering code for the PE29102. Table 7 • Order Code for PE29102 Description PE29102 flip chip PE29102A-Z PE29102 flip chip Advance Information Die on tape and reel 500 units/T&R Die on tape and reel 3000 units/T&R O Document Categories Shipping Method F PE29102A-X Packaging LI FE Order Codes The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The datasheet contains preliminary data. Additional data may be added at a later date. pSemi reserves the right to change specifications at any time without notice in order to supply the best possible product. D Product Specification The datasheet contains final data. In the event pSemi decides to change the specifications, pSemi will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Sales Contact EN For additional information, contact Sales at sales@psemi.com. Disclaimers The information in this document is believed to be reliable. However, pSemi assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. pSemi’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the pSemi product could create a situation in which personal injury or death might occur. pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Patent Statement pSemi products are protected under one or more of the following U.S. patents: patents.psemi.com Copyright and Trademark ©2018, pSemi Corporation. All rights reserved. The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. Product Specification www.psemi.com DOC-81227-7 – (11/2018)