EK4280-01

Product Specification PE4280 75 Ω SPDT CATV UltraCMOS™ Switch 5 MHz - 2.2 GHz Product Description The PE4280 is an UltraCMOS™ Switch designed for CATV applications, covering a broad frequency range from DC up to 2.2 GHz. This single-supply SPDT switch integrates a two-pin CMOS control interface. It also provides low insertion loss with extremely low bias requirements while operating on a single 3 V supply. In a typical CATV application, the PE4280 provides for a cost effective and manufacturable solution when compared to mechanical relays. The PE4280 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram Features  75 Ω characteristic impedance  Integrated 75 Ω terminations  CTB performance of 85 dBc  High isolation 60 dB at 1 GHz  Low insertion loss: typically 0.5 dB at 5 MHz, 1.1 dB at 1 GHz  High input IP3: 50 dBm  CMOS two-pin control  Single +3 V supply operation  Low current consumption: 8 μA  Unique all off terminated mode  4 x 4 x 0.85 mm QFN package RFC Figure 2. Package Type 20-lead 4 x 4 x 0.85 mm QFN 75 RF1 RF2 75 CMOS Control Driver C1 75 C2 Table 1. Electrical Specifications @ +25 °C (ZS = ZL = 75 Ω) Parameter Condition Operating Frequency Insertion Loss Isolation 5 MHz - 250 MHz 250 MHz - 750 MHz 750 MHz - 1000 MHz 1000 MHz - 2200 MHz 0.5 0.8 0.9 1.1 67 60 57 44 5 MHz - 1000 MHz 1 Typical 5 5 MHz - 250 MHz 250 MHz - 750 MHz 750 MHz - 1000 MHz 1000 MHz - 2200 MHz Input IP21 Minimum Maximum Units 2200 MHz 0.6 0.95 1.1 1.3 dB 72 65 60 47 dB 75 dBm 5 MHz - 1000 MHz 50 50 dBm Input 1dB Compression1 1000 MHz 29 26 dBm CTB/CSO 77 and 110 Channels; Power Out = 44 dBm V -85 dBc Switching Time 50% CTRL to 10/90% RF Video Feedthrough2 5 MHz - 1000 MHz Input IP3 2 µs 15 mVpp Notes: 1. Measured in a 50 Ω system. 2. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth Document No. 70-0164-05 │ www.psemi.com ©2010-11 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE4280 Product Specification Figure 3. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings Symbol VDD VI No. Name Description 1 GND Ground 2 GND Ground 31 RF1 RF I/O 4 GND Ground 5 GND Ground 6 GND Ground 74 GND Ground 81 RFC Common 4 GND Ground 10 GND Ground 11 GND Ground 12 4 GND Ground 13 1 RF2 RF I/O 14 GND Ground 15 GND Ground 162 C2 Control 2 9 Min Max Unit Power supply voltage -0.3 4.0 V Voltage on any DC input -0.3 VDD + 0.3 V 24 dBm PRF RF CW power TST Storage temperature -65 150 °C TOP Operating temperature -40 85 °C VESD ESD voltage (Human Body Model) 1000 V Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Table 2. Pin Descriptions 4 Parameter/Condition 172 C1 Control 1 183 VSS/GND Negative Supply Option 19 GND Ground 20 VDD Supply Pad GND Ground Pad Notes: 1. RF pins 3, 8, and 13 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is met. 2. Pins 16 and 17 are the CMOS controls that set the three operating states. 3. Connect pin 18 to GND to enable the on-chip negative voltage generator. Connect pin 18 to VSS (-3 V) to bypass and disable internal -3 V supply generator. Also, see paragraph "Switching Frequency." 4. Customer can add external resistance to ground to change or modify termination resistance. ©2010-11 Peregrine Semiconductor Corp. All rights reserved. Table 4. Operating Ranges @ 25 °C Parameter VDD Power Supply Min Typ Max Unit 2.7 3.0 3.3 V 8 20 μA IDD Power Supply Current Control Voltage High 70% VDD Control Voltage Low V 30% VDD V Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE4280 in the 20-lead 4 x 4 x 0.85 mm QFN package is MSL1. Document No. 70-0164-05 │ UltraCMOS™ RFIC Solutions Page 2 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE4280 Product Specification Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Switching Frequency The PE4280 has a maximum 25 kHz switching rate when the internal negative voltage generator is used (pin 18 = GND). The rate at which the PE4280 can be switched is only limited to the switching time if an external -3 V supply is provided at pin 18 (VSS). Table 5. RF Path Truth Table C1 C2 RFC – RF1 RFC – RF2 Low Low OFF OFF Low High OFF ON High Low ON OFF High High N/A 1 N/A1 Table 6. Termination Truth Table C1 C2 RFC – 75 Ω Low Low X2 Low High High Low High High RF1 – 75 Ω RF2 – 75 Ω X2 X2 X2 X2 N/A1 N/A1 N/A1 Notes: 1. The operation of the PE4280 is not supported or characterized in the C1 = VDD and C2 = VDD state. 2. "X" denotes termination enabled. Document No. 70-0164-05 │ www.psemi.com ©2010-11 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE4280 Product Specification Figure 4. Evaluation Board Layouts Peregrine Specification 101/0148~03A Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE4280 SPDT switch. The RFC port is connected through a 75 Ω transmission line to J2. Port 1 and Port 2 are connected through 75 Ω transmission lines to J1 and J3. A through transmission line connects F connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a four metal layer FR4 material with a total thickness of 0.062". The transmission lines were designed using a coplanar waveguide with ground plane (28 mil core, 21 mil width, 30 mil gap). J6 provides a means for controlling DC and digital inputs to the device. The provided jumpers short the package pin to ground for logic low. When the jumper is removed, the pin is pulled up to VDD for logic high. When the jumper is in place, 3 µA of current will flow through the 1 MΩ pull up resistor. This extra current should not be attributed to the requirements of the device. Proper PCB design is essential for full isolation performance. This eval board demonstrates good trace and ground management for minimum coupling and radiation. Figure 5. Evaluation Board Schematic Peregrine Specification 102/0195~02A J6 HEADER 7X2 1 3 5 7 9 11 13 R2 1M C2 DNI C3 DNI 2 4 6 8 10 12 14 16 R1 1M GND GND GND GND GND GND GND 12 GND 11 J3 1 GND 2 GND GND 75 OHM T-Line 10 GND C2 GND GND 21 18 13 RFC 5 17 14 RF2 U1 PE4280 9 4 C1 15 GND 8 RF1 VSS/GND 20 VDD 3 GND GND GND GND GND GND 2 6 2 1 1 7 75 OHM T-Line J1 19 C1 DNI VDD GND VSS/GND GND C1 GND C2 75 OHM T-Line J2 1 75 OHM T-Line J5 2 J4 ©2010-11 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0164-05 2 1 2 1 │ UltraCMOS™ RFIC Solutions Page 4 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE4280 Product Specification Typical Performance Data from -40 °C to +85 °C (unless otherwise noted) (75 Ω impedance except as indicated) Figure 6. Insertion Loss (RFC to RF1 or RF2) Figure 7. Input to Output Isolation (Closed) 25C -40C 85C RFC - RF1 (RF2 CLOSED) RFC - RF2 (RF1 CLOSED) -40 -0.2 -0.4 -50 -60 -0.8 Isolation (dB) Insertion Loss (dB) -0.6 -1 -1.2 -70 -80 -1.4 -90 -1.6 -100 -1.8 0 500 1000 1500 2000 2500 0 3000 500 1000 2000 2500 3000 2000 2500 3000 Frequency (MHz) Frequency (MHz) Figure 9. Isolation - RF1 To RF2 Figure 8. Input to Output Isolation (Open) RFC - RF1 (RF2 OPEN) RFC - RF2 (RF1 OPEN) RF1 - RF2 (RF1 Thru) RF1 - RF2 (RF2 Thru) RF1 - RF2 (RF1 & 2 OPEN) -40 -40 -50 -50 -60 -60 Isolation (dB) Isolation (dB) 1500 -70 -70 -80 -80 -90 -90 -100 -100 0 500 1000 1500 Frequency (MHz) Document No. 70-0164-05 │ www.psemi.com 2000 2500 3000 0 500 1000 1500 Frequency (MHz) ©2010-11 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE4280 Product Specification Typical Performance Data @ +25° C (Unless otherwise noted) (75 Ω impedance except as indicated) Figure 10. RFC Return Loss Figure 11. RF1 Return Loss RFC Terminated RFC - RF1 CLOSED 0 -5 Return Loss (dB) -10 -15 -20 -25 -30 -35 0 500 1000 1500 2000 2500 3000 Frequency (MHz) Figure 12. RF2 Return Loss Figure 13. Linearity: 50 Ω Impedance Input IP3 1dB Compression 60 50 Power (dBm) 40 30 20 10 0 0 500 1000 1500 2000 2500 3000 Frequency (MHz) ©2010-11 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0164-05 │ UltraCMOS™ RFIC Solutions Page 6 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE4280 Product Specification Figure 14. Package Drawing (mm) 4 x 4 mm 20-Lead QFN Figure 15. Tape and Reel Drawing Notes: 1. 10 sprocket hole pitch cumulative tolerance ± 0.2 2. Camber in compliance with EIA 481 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole Ao = 4.35 ± 0.1 mm Bo = 4.35 ± 0.1 mm Ko = 1.10 ± 0.1 mm Table 7. Ordering Information Order Code Part Marking Description Package Shipping Method 4280-52 4280 PE4280G-20QFN 4x4 mm-3000C Green 20-lead 4x4 mm QFN, Matte Tin Lead Finish 3000 units/T&R PE4280MLIAA 4280 PE4280-20QFN 4x4 mm-75 20-lead 4x4 mm QFN, NiPdAu Lead Finish 75 units/Tube PE4280MLIAA-Z 4280 PE4280-20QFN 4x4 mm-3000 20-lead 4x4 mm QFN, NiPdAu Lead Finish 3000 units/T&R EK4280-01 PE4280-EK PE4280-20QFN 4x4 mm-EK Evaluation Kit 1/Box Document No. 70-0164-05 │ www.psemi.com ©2010-11 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com PE4280 Product Specification Sales Contact and Information For Sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. ©2010-11 Peregrine Semiconductor Corp. All rights reserved. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. All other trademarks mentioned herein are the property of their respective companies. Document No. 70-0164-05 │ UltraCMOS™ RFIC Solutions Page 8 of 8 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com