EK4314-01

PE4314 Document Category: Product Specification UltraCMOS® RF Digital Step Attenuator, 1 MHz–2.5 GHz Features Figure 1 • PE4314 Functional Diagram • Attenuation step of 0.5 dB up to 31.5 dB • Glitch-less attenuation state transitions Switched Attenuator Array • Low distortion for CATV and multi-carrier applications RF Input RF Output • Extended +105 °C operating temperature • Parallel and Serial programming interfaces • Packaging – 20-lead 4 × 4 × 0.85 mm QFN Applications • DOCSIS 3.1/0 customer premises equipment (CPE) and infrastructure • Satellite CPE and infrastructure • Fiber CPE and infrastructure Parallel Control 6-bit Serial Control Control Logic Interface 3-bit Power-up Control 2-bit P/S VSS_EXT (optional) Product Description The PE4314 is a 75Ω HaRP™ technology-enhanced, 6-bit RF digital step attenuator (DSA) that supports a frequency range from 1 MHz to 2.5 GHz. It features glitch-less attenuation state transitions and supports 1.8V control voltage and an extended operating temperature range up to +105 °C, making this device ideal for multiple wired broadband applications. The PE4314 is a pin-compatible upgraded version of the PE4304, PE4307, PE4308 and PE43404. An integrated digital control interface supports both Serial and Parallel programming of the attenuation, including the capability to program an initial attenuation state at power up. The PE4314 covers a 31.5 dB attenuation range in a 0.5 dB step. It is capable of maintaining 0.5 dB monotonicity through 2.5 GHz. In addition, no external blocking capacitors are required if 0 VDC is present on the RF ports. The PE4314 is manufactured on Peregrine’s UltraCMOS® process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate. ©2015–2016, Peregrine Semiconductor Corporation. All rights reserved. • Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Peregrine’s HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Optional External VSS For proper operation, the VSS_EXT pin must be grounded or tied to the VSS voltage specified in Table 2. When the VSS_EXT pin is grounded, FETs in the switch are biased with an internal negative voltage generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied externally to bypass the internal negative voltage generator. Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 • Absolute Maximum Ratings for PE4314 Parameter/Condition Min Max Unit Supply voltage, VDD –0.3 5.5 V Digital input voltage –0.3 3.6 V See Fig. 5 +30 dBm dBm +150 °C ESD voltage HBM(1), all pins 1500 V ESD voltage CDM(2), all pins 1000 V RF input power, 75Ω 1–30 MHz ≥30 MHz–2.5 GHz Storage temperature range –65 Notes: 1) Human body model (MIL-STD 883 Method 3015). 2) Charged device model (JEDEC JESD22-C101). Page 2 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Recommended Operating Conditions Table 2 lists the recommended operating conditions for the PE4314. Devices should not be operated outside the recommended operating conditions listed below. Table 2 • Recommended Operating Conditions for PE4314 Parameter Min Typ Max Unit 2.3 3.3 5.5 V 130 200 µA 3.4 5.5 V 50 80 µA –3.2 V Normal mode, VSS_EXT = 0V(1) Supply voltage, VDD Supply current, IDD Bypass mode, VSS_EXT = –3.4V(2) Supply voltage, VDD (Table 3 spec compliance applies for VDD ≥ 3.4V.) 2.7 Supply current, IDD Negative supply voltage, VSS_EXT –3.6 Negative supply current, ISS –40 –16 µA Normal or bypass mode Digital input high 1.17 3.6 V Digital input low –0.3 0.6 V Digital input current(3) 20 µA RF input power, CW(4) 1–30 MHz ≥30 MHz–2.5 GHz Fig. 5 +24 dBm dBm RF input power, pulsed(5) 1–30 MHz ≥30 MHz–2.5 GHz Fig. 5 +27 dBm dBm +105 °C Operating temperature range –40 +25 Notes: 1) Normal mode: connect VSS_EXT (pin 12) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. 2) Bypass mode: use VSS_EXT (pin 12) to bypass and disable internal negative voltage generator. 3) Applies to all pins except pins 1, 5, 7 and 20. Pins 1, 7 and 20 have an internal 1 MΩ pull-down resistor to ground and pin 5 has an internal 2 MΩ pull-up resistor to internal VDD. 4) 100% duty cycle, all bands, 75Ω. 5) Pulsed, 5% duty cycle of 4620 µs period, 75Ω. DOC-81718-1 – (02/2017) Page 3 www.psemi.com PE4314 RF Digital Step Attenuator Electrical Specifications Table 3 provides the PE4314 key electrical specifications @ +25 °C, ZS = ZL = 75Ω, unless otherwise specified. Normal mode(1) is @ VDD = 3.3V and VSS_EXT = 0V. Bypass mode(2) is @ VDD = 3.4V and VSS_EXT = –3.4V. Table 3 • PE4314 Electrical Specifications Parameter Condition Frequency Operating frequency Attenuation range Insertion loss Min Typ 1 MHz 0.5 dB step Reference state 1–204 MHz 204–870 MHz 870–1218 MHz 1218–2500 MHz 204–1218 MHz Any bit or bit combination 1218–1794 MHz Return loss 1–204 MHz 204–870 MHz Input and output ports, reference state 870–1794 MHz 1794–2500 MHz Relative phase All states Input IP2 Two tones at +15 dBm 10 kHz spacing 0 dB and 31.5 dB attenuation states 2.5 GHz As shown dB 1.0 1.2 1.3 1.5 1.25 1.50 1.80 1.90 dB dB dB dB dB See Fig. 13– Fig. 17 ±(0.15 + 2% of attenuation setting) ±(0.15 + 3% of attenuation setting) ±(0.15 + 4% of attenuation setting) ± (0.15 + 8% of attenuation setting) 1794–2500 MHz Input 0.1dB compression point(3) Unit 0–31.5 1–204 MHz Attenuation error Max dB dB dB 19 17 16 19 dB dB dB dB 870 MHz 1000 MHz 1218 MHz 9 11 14 deg deg deg 30–2500 MHz 30 dBm 5 MHz 10 MHz 17 MHz 35 MHz 500 MHz 1000 MHz 1900 MHz 2500 MHz Page 4 0 dB 31.5 dB 70 76 80 88 104 106 98 110 100 101 104 105 110 113 102 99 dBm dBm dBm dBm dBm dBm dBm dBm DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Table 3 • PE4314 Electrical Specifications (Cont.) Parameter Condition Input IP3 Two tones at +15 dBm 10 kHz spacing 0 dB and 31.5 dB attenuation states Video feed-through DC measurement Settling time Frequency 5 MHz 10 MHz 17 MHz 35 MHz 500 MHz 1000 MHz 1900 MHz 2500 MHz Min Typ Max 0 dB 31.5 dB 57 69 63 62 62 59 60 58 62 61 62 61 62 55 55 57 Unit dBm dBm dBm dBm dBm dBm dBm dBm 7 mVPP 50% CTRL to 0.05 dB of final value 1.8 µs Settling time 50% CTRL to 0.5 dB of final value 0.4 µs Switching time 50% CTRL to 90% or 10% RF 370 Attenuation transient (envelope) 250 MHz 0.5 700 ns dB Notes: 1) Normal mode: connect VSS_EXT (pin 12) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. 2) Bypass mode: use VSS_EXT (pin 12) to bypass and disable internal negative voltage generator. 3) The input 0.1dB compression point is a linearity figure of merit. Refer to Table 2 for the operating RF input power (75Ω). DOC-81718-1 – (02/2017) Page 5 www.psemi.com PE4314 RF Digital Step Attenuator Switching Frequency Table 4 • Thermal Data for PE4314 The PE4314 has a maximum 25 kHz switching frequency in normal mode (pin 12 tied to ground). A faster switching frequency is available in bypass mode (pin 12 tied to VSS_EXT). The rate at which the PE4314 can be switched is then limited to the switching time as specified in Table 3. Switching frequency is defined to be the speed at which the DSA can be toggled across attenuation states. Switching time is the time duration between the point the control signal reached 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. Spur-Free Performance The typical spurious performance of the PE4314 in normal mode is –158 dBm/Hz (pin 12 tied to ground). The spur fundamental occurs around 2.6 MHz and it has a bandwidth of 100 kHz. This results in a CATV band typical spurious level for frequencies above 5 MHz of –154 dBm. If spur-free performance is desired, the internal negative voltage generator can be disabled by applying a negative voltage to VSS_EXT (pin 12). Glitch-less Attenuation State Transitions The PE4314 features a novel architecture to provide the best-in-class glitch-less transition behavior when changing attenuation states. When RF input power is applied, the output power spikes are greatly reduced (0.5 dB) during attenuation state changes when comparing to previous generations of DSAs. Thermal Data Psi-JT (JT), junction top-of-package, is a thermal metric to estimate junction temperature of a device on the customer application PCB (JEDEC JESD51-2). Parameter Typ Unit Maximum junction temperature, TJMAX 124 °C JT 25 °C/W θJA, junction-to-ambient thermal resistance 74 °C/W (RF input power, CW = 24 dBm, +105 °C ambient) Truth Tables Table 5 and Table 6 provide the truth tables for the PE4314. Table 5 • Parallel Truth Table for PE4314(*) P/S C16 C8 C4 C2 C1 C0.5 Attenuation Setting RF1–RF2 0 0 0 0 0 0 0 Reference IL 0 0 0 0 0 0 1 0.5 dB 0 0 0 0 0 1 0 1 dB 0 0 0 0 1 0 0 2 dB 0 0 0 1 0 0 0 4 dB 0 0 1 0 0 0 0 8 dB 0 1 0 0 0 0 0 16 dB 0 1 1 1 1 1 1 31.5 dB Note: * Not all 64 possible combinations of C0.5–C16 are shown. Table 6 • Parallel Power-up Truth Table for PE4314(*) LE JT = (TJ – TT)/P 0 0 0 0 Reference IL where 0 0 0 1 8 dB JT = junction-to-top of package characterization 0 0 1 0 16 dB parameter, °C/W 0 0 1 1 31.5 dB TJ = die junction temperature, °C 0 1 X X Defined by C0.5–C16 TT = package temperature (top surface, in the center), °C PUP1 PUP2 Attenuation Setting RF1–RF2 P/S Note: * Power up with LE = 1 provides normal parallel operation with C0.5–C16, and PUP1 and PUP2 are not active. P = power dissipated by device, Watts Page 6 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Programming Options new data into the DSA. The Serial timing for the operation is defined by Figure 2 and Table 7. Parallel/Serial Selection Power-up Control Settings Either a Parallel or Serial interface can be used to control the PE4314. The P/S bit provides this selection, with P/S = LOW selecting the Parallel interface and P/S = HIGH selecting the Serial interface. The PE4314 always assumes a specifiable attenuation setting on power up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial Serial or Parallel control word is provided. Parallel Mode Interface The Parallel interface consists of six CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The Parallel interface timing requirements are defined by Figure 3, Table 8 and switching time in Table 3. For Latched Parallel programming, the latched enable (LE) should be held LOW while changing attenuation state control values, then pulsed LE HIGH to LOW (per Figure 3) to latch new attenuation state into the device. For Direct Parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches or jumpers). When the attenuator powers up in Serial mode (P/S = 1), the six control bits are set to whatever data is present on the six Parallel data inputs (C0.5–C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/S = 0) with LE = 0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up (PUP) control bits, PUP1 and PUP2, as shown in Table 6. Figure 2 • Serial Interface Timing Diagram LE Clock In Parallel mode, DATA and CLOCK (CLK) pins are “don’t care” and may be tied to logic LOW or logic HIGH. Data MSB LSB tLESUP tSDSUP Serial Interface The Serial interface is a 6-bit Serial-in, Parallel-out shift register buffered by a transparent latch. It is controlled by using three CMOS-compatible signals: DATA, CLK and LE. The DATA and CLK inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. Serial data is clocked in MSB first. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the Serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. tLEPW tSDHLD Figure 3 • Parallel Interface Timing Diagram LE Parallel Data C16:C0.5 The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the DOC-81718-1 – (02/2017) tPDSUP tLEPW tPDHLD Page 7 www.psemi.com PE4314 RF Digital Step Attenuator Serial Register Map Figure 4 provides the Serial programming register map for the PE4314. Figure 4 • Serial Register Map(*) MSB (first in) LSB (last in) B5 B4 B3 B2 B1 B0 C16 C8 C4 C2 C1 C0.5 Note: * For backward compatibility, the same programming scheme can be used. Table 7 • Serial Interface AC Characteristics(1) Parameter Min Serial data clock frequency, fCLK(2) Max Unit 10 MHz Serial clock HIGH time, tCLKH 30 ns Serial clock LOW time, tCLKL 30 ns LE set-up time after last clock rising edge, tLESUP 10 ns LE minimum pulse width, tLEPW 30 ns Serial data set-up time before clock rising edge, tSDSUP 10 ns Serial data hold time after clock rising edge, tSDHLD 10 ns Notes: 1) VDD = 3.3V or 5.0V, –40 °C < TA < +105 °C, unless otherwise specified. 2) fCLK is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fCLK specification. Table 8 • Parallel Interface AC Characteristics(*) Parameter Min Max Unit LE minimum pulse width, tLEPW 10 ns Data set-up time before rising edge of LE, tPDSUP 10 ns Data hold time after falling edge of LE, tPDHLD 10 ns Note: * VDD = 3.3V or 5.0V, –40 °C < TA < +105 °C, unless otherwise specified. Page 8 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Figure 5 • Power De-rating Curve, 1 MHz–2.5 GHz, –40 to +105 °C Ambient, 75Ω P0.1 dB Compression (≥ 30 MHz) Pulsed (≥ 30 MHz) CW & Pulsed (< 30 MHz) CW (≥ 30 MHz) 32 30 28 Input Power (dBm) 26 24 22 20 18 16 14 12 10 8 6 4 1.0 10.0 100.0 1000.0 Frequency (MHz) DOC-81718-1 – (02/2017) Page 9 www.psemi.com PE4314 RF Digital Step Attenuator Typical Performance Data Figure 6–Figure 27 show the typical performance data at +25 °C, VDD = 3.3V, ZS = ZL = 75Ω, unless otherwise specified. Figure 6 • Insertion Loss vs Temperature -40°C +25°C +85°C +105°C 0 Insertion Loss (dB) -1 -2 -3 -4 -5 -6 0 0.5 1 1.5 2 2.5 3 Frequency (GHz) Page 10 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Figure 7 • Input Return Loss vs Attenuation Setting 0 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB 0 Return Loss (dB) -10 -20 -30 -40 -50 -60 0 0.5 1 1.5 2 2.5 3 16 dB 31.5 dB 2.5 3 Frequency (GHz) Figure 8 • Output Return Loss vs Attenuation Setting 0 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 0 Return Loss (dB) -10 -20 -30 -40 -50 -60 -70 0 0.5 1 1.5 2 Frequency (GHz) DOC-81718-1 – (02/2017) Page 11 www.psemi.com PE4314 RF Digital Step Attenuator Figure 9 • Input Return Loss for 16 dB Attenuation Setting vs Temperature -40°C +25°C +85°C +105°C 0 Return Loss (dB) -10 -20 -30 -40 -50 -60 0 0.5 1 1.5 2 2.5 3 2.5 3 Frequency (GHz) Figure 10 • Output Return Loss for 16 dB Attenuation Setting vs Temperature -40°C +25°C +85°C +105°C 0 Return Loss (dB) -10 -20 -30 -40 -50 -60 -70 0 0.5 1 1.5 2 Frequency (GHz) Page 12 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Figure 11 • Relative Phase Error vs Attenuation Setting 0 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB 30 Relative Phase Error (deg) 25 20 15 10 5 0 -5 -10 0 0.5 1 1.5 2 2.5 Frequency (GHz) Figure 12 • Relative Phase Error for 31.5 dB Attenuation Setting vs Frequency 0.2 GHz 0.9 GHz 1.8 GHz 2.5 GHz 18 Relative Phase Error (deg) 16 14 12 10 8 6 4 2 0 -40 25 85 105 Temperature (°C) DOC-81718-1 – (02/2017) Page 13 www.psemi.com PE4314 RF Digital Step Attenuator Figure 13 • Attenuation Error @ 200 MHz vs Temperature(*) -40°C +25°C +85°C Upper Atten. Error Limit +105°C Lower Atten. Error Limit 1 Attenuation Error (dB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 4 8 12 16 20 24 28 32 28 32 Attenuation Setting (dB) Note: * Attenuation error limit @ ±(0.15 + 2% of attenuation setting). Figure 14 • Attenuation Error @870 MHz vs Temperature(*) -40°C +25°C +85°C Upper Atten. Error Limit +105°C Lower Atten. Error Limit Attenuation Error (dB) 1.5 1 0.5 0 -0.5 -1 -1.5 0 4 8 12 16 20 24 Attenuation Setting (dB) Note: * Attenuation error limit @ ±(0.15 + 3% of attenuation setting). Page 14 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Figure 15 • Attenuation Error @ 1218 MHz vs Temperature(*) -40°C +25°C +85°C Upper Atten. Error Limit +105°C Lower Atten. Error Limit Attenuation Error (dB) 1.5 1 0.5 0 -0.5 -1 -1.5 0 4 8 12 16 20 24 28 32 28 32 Attenuation Setting (dB) Note: * Attenuation error limit @ ±(0.15 + 3% of attenuation setting). Figure 16 • Attenuation Error @ 1790 MHz vs Temperature(*) -40°C +25°C +85°C Upper Atten. Error Limit +105°C Lower Atten. Error Limit Attenuation Error (dB) 1.5 1 0.5 0 -0.5 -1 -1.5 0 4 8 12 16 20 24 Attenuation Setting (dB) Note: * Attenuation error limit @ ±(0.15 + 4% of attenuation setting). DOC-81718-1 – (02/2017) Page 15 www.psemi.com PE4314 RF Digital Step Attenuator Figure 17 • Attenuation Error @ 2500 MHz vs Temperature(*) -40°C +25°C +85°C Upper Atten. Error Limit +105°C Lower Atten. Error Limit Attenuation Error (dB) 3 2 1 0 -1 -2 -3 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Note: * Attenuation error limit @ ±(0.15 + 8% of attenuation setting). Figure 18 • IIP3 vs Attenuation Setting (Low Frequencies) 0 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB 75.00 Input IP3 (dBm) 70.00 65.00 60.00 55.00 5 10 17 35 Frequency (MHz) Page 16 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Figure 19 • IIP3 vs Attenuation Setting (High Frequencies) 0 dB 0.5 dB 1 dB 2 dB 3.5 dB 31.5 dB 70.00 Input IP3 (dBm) 65.00 60.00 55.00 50.00 500 1000 1900 2500 Frequency (MHz) Figure 20 • IIP2 vs Attenuation Setting (Low Frequencies) 0 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB 110.00 105.00 Input IP2 (dBm) 100.00 95.00 90.00 85.00 80.00 75.00 70.00 65.00 5 10 17 35 Frequency (MHz) DOC-81718-1 – (02/2017) Page 17 www.psemi.com PE4314 RF Digital Step Attenuator Figure 21 • IIP2 vs Attenuation Setting (High Frequencies) 0 dB 0.5 dB 1 dB 2 dB 3.5 dB 31.5 dB 120.00 Input IP2 (dBm) 115.00 110.00 105.00 100.00 95.00 90.00 500 1000 1900 2500 Frequency (MHz) Figure 22 • 0.5 dB Step Error vs Frequency(*) 200 MHz 870 MHz 1218 MHz 1790 MHz 2500 MHz 0.5 0.4 Step Error (dB) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Note: * Monotonicity is held so long as step error does not cross below –0.5 dB. Page 18 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Figure 23 • 0.5 dB Step, Actual vs Frequency 200 MHz 870 MHz 1218 MHz 1790 MHz 2500 MHz 32 Actual Attenuation (dB) 28 24 20 16 12 8 4 0 0 4 8 12 16 20 24 28 32 Ideal Attenuation (dB) Figure 24 • 0.5 dB Major State Bit Error vs Attenuation Setting 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB 1 Attenuation Error (dB) 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 0 0.5 1 1.5 2 2.5 Frequency (GHz) DOC-81718-1 – (02/2017) Page 19 www.psemi.com PE4314 RF Digital Step Attenuator Figure 25 • 0.5 dB Attenuation Error vs Frequency 200 MHz 870 MHz 1218 MHz 1790 MHz 2500 MHz 1 Attenuation Error (dB) 0.5 0 -0.5 -1 -1.5 -2 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Figure 26 • Attenuation Transient (15.5–16 dB), Typical Switching Time = 370 ns Power (dBm) Envelope Power (dBm) -12 Trigger starts ~ 4230 ns -12.4 -12.8 Glitch = 0.28 dB -13.2 -13.6 -14 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 Time (ns) Page 20 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Figure 27 • Attenuation Transient (16–15.5 dB), Typical Switching Time = 370 ns Power (dBm) Envelope Power (dBm) -12 Glitch = 0.05 dB Trigger starts ~ 4230 ns -12.4 -12.8 -13.2 -13.6 -14 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 Time (ns) DOC-81718-1 – (02/2017) Page 21 www.psemi.com PE4314 RF Digital Step Attenuator Evaluation Kit Latched Parallel Programming Procedure The digital step attenuator evaluation board (EVB) was designed to ease customer evaluation of the PE4314 digital step attenuator. The PE4314 EVB supports Direct Parallel, Latched Parallel and Serial modes. For automated Latched Parallel programming, connect the USB dongle board and cable that is provided with the evaluation kit (EVK) from the USB port of the PC to the J1 header of the PE4314 EVB, and set the LE and D1–D6 SP3T switches to the EXTERNAL position. Position the Parallel/Serial (P/S) select switch to the Parallel position. The evaluation software is written to operate the DSA in Parallel mode. Ensure that the software GUI is set to Latched Parallel mode. Use the software GUI to enable the desired attenuation state. The software GUI automatically programs the DSA each time an attenuation state is enabled. Evaluation Kit Setup Connect the EVB with the USB dongle board and USB cable as shown in Figure 28. Direct Parallel Programming Procedure Direct Parallel programming is suitable for manual operation without software programming. For manual Direct Parallel programming, position the Parallel/ Serial (P/S) select switch to the Parallel position. The LE switch must be switched to HIGH position. Switches D1–D6 are SP3T switches that enable the user to manually program the parallel bits. When D1– D6 are toggled to the HIGH position, logic high is presented to the parallel input. When toggled to the LOW position, logic low is presented to the parallel input. Setting LE and D1–D6 to the EXTERNAL position presents as OPEN, which is set for software programming of Latched Parallel and Serial modes. Table 5 depicts the Parallel truth table. Serial Programming Procedure For automated Serial programming, connect the USB dongle board and cable that is provided with the EVK from the USB port of the PC to the J1 header of the PE4314 EVB, and set the LE and D1–D6 SP3T switches to the EXTERNAL position. Position the Parallel/Serial (P/S) select switch to the Serial position. The software GUI is written to operate the DSA in Serial mode. Use the software GUI to enable each setting to the desired attenuation state. The software GUI automatically programs the DSA each time an attenuation state is enabled. Figure 28 • Evaluation Kit for PE4314 Page 22 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Figure 29 • Evaluation Kit Layout for PE4314 DOC-81718-1 – (02/2017) Page 23 www.psemi.com PE4314 RF Digital Step Attenuator Pin Information Table 9 • Pin Descriptions for PE4314 This section provides pinout information for the PE4314. Figure 30 shows the pin map of this device for the available package. Table 9 provides a description for each pin. Pin No. Pin Name 1 C16(1)(2) 2 RF1(3) RF1 port 3 DATA Serial interface data input 4 CLK Serial interface clock input 5 LE(4) Serial interface latch enable input 6, 9 VDD Supply voltage C16 1 RF1 2 C0.5 C1 GND C2 C4 19 18 17 16 Pin 1 Dot Marking 20 Figure 30 • Pin Configuration (Top View) Exposed Ground Pad 15 C8 7 14 RF2 8 PUP2(1) 13 P/S 10, 11, 18 GND Description Parallel control bit, 16 dB PUP1(1)(2) Power-up control bit, MSB Power-up control bit, LSB VSS_EXT 12 LE 5 11 GND 13 P/S 14 RF2(3) RF2 port 15 C8(1) Parallel control bit, 8 dB 16 C4(1) Parallel control bit, 4 dB 17 C2(1) Parallel control bit, 2 dB 19 C1(1) Parallel control bit, 1 dB 20 C0.5(1)(2) Pad GND GND VDD PUP2 PUP1 VDD 10 12 9 4 8 CLK 7 3 6 DATA Ground VSS_EXT(5) External VSS negative control voltage Parallel/Serial mode select Parallel control bit, 0.5 dB Exposed pad: ground for proper operation Notes: 1) Ground PUP1, PUP2, C0.5, C1, C2, C4, C8 and C16 if not in use. 2) C0.5, C16 and PUP1 have an internal 1 MΩ pull-down resistor to ground. 3) RF pins 2 and 14 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is met. 4) LE (pin 5) has an internal 2 MΩ pull-up resistor to internal VDD. 5) Use VSS_EXT (pin 12) to bypass and disable internal negative voltage generator. Connect VSS_EXT (pin 12) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. Page 24 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Packaging Information This section provides packaging data including the moisture sensitivity level, package drawing, package marking and tape-and-reel information. Moisture Sensitivity Level The moisture sensitivity level rating for the PE4314 in the 20-lead 4 × 4 × 0.85 mm QFN package is MSL1. Package Drawing Figure 31 • Package Mechanical Drawing for 20-lead 4 × 4 × 0.85 mm QFN 0.10 C 4.00 A (2X) 2.15±0.05 0.28 (x20) 0.55±0.05 (x20) B 11 15 0.50 10 16 2.15±0.05 4.00 6 5 (2X) 4.40 1 0.18 2.00 Pin #1 Corner 0.18 TOP VIEW 2.20 20 0.23±0.05 (x20) 0.10 C 0.50 0.75 (x20) BOTTOM VIEW 0.435 SQ REF 2.20 4.40 RECOMMENDED LAND PATTERN 0.10 C 0.10 0.05 0.85±0.05 0.05 C C A B C ALL FEATURES SEATING PLANE 0.203 SIDE VIEW 0.05 C Top-Marking Specification Figure 32 • Package Marking Specifications for PE4314 4314 YYWW ZZZZZZ = YY = WW = ZZZZZZ = Pin 1 indicator Last two digits of assembly year Assembly work week Assembly lot code (maximum six characters) DOC-81718-1 – (02/2017) Page 25 www.psemi.com PE4314 RF Digital Step Attenuator Tape and Reel Specification Figure 33 • Tape and Reel Specifications for 20-lead 4 × 4 × 0.85 mm QFN Direction of Feed Section A-A P1 P0 see note 1 T P2 see note 3 D1 D0 A E F see note 3 B0 A0 K0 A W0 Notes: 1. 10 Sprocket hole pitch cumulative tolerance ±0.2 A0 B0 K0 D0 D1 E F P0 P1 P2 T W0 4.35 4.35 1.10 1.50 + 0.10/ -0.00 1.50 min 1.75 ± 0.10 5.50 ± 0.05 4.00 8.00 2.00 ± 0.05 0.30 ± 0.05 12.00 ± 0.30 2. Camber in compliance with EIA 481 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole Pin 1 Device Orientation in Tape Page 26 DOC-81718-1 – (02/2017) www.psemi.com PE4314 RF Digital Step Attenuator Ordering Information Table 10 lists the available ordering codes for the PE4314 as well as available shipping methods. Table 10 • Order Codes for PE4314 Order Codes Description Packaging Shipping Method PE4314B–Z PE4314 digital step attenuator Green 20-lead 4 × 4 mm QFN 3000 Units/T&R EK4314–02 PE4314 evaluation kit Evaluation kit 1/Box Document Categories Advance Information The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Sales Contact For additional information, contact Sales at sales@psemi.com. Disclaimers The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Patent Statement Peregrine products are protected under one or more of the following U.S. patents: patents.psemi.com Copyright and Trademark ©2015–2016, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo, UTSi and UltraCMOS are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Product Specification www.psemi.com DOC-81718-1 – (02/2017)