EK44820-01

PE44820 Document Category: Product Specification UltraCMOS® RF Digital Phase Shifter 8-bit, 1.7–2.2 GHz Features Figure 1 • PE44820 Functional Diagram • 8-bit full-range phase shifter of 358.6°; 180°, 90°, 45°, 22.5°, 11.2°, 5.6°, 2.8° and 1.4° bits • Low RMS phase and amplitude error 1.4° 2.8° 5.6° 11.2° 22.5° 45° 90° RF1 180° ▪ RMS phase error of 1.0° RF2 • High linearity of +60 dBm IIP3 • Extended narrow band frequency operation of 1.1–3.0 GHz • +105 °C operating temperature • Packaging – 32-lead 5 × 5 × 0.85 mm QFN Serial Interface ▪ RMS amplitude error of 0.1 dB SI VDD CLK Digital Interface VSS_EXT GND LE 8 • Active antenna arrays S/P = Parallel S/P P0... P7 Parallel Interface • Weather and military radar OPT • Base station transceivers 4 A0... A3 Serial Address SDO2 SDO1 CLKO LEO Applications S/P = Serial Product Description The PE44820 is a HaRP™ technology-enhanced 8-bit digital phase shifter (DPS) designed for use in a broad range of applications including: beamforming networks, distributed antenna systems, active antenna systems and phased array applications. This DPS covers a phase range of 358.6 degrees in 1.4 degree steps, maintaining excellent phase and amplitude accuracy across the nominal frequency band of 1.7–2.2 GHz. The PE44820 is also capable of extended frequency operation from 1.1–3.0 GHz for narrow band applications, as detailed in Application Note 45. An integrated digital control interface supports both serial and parallel programming of the phase setting. The PE44820 also features an external negative supply option for a faster switching frequency, and is offered in a 32-lead 5 × 5 × 0.85 mm QFN package. In addition, no external blocking capacitors are required if 0 VDC is present on the RF ports. The PE44820 is manufactured on pSemi’s UltraCMOS® process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate. pSemi’s HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. ©2015–2016, 2018, pSemi Corporation. All rights reserved. • Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Optional External VSS For proper operation, the VSS_EXT pin must be grounded or tied to the VSS voltage specified in Table 2. When the VSS_EXT pin is grounded, FETs in the switch are biased with an internal negative voltage generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied externally to bypass the internal negative voltage generator. Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 • Absolute Maximum Ratings for PE44820 Parameter/Condition Min Max Unit Supply voltage, VDD –0.3 5.5 V Negative supply voltage, VSS_EXT –3.6 –2.4 V Digital input voltage –0.3 3.6 V 28 dBm +150 °C 500 V Maximum input power Storage temperature range –65 ESD voltage HBM, all pins(*) Note: * Human body model (MIL-STD 883 Method 3015). Page 2 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Recommended Operating Conditions Table 2 lists the recommended operating conditions for the PE44820. Devices should not be operated outside the recommended operating conditions listed below. Table 2 • Recommended Operating Conditions for PE44820 Parameter Min Typ Max Unit 5.5 V 130 200 µA Supply voltage, VDD 3.3 5.5 V Supply current, IDD 50 80 µA –3.2 V Normal mode, VSS_EXT = 0V(1) Supply voltage, VDD 2.3 Supply current, IDD Bypass mode, VSS_EXT = –3.3V(2) Negative supply voltage, VSS_EXT –3.6 Negative supply current, ISS –40 –16 µA Normal or Bypass mode Digital input high 1.17 3.6 V Digital input low –0.3 0.6 V 15 µA Digital input current Digital input current, D4–D7(3) 200 RF input power, CW Operating temperature range –40 +25 µA 25 dBm +105 °C Notes: 1) Normal mode: connect VSS_EXT (pin 20) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. 2) Bypass mode: use VSS_EXT (pin 20) to bypass and disable internal negative voltage generator. 3) Typical current draw 200 µA @ 3.6V. Recommended operation at 1.8V reduces input current draw to 0.6 µA. DOC-43214-7 – (10/2018) Page 3 of 22 www.psemi.com PE44820 Digital Phase Shifter Electrical Specifications Table 3 provides the PE44820 key electrical specifications at +25 °C (ZS = ZL = 50Ω), unless otherwise specified. Normal mode(1) is at VDD = 3.3V and VSS_EXT = 0V. Bypass mode(2) is at VDD = 3.3V and VSS_EXT = –3.3V. Table 3 • PE44820 Electrical Specifications Parameter Condition Operating frequency Phase shift range LSB = 1.4° Number of bits Min Typ Max Unit 1.7 1.95 2.2 GHz +0 358.6 deg 8 bits Insertion loss Across all states RMS phase error Over all 256 states 1.0 deg RMS amplitude error Over all 256 states 0.1 dB Phase accuracy Across all states ±3 deg Attenuation variation Across all states ±0.50 dB 1.4° bit –0.60 deg 2.8° bit –0.40 deg 5.6° bit +0.05 deg 11.2° bit +0.25 deg 22.5° bit +0.50 deg 45° bit +0.25 deg 90° bit +1.75 deg 180° bit –0.65 deg Return loss 13 dB Input 0.1dB compression point(3) 28 dBm Input IP3 60 dBm 365 ns Phase accuracy relative to reference phase @ 1.95 GHz Settling time(4) 6 RF settled within 2 deg of final value 7.1 dB Notes: 1) Normal mode: single external positive supply used. 2) Bypass mode: both external positive supply and external negative supply used. 3) The input P0.1dB compression point is a linearity figure of merit. Refer to Table 2 for the operating RF input power (50Ω). 4) Use of VSS_EXT reduces the settling time. Page 4 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Switching frequency describes the time duration between switching events. Switching time is the time between the point the control signal LE reaches 50% of its final value and the point the RF output signal reaches within 10% or 90% of its target value. Switching Frequency The PE44820 has a maximum 25 kHz switching frequency in normal mode (pin 20 tied to ground). A faster switching frequency is available in bypass mode (pin 20 tied to VSS_EXT). Control Logic Table 4 and Table 5 provide the Serial/Parallel selection truth table and the Serial and Parallel truth table for the PE44820. Table 4 • Serial/Parallel Selection Truth Table for PE44820 P/S Pin Control Mode L Parallel H Serial Table 5 • Serial and Parallel Truth Table(*) Phase Control Setting Phase Shift Setting RF1–RF2 D0 D1 D2 D3 D4 D5 D6 D7 OPT L L L L L L L L L Reference phase H L L L L L L L L 1.4 deg L H L L L L L L L 2.8 deg L L H L L L L L L 5.6 deg L L L H L L L L L 11.2 deg L L L L H L L L L 22.5 deg L L L L L H L L L 45 deg L L L L L L H L H 90 deg L L L L L L L H L 180 deg H H H H H H H H H 358.6 deg L L L L L L L L H 1.4 deg Note: * Normal mode operation uses the OPT bit to synchronize the 90 degree bit optimizing the phase accuracy across all states. For additional information on the OPT bit, reference Application Note 45. DOC-43214-7 – (10/2018) Page 5 of 22 www.psemi.com PE44820 Digital Phase Shifter Figure 2 • Serial Control Register Map SDO1 LSB (first in) SI MSB (last in) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3 Phase Setting Word SDO2 Unit Address Word Phase Setting Word is derived directly from the Phase Setting. For example, to program the 205.3 degree setting at unit address 3: Unit Address Word: 1100 (Unit Address = 1 + 2) Phase Setting Word: Multiply the degree desired by 256 states divided by 360° and convert to binary 205.3° × (256 states / 360°) = state 146 state 146 → 01001001 LSB→MSB (205.3 deg setting = 2.8° + 22.5° + 180°) Program Word (LSB→MSB): 010010010 + 1100, OPT bit is synchronized to 90° bit Page 6 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Programming Options Parallel/Serial Selection Serial Interface Either a Parallel or Serial addressable interface can be used to control the PE44820. The P/S bit provides this selection, with P/S = LOW selecting the Parallel interface and P/S = HIGH selecting the Serialaddressable interface. The Serial addressable interface is a 13-bit Serial-In, Parallel-Out shift register buffered by a transparent latch. The 13 bits make up two words comprising 9 data and 4 address bits. The first word is the Phase Word, which controls the state of the DPS. The second Word is the Address Word, which is compared to the static (or programmed) logical states of the A0– A3 digital state; otherwise, its current state will remain unchanged. Figure 4 and Figure 6 illustrate examples of timing diagrams for programming a state. Parallel Mode Interface The Parallel interface consists of nine CMOScompatible control lines that select the desired phase state, as shown in Table 5. The Parallel interface timing requirements are defined by Figure 5 (Latched Parallel/Direct Parallel Timing Diagram) and Table 7 (Parallel and Direct Interface AC Characteristics). For Latched Parallel programming, the Latch Enable (LE) should be held LOW while changing phase state control values, then pulse LE HIGH to LOW (per Figure 5) to latch new phase state into device. For Direct Parallel programming, the LE line should be pulled HIGH. Changing a phase state control value will change the device state to a new phase. Direct mode is ideal for manual control of the device (using hardware, switches or jumpers). The Serial interface is controlled using three CMOScompatible signals: Serial In (SI), Clock (CLK) and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first, beginning with the Phase Word. SDO1 is provided to connect several devices in parallel to the serial bus. SDO1 is a non-inverting buffered output of SI. SDO1 changes state with SI without regard to CLK. This is useful to connect multiple devices with different serial addresses to the serial controller without the need for additional external logic buffers. SDO2 is the buffered output of the last bit of the internal shift register and changes state on the rising edge of the clock. DOC-43214-7 – (10/2018) Page 7 of 22 www.psemi.com PE44820 Digital Phase Shifter Figure 3 • Buffered SDO1 Serial Interface(*) TCLK TH TCLKH TCLKL TSU LE TLCLKH TSettle CLK D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3 SI D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3 SDO1 TOVSDO1 Register Data Default/Current Value New Value Note: * SDO1 data buffered with respect to SI and valid on rising edge of CLK. Figure 4 • SDO2 (Last Bit of Shift Register)—Single Write with Readback(*) TSU TCLK TH LE TOVSDO2 TCLKH TCLKL TSettle CLK D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3 DON’T CARE SI D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3 D0 SDO2 DON’T CARE DON’T CARE TOH Register Data Default/Current Value New Value TPD Note: * SDO2 data changes on rising edge of CLK and is valid on falling edge of CLK. Page 8 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Table 6 • Serial Interface AC Characteristics Parameter Min Serial clock period, TCLK Max Unit 100 ns Table 7 • Parallel and Direct Interface AC Characteristics Parameter Min Max Unit Serial clock HIGH time, TCLKH 30 ns Latch enable minimum pulse width, TLEPW 30 ns Serial clock LOW time, TCLKL 30 ns Parallel data setup time, TDISU 100 ns Last serial clock rising edge setup time to latch enable rising edge, TSETTLE 10 ns Parallel data hold time, TDIH 100 ns Parallel/Serial setup time, TPSSU 100 ns Latch enable min pulse width, TLEPW 30 ns Parallel/Serial hold time, TPSH 100 ns Serial data setup time, TSU 10 ns Digital register delay (internal), TPD 10 ns Serial data hold time, TH 10 ns Digital register delay (internal, direct mode only), TDIPD 5 ns Digital register delay (internal), TPD 10 ns SD01 and SD02 drive strength(*) 25 pF Serial data output propagation delay from SI to SDO1, TOVSD01 25 ns Serial data output propagation delay from CLK to SDO2, TOVSD02 25 ns Serial data output hold time from CLK rising edge, TOH 1 Figure 5 • Latched Parallel/Direct Parallel Timing Diagram ns P/S DI[OPT, D7:0] LE Note: * SD01/2 maximum capacitive load drive strength for clock period of 100 ns. TPSSU TPSH Valid TDISU TLEPW DO[OPT, D7:0] TDIPD DOC-43214-7 – (10/2018) TDIH Valid TPD Page 9 of 22 www.psemi.com PE44820 Digital Phase Shifter Typical Performance Data Figure 6–Figure 19 show the typical performance data at +25 °C, VDD = 3.3V and VSS_EXT = 0V, unless otherwise specified. Figure 6 • Relative Phase Error: OPT Bit Phase Error: OPT Bit 5 4 3 2 [deg] 1 0 -1 -2 -3 -4 -5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 Frequency [MHz] Page 10 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Figure 7 • Relative Phase Error: 180 Deg Bit Phase Error: 180° 5 4 3 2 [deg] 1 0 -1 -2 -3 -4 -5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2050 2100 2150 2200 Frequency [MHz] Figure 8 • Relative Phase Error: 90 Deg Bit Phase Error: 90° 5 4 3 2 [deg] 1 0 -1 -2 -3 -4 -5 1700 1750 1800 1850 1900 1950 2000 Frequency [MHz] DOC-43214-7 – (10/2018) Page 11 of 22 www.psemi.com PE44820 Digital Phase Shifter Figure 9 • Relative Phase Error: 45 Deg Bit Phase Error: 45° 5 4 3 2 [deg] 1 0 -1 -2 -3 -4 -5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 Frequency [MHz] Figure 10 • Relative Phase Error: 22.5 Deg Bit Phase Error: 22.5° 5 4 3 2 [deg] 1 0 -1 -2 -3 -4 -5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 Frequency [MHz] Page 12 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Figure 11 • Relative Phase Error: 11.25 Deg Bit Phase Error: 11.25° 5 4 3 2 [deg] 1 0 -1 -2 -3 -4 -5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2050 2100 2150 2200 Frequency [MHz] Figure 12 • Relative Phase Error: 5.6 Deg Bit Phase Error: 5.6° 5 4 3 2 [deg] 1 0 -1 -2 -3 -4 -5 1700 1750 1800 1850 1900 1950 2000 Frequency [MHz] DOC-43214-7 – (10/2018) Page 13 of 22 www.psemi.com PE44820 Digital Phase Shifter Figure 13 • Relative Phase Error: 2.8 Deg Bit Phase Error: 2.8° 5 4 3 2 [deg] 1 0 -1 -2 -3 -4 -5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2050 2100 2150 2200 Frequency [MHz] Figure 14 • Relative Phase Error: 1.4 Deg Bit Phase Error: 1.4° 5 4 3 2 [deg] 1 0 -1 -2 -3 -4 -5 1700 1750 1800 1850 1900 1950 2000 Frequency [MHz] Page 14 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Figure 15 • RMS Amplitude Error -40 °C 25 °C 85 °C 105 °C 1 0.9 0.8 0.7 [dB] 0.6 0.5 0.4 0.3 0.2 0.1 0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 Frequency [MHz] Figure 16 • RMS Phase Error -40°C 25°C 85°C 105°C 3 2.5 [deg] 2 1.5 1 0.5 0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 Frequency [MHz] DOC-43214-7 – (10/2018) Page 15 of 22 www.psemi.com PE44820 Digital Phase Shifter Figure 17 • Maximum Return Loss S11 Over All Major States -40 °C 25 °C 85 °C 105 °C -10 -15 -20 [dB] -25 -30 -35 -40 -45 -50 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2100 2150 2200 Frequency [MHz] Figure 18 • Maximum Return Loss S22 Over All Major States -40 °C 25 °C 85 °C 105 °C -10 -15 -20 [dB] -25 -30 -35 -40 -45 -50 1700 1750 1800 1850 1900 1950 2000 2050 Frequency [MHz] Page 16 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Figure 19 • Insertion Loss—Reference States -40 °C 25 °C 85 °C 105 °C -4 -4.5 -5 -5.5 [dB] -6 -6.5 -7 -7.5 -8 -8.5 -9 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 Frequency [MHz] DOC-43214-7 – (10/2018) Page 17 of 22 www.psemi.com PE44820 Digital Phase Shifter Evaluation Kit The PE44820 evaluation kit (EVK) includes hardware required to control and evaluate the functionality of the DPS. The DPS evaluation software can be downloaded at www.psemi.com and requires a PC running Windows® operating system to control the USB interface board. Refer to the PE44820 Evaluation Kit User’s Manual for more information. Figure 20 • Evaluation Kit Layout for PE44820 Page 18 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Pin Information This section provides pinout information for the PE44820. Figure 21 shows the pin map of this device for the available package. Table 8 provides a description for each pin. D0/A0 D1/A1 D2/A2 D3/A3 D4/LE0 D5/CLK0 D6/SDO1 D7/SDO2 32 31 30 29 28 27 26 25 24 OPT 1 24 SI VDD 2 23 CLK S/P 3 22 LE GND 4 21 GND GND 5 20 VSS_EXT GND 6 19 GND RF1 7 18 RF2 GND 8 17 GND Table 8 • Pin Descriptions for PE44820 Pin No. 1 Pin Name OPT(1) Parallel: phase accuracy optimization bit. Serial: not used— must be tied low. VDD Supply voltage. 3 S/P Serial/parallel mode select. 4–6, 8–17, 19, 21 GND Ground. 7 RF1(2) RF1 port. 18 RF2(2) RF2 port VSS_EXT(3) 22 LE Description CLK Parallel: not used, optional tie high or low (internal pullup). Serial: serial interface clock input. SI Parallel: not used, optional tie high or low (internal pullup). Serial: serial interface data input. 25 Parallel—D7 180° bit/serial data D7/SDO2(4)(6)(8) out 2. 26 Parallel—D6 90° bit/serial data D6/SDO1(4)(6)(8) out 1. Parallel—D5 45° bit/serial-buffered CLK out. 27 D5/CLKO(6)(8) 28 D4/LEO(6)(8) 29 D3/A3 Parallel—D3 11.2° bit/serial A3 address bit. 30 D2/A2 Parallel—D2 5.6° bit/serial A2 address bit. 31 D1/A1 Parallel—D1 2.8° bit/serial A1 address bit. 32 D0/A0 Parallel—D0 1.4° bit/serial A0 address bit. Pad GND Exposed pad: Ground for proper operation. Description 2 20 Pin Name 16 GND 15 GND 14 GND 13 GND 12 GND 11 GND 10 GND GND 9 Exposed Ground Pad Pin No. 23 Figure 21 • Pin Configuration (Top View) Pin 1 Dot Marking Table 8 • Pin Descriptions for PE44820 (Cont.) Parallel—D4 22.4° bit/serial buffered LE out. Notes: 1) OPT bit is used to optimize the phase accuracy across all states. OPT bit (pin 1) must be synchronized to the 90° bit (pin 26) for normal operation. 2) RF1 and RF2 (pins 7 and 18) are bi-directional. 3) Use VSS_EXT (pin 20) with negative supply (VSS_EXT = –3.4V) to bypass and disable internal negative voltage generator. Connect VSS_EXT (pin 20) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. 4) SDO2 is buffered output of the last bit of the internal shift register. 5) SDO1 is a buffered output of the serial data input. 6) D4–D7 (pins 25–28) are bi-directional pins. External VSS negative supply voltage. Parallel: see table note(7). Serial: serial interface latch enable input. 7) LE operation in parallel mode: Holding LE HIGH while changing OPT, D7:D0 will immediately latch phase setting states into the device. Holding LE low while changing OPT,D7:D0 requires a rising edge on LE to latch the phase setting states into the device. 8) If not using buffered output in serial mode, leave floating. DOC-43214-7 – (10/2018) Page 19 of 22 www.psemi.com PE44820 Digital Phase Shifter Packaging Information This section provides packaging data including the moisture sensitivity level, package drawing, package marking and tape and reel information. Moisture Sensitivity Level The moisture sensitivity level rating for the PE44820 in the 32-lead 5 × 5 × 0.85 mm QFN package is MSL1. Package Drawing Figure 22 • Package Mechanical Drawing for 32-lead 5 × 5 × 0.85 mm QFN 0.10 C A 5.00 (2X) 3.60±0.05 0.40±0.05 (x32) B 17 0.60 (x32) 24 0.30 (x32) 0.50 (x28) 0.50 (x28) 16 25 3.60±0.05 5.00 0.25±0.05 (x32) 0.10 C 3.65 5.40 32 9 8 1 (2X) 3.65 3.50 REF PIN #1 CORNER TOP VIEW 5.40 BOTTOM VIEW RECOMMENDED LAND PATTERN 0.10 C 0.10 0.05 0.85±0.05 0.05 C SEATING PLANE 0.203 REF C A B C ALL FEATURES 0.05 REF C SIDE VIEW Top-Marking Specification Figure 23 • Package Marking Specifications for PE44820 44820 YYWW ZZZZZZZ = YY = WW = ZZZZZZZ = Pin 1 indicator Last two digits of assembly year Assembly work week Assembly lot code (maximum seven characters) Page 20 of 22 DOC-43214-7 – (10/2018) www.psemi.com PE44820 Digital Phase Shifter Tape and Reel Specification Figure 24 • Tape and Reel Specifications for 32-lead 5 × 5 × 0.85 mm QFN Direction of Feed Section A-A P1 P0 see note 1 T P2 see note 3 D1 D0 A E F see note 3 B0 A0 K0 A0 B0 K0 D0 D1 E F P0 P1 P2 T W0 5.25 5.25 1.10 1.50 + 0.1/ -0.0 1.5 min 1.75 ± 0.10 5.50 ± 0.05 4.00 8.00 2.00 ± 0.05 0.30 ± 0.05 12.00 ± 0.30 A W0 Pin 1 Notes: 1. 10 Sprocket hole pitch cumulative tolerance ±0.2 2. Camber in compliance with EIA 481 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole Dimensions are in millimeters unless otherwise specified DOC-43214-7 – (10/2018) Device Orientation in Tape Page 21 of 22 www.psemi.com PE44820 Digital Phase Shifter Ordering Information Table 9 lists the available ordering codes for the PE44820 as well as available shipping methods. Table 9 • Order Codes for PE44820 Order Codes Description Packaging Shipping Method PE44820B–X PE44820 Digital phase shifter Green 32-lead 5 × 5 mm QFN 500 units/T&R EK44820–02 PE44820 Evaluation kit Evaluation kit 1/Box Document Categories Advance Information The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The datasheet contains preliminary data. Additional data may be added at a later date. pSemi reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The datasheet contains final data. In the event pSemi decides to change the specifications, pSemi will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Sales Contact For additional information, contact Sales at sales@psemi.com. Disclaimers The information in this document is believed to be reliable. However, pSemi assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. pSemi’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the pSemi product could create a situation in which personal injury or death might occur. pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Patent Statement pSemi products are protected under one or more of the following U.S. patents: patents.psemi.com Copyright and Trademark ©2015–2016, 2018, pSemi Corporation. All rights reserved. The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. Product Specification www.psemi.com DOC-43214-7 – (10/2018)