EK45140-02

Product Specification PE45140 Product Description Features  Monolithic drop in solution with no EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES The PE45140 is a HaRP™ technology-enhanced RF power limiter designed for use in tactical and military communications receivers, land mobile radio and other high performance power limiting applications. IG N S UltraCMOS® Power Limiter 20 MHz–2 GHz Unlike traditional PIN diode solutions the limiting threshold can be adjusted through a low current control voltage (VCTRL), eliminating the need for external components such as DC blocking capacitors, RF choke inductors, and bias resistors. external components required  Adjustable power limiting threshold from +22 dBm to +32 dBm  Max power handling  +47 dBm Pulsed (50W)  +40 dBm CW (10W)  Superior ESD rating and ESD protection This power limiter has symmetric RF ports that limit incident power up to 50W pulsed in both biased and unbiased conditions. It provides an extremely fast limiting response to undesired high power signals while delivering low insertion loss and high linearity under safe operating power levels. The PE45140 is manufactured on Peregrine’s UltraCMOS® process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate.  1 kV CDM on all pins  200V MM on all pins  Unbiased power limiting operation  Fast response and recovery time of 1 ns  Dual mode operation  Power limiting mode Figure 2. Package Type 12-lead 3x3 mm QFN O M Peregrine’s HaRP™ technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and  8 kV HBM on RF pins to GND POUT R R EC Figure 1. Functional Diagram P1dB RF2 N O T RF1 PIN Voltage Control and ESD VCTRL Document No. DOC-44014-4 │ www.psemi.com DOC-62357 ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 12 PE45140 Product Specification Table 1. Electrical Specifications @ +25°C (ZS = ZL = 50Ω ), unless otherwise noted Operating frequency Min Max Typ 20 Power limiting mode Unit 2000 S Condition 0.45 1.00 dB dB IG N Parameter MHz Insertion loss 20 MHz–1 GHz 1–2 GHz Return loss 20 MHz–1 GHz 1–2 GHz 16 10 dB dB P1dB / limiting threshold VCTRL = –2.5V @ 915 MHz VCTRL = –0.5V @ 915 MHz 32 22 dBm dBm Leakage power1 VCTRL = –2.5V @ 915 MHz VCTRL = –0.5V @ 915 MHz 31.5 29 VCTRL = –1.0V @ 915 MHz 0.4 VCTRL = 0V 23.5 Input IP2 VCTRL = –2.5V @ 915 MHz 104 dBm Input IP3 VCTRL = –2.5V @ 915 MHz 64 dBm 1 GHz 1 ns Leakage power1 VCTRL = +2.5V @ 915 MHz –1 Switching time3 State change to 10% RF 390 Unbiased leakage power 1 Response / recovery time Power reflecting mode 34 31.5 dBm dBm dB/dB 27 4.5 dBm dBm µs 1. Measured with +40 dBm CW applied at input. 2. This mode requires the control voltage to toggle between +2.5V and -2.5V. At +2.5V, the limiter equivalent circuit is a low impedance to ground, reflecting most of the incident power back to the source. 3. State change is VCTRL toggle from –2.5V to +2.5V. R N O T R EC O M Notes: 2 EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES Leakage power slope 0.20 0.60 ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 12 Document No. DOC-44014-4 │ UltraCMOS® RFIC Solutions PE45140 Product Specification Table 3. Operating Ranges DC voltage Control voltage Power limiting mode Power reflecting mode RF input power, CW1 VDC 2.5 –2.5 –2.5 Max Unit 3.3 V –0.5 +2.5 V V 40 dBm PMAX,PULSED 47 dBm PMAX,UNB 47 dBm +85 °C +270 °C VCTRL PMAX,CW 2 RF input power, unbiased Table 2. Pin Descriptions Pin No. Pin Name 1, 3, 4, 6, 7, 9 GND Ground 2 RF1* RF port 1 5 VCTRL Control 8 RF2* RF port 2 2,3 Operating temperature range TOP Operating junction temperature1 TJ Notes: Typ –55 +25 1. CW, 100% duty cycle, in 10 min, 50Ω 2. Pulsed, 0.1% duty cycle of 1 µs pulse width in 10 min, 50Ω Table 4. Absolute Maximum Ratings Description Symbol Min Max Unit VDC -0.3 3.6 V Control voltage Power limiting mode Power reflecting mode VCTRL –3.3 3.6 V Storage temperature range TST –65 +150 °C Parameter DC voltage 1 DC voltage ESD voltage HBM All pins RF pins to GND VESD,HBM 7000 8000 V V Exposed pad: Ground for proper operation ESD voltage MM2, all pins VESD,MM 200 V VESD,CDM 1000 V 10, 12 N/C No connect 11 VDC Pad GND Note: * RF pins 2 and 8 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is 3 ESD voltage CDM , all pins Notes: M Latch-Up Avoidance O Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. EC Min EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES RF input power, pulsed R Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE45140 in the 12-lead 3x3 mm QFN package is MSL1. N O T R Symbol S Parameter IG N Figure 3. Pin Configuration (Top View) Document No. DOC-44014-4 │ www.psemi.com 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7) 2. Machine Model (JEDEC JESD22-A115) Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 12 PE45140 Product Specification Dual Mode Operation The PE45140 has the unique capability of being used as a voltage clamp in the event of an ESD strike. Clamping the output voltage can protect devices that follow from ESD damage and enable overall system ESD ratings to be increased. Power Limiting Mode The PE45140 performs as a linear power limiter with adjustable P1dB / limiting threshold. The P1dB / limiting threshold can be adjusted by changing the control voltage between –2.5V and –0.5V. If unbiased, or if VCTRL = 0V, the PE45140 still offers power limiting protection. EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES IG N S ESD Protection Capability The PE45140's ESD protection capability under biased and unbiased conditions is observed with a Transmission Line Pulse (TLP) measurement characterizing the product as an ESD clamp from Power Reflecting Mode Power reflecting mode requires a power detector to sample the RF input power and a microcontroller to toggle the limiter control voltage between +2.5V and –2.5V based on the system protection requirements. At +2.5V, the limiter impedance to ground is less than 1Ω and most of the incident power will be reflected back to the source. At –2.5V, the device operates as in power Table 5. Transmission Line Pulse Data vs. HBM VCTRL HBM (V) 0 1000 –1.5 1000 0 2000 –1.5 2000 0 3000 –1.5 3000 Max Current (A) Voltage (V) 0.7 4.5 0.7 14.5 1.3 8 1.3 16 2.0 11 2.0 17 Figure 4. Transmission Line Pulse Measurement 10 9 8 M 7 5 EC 4 3 R 2 T 1 Vctrl=0V R O Current (A) 6 Vctrl=‐1.5V 0 5 10 15 20 25 Voltage (V) N O 0 ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 12 Document No. DOC-44014-4 │ UltraCMOS® RFIC Solutions PE45140 Product Specification Table 5. Theta JC Theta JC Min Typ 16 Max Unit °C/W EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES Special consideration needs to be made in the design of the PCB to properly dissipate the heat away from the part and maintain the +270°C maximum junction temperature. Parameter S When limiting high power RF signals, the junction temperature of the power limiter can rise significantly. IG N Thermal Data R N O T R EC O M It is recommended to use best design practices for high power QFN packages: multi-layer PCBs with thermal vias in a thermal pad soldered to the slug of the package. Special care also needs to be made to alleviate solder voiding under the part. Document No. DOC-44014-4 │ www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 12 PE45140 Product Specification Typical Performance Data @ +25°C (ZS = ZL = 50Ω ), unless otherwise noted EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES IG N S Figure 5. Insertion Loss vs. Temperature Figure 7. Output Return Loss vs. Temperature R N O T R EC O M Figure 6. Input Return Loss vs. Temperature ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 12 Document No. DOC-44014-4 │ UltraCMOS® RFIC Solutions PE45140 Product Specification S Typical Performance Data @ +25°C, 915 MHz (ZS = ZL = 50Ω ), unless otherwise noted Figure 8. POUT vs. PIN Over VCTRL –1.5V –0.7V –0.5V 0V 2.5V –0.7V @ 915 MHz 40 –0.7V @ 2 GHz 35 35 EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES 30 30 25 Pout (dBm) 25 Pout (dBm) IG N –2.5V Figure 9. POUT vs. PIN Over Frequency @ VCTRL = –0.7V 20 15 10 20 15 10 5 5 0 ‐5 0 10 15 20 25 Pin (dBm) 30 35 40 Figure 10. P1dB vs. VCTRL Over Temperature P1dB @ –55°C (dBm) P1dB @ 25°C (dBm) 40 10 15 20 25 Pin (dBm) 30 35 40 Figure 11. POUT vs. PIN Over Frequency @ VCTRL = –1.5V P1dB @ 85°C (dBm) –1.5V @ 915 MHz –1.5V @ 2 GHz 35 30 35 M 25 Pout (dBm) 30 15 ‐2 20 15 10 5 ‐1.5 VCTRL (V) ‐1 ‐0.5 0 10 15 20 25 Pin (dBm) 30 35 N O T R ‐2.5 EC O 20 R P1dB (dBm) 25 Document No. DOC-44014-4 │ www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 12 40 PE45140 Product Specification Figure 13. IIP3 / IIP2 vs. PIN Over VCTRL IIP3 @ –55°C (dBm) IIP3 @ 25°C (dBm) IIP3 @ 85°C (dBm) IIP3 @ VCTRL = –2.5V (dBm) IIP2 @ VCTRL = –2.5V (dBm) IIP3 @ VCTRL = –1.5V (dBm) IIP2 @ –55°C (dBm) IIP2 @ 25°C (dBm) IIP2 @ 85°C (dBm) IIP2 @ VCTRL = –1.5V (dBm) IIP3 @ VCTRL = –0.7V (dBm) IIP2 @ VCTRL = –0.7V (dBm) IIP3 @ VCTRL = –0.5V (dBm) IIP2 @ VCTRL = –0.5V (dBm) 130 120 120 100 100 IIP3 / IIP2  (dBm) IIP3 / IIP2 (dBm) EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES 110 110 90 80 70 60 50 80 70 60 50 30 20 30 ‐2.5 ‐2 ‐1.5 VCTRL (V) ‐1 ‐0.5 Leakage Power (–55°C) @ Pmax  Leakage Power (85°C) @ Pmax 40 35 30 25 20 15 15 20 25 30 5 O 0 Leakage Power (25°C) @ Pmax ‐1 ‐0.5 0 VCTRL (V) 0.5 1 1.5 2 2.5 N O T ‐1.5 R ‐2 R ‐2.5 EC ‐5 ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 12 35 Figure 15. P1dB, IIP3, IIP2, Leakage Power @ PMAX vs. VCTRL M 10 10 Pin (dBm) Figure 14. Leakage Power @ PMAX vs. VCTRL Over Temperature Leakage Power (dBm) 90 40 40 ‐10 IG N Figure 12. IIP3 / IIP2 vs. VCTRL Over Temperature S Typical Performance Data @ +25°C, 915 MHz (ZS = ZL = 50Ω ), unless otherwise noted Document No. DOC-44014-4 │ UltraCMOS® RFIC Solutions PE45140 Product Specification IG N EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES The power limiter EVK board was designed to ease customer evaluation of Peregrine’s PE45140. The bi-directional RF input and output are connected to RF1 and RF2 port through a 50Ω transmission line via SMA connectors J2 and J3. A through 50Ω transmission line is available via SMA connectors J5 and J6. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The 2-pin connectors J1 and J4 are connected to the external DC voltage VDC and VCTRL, respectively. S Figure 16. Evaluation Board Layout Evaluation Kit PRT-51452 R N O T R EC O M The board is constructed of a four metal layer material with a total thickness of 62 mils. The top RF layer is Rogers RO4350B material with a 6.6 mil RF core and Er = 3.66. The middle layers provide ground for the transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 13.5 mils, trace gaps of 10 mils, and metal thickness of 2.1 mils. Document No. DOC-44014-4 │ www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 12 PE45140 Product Specification S Figure 17. Evaluation Board Schematic VDC IG N J1 1 1 2 2 R1 0 Ohm HEADER2 EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES C3 DNI U1 N/C 12 VDC 11 N/C 10 1 GND 2 RF1 3 GND C1 DNI 50 OHM GND 9 RF2 8 GND 7 13 DAP 50 OHM 4 GND 5 VCTRL 6 GND J2 PE45140 J3 J5 50 OHM J6 C2 DNI THRU C4 DNI R2 0 Ohm J4 1 1 2 2 HEADER2 DOC-44027 R N O T R EC O M Caution: Contains parts and assemblies susceptible to damage by electrostatic discharge (ESD) ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 12 Document No. DOC-44014-4 │ UltraCMOS® RFIC Solutions PE45140 Product Specification IG N A 0.30 (x12) 0.10 C (2X) 3.00 S Figure 18. Package Drawing 12-lead 3x3 mm QFN 0.50 1.80±0.10 B 0.30±0.05 (x12) (x8) 0.70 (x12) EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES 0.50 (x8) 3.00 1.80±0.10 1.90 3.10 0.25±0.05 (x12) 0.10 C 1.00 Ref. (2X) PIN #1 CORNER TOP VIEW BOTTOM VIEW 0.10 0.05 0.10 C 0.50±0.05 0.05 C SEATING PLANE SIDE VIEW 0.152 Ref. 1.90 3.80 0.02 RECOMMENDED LAND PATTERN C A B C DOC-52193 ALL FEATURES C = Pin 1 designator 45140 = Five digit part number R YYWW = Date code, last two digits of the year and work week ZZZZZ = Five digits of the lot number DOC-51207 N O T R EC O 45140 YYWW ZZZZZ M Figure 19. Top Marking Specifications Document No. DOC-44014-4 │ www.psemi.com ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 12 PE45140 Product Specification EP M LA EN C DE E D W F IT O H R PE NE 45 W 45 D 0 ES IG N S Figure 20. Tape and Reel Drawing M Table 6. Ordering Information Package Shipping Method PE45140 Power limiter Green 12-lead 3x3 mm QFN 500 units / T&R PE45140 Evaluation kit Evaluation kit 1 / box N O T R EK45140-02 Description R EC PE45140A-X O Order Code Sales Contact and Information For sales and contact information please visit www.psemi.com. ©2014 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 12 Document No. DOC-44014-4 │ UltraCMOS® RFIC Solutions