Product Specification
PE64906
UltraCMOS® Digitally Tunable Capacitor
(DTC)
100 - 3000 MHz
Product Description
PE64906 is a DuNE™ technology-enhanced digitally tunable
capacitor (DTC) based on Peregrine’s UltraCMOS®
technology. This highly versatile product supports a wide
variety of tuning circuit topologies with emphasis on
impedance matching and aperture tuning applications.
PE64906 offers high RF power handling and ruggedness
while meeting challenging harmonic and linearity
requirements enabled by Peregrine’s HaRP™ technology.
The device is controlled through the widely supported 3-wire
(SPI compatible) interface. All decoding and biasing is
integrated on-chip and no external bypassing or filtering
components are required.
DuNE devices feature ease of use while delivering superior
RF performance in the form of tuning accuracy, monotonicity,
tuning ratio, power handling, size, and quality factor. With
built-in bias voltage generation and ESD protection, DTC
products provide a monolithically integrated tuning solution
for demanding RF applications.
Features
3-wire (SPI compatible) serial interface
with built-in bias voltage generation and
ESD protection
DuNE™ technology enhanced
5-bit 32-state digitally tunable capacitor
Shunt configuration C = 0.9 pF to 4.6 pF
(5.1:1 tuning ratio) in discrete 119 fF
steps
High RF power handling (30 Vpk RF) and
linearity
Wide power supply range (2.3V to 4.8V)
and low current consumption
(typ. 140 μA at 2.75V)
High ESD tolerance of 2 kV HBM on all
pins
Applications include:
Tunable antennas
Tunable matching networks
Tunable filter networks
Phase shifters
Figure 1. Functional Diagram
Figure 2. Package Type
10-lead 2 x 2 x 0.55 mm QFN
RF-
RF+
ESD
Serial
Interface
ESD
CMOS Control
Driver and ESD
DOC-02169
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Page 1 of 11
PE64906
Product Specification
Table 1. Electrical Specifications @ 25 °C, VDD = 2.75V (In shunt configuration, RF- connected to GND)
Parameter
Condition
Min
Typ
Max
Unit
3000
MHz
Operating frequency
100
Minimum capacitance (Cmin) State = 00000, 100 MHz
0.81
0.9
0.99
pF
Maximum capacitance
(Cmax)
State = 11111, 100 MHz
3.68
4.6
5.52
pF
Tuning ratio
Cmax/Cmin, 100 MHz
5.1:1
Step size
5 bits (32 states), 100 MHz
0.119
Quality factor at Cmin1
698–960 MHz, with LS removed
1710–2170 MHz, with LS removed
40
40
Quality factor at Cmax1
698–960 MHz, with LS removed
1710–2170 MHz, with LS removed
29
13
Self resonant frequency
State 00000
State 11111
7.9
2.8
Harmonics2
2fo, 3fo: 698–915 MHz; PIN = +34 dBm, 50Ω
2fo, 3fo: 1710–1910 MHz; PIN = +32 dBm, 50Ω
–36
–36
dBm
dBm
IMD3
Bands I,II,V/VIII, +20 dBm CW @ TX freq,
–15 dBm CW @ 2TX-RX freq, 50Ω
–105
dBm
Third order intercept point
(IP3)
Shunt configuration derived from IMD3 spec
IP3 = (2PTX + Pblock – IMD3) / 2
Switching time3,4
State change to 10/90% delta capacitance between any two states
12
μs
Start-up time3
Time from VDD within specification to all performances within specification
70
μs
Wake-up time3,4
State change from Standby mode to RF state to all performances within specification
70
μs
pF
GHz
65
dBm
Notes: 1. Q for a shunt DTC based on a series RLC equivalent circuit
Q = XC / R = (X - XL) / R, where X = XL + XC , XL = 2*pi*f*L, XC = -1 / (2*pi*f*C), which is equal to removing the effect of parasitic inductance LS
2. In shunt between 50Ω ports. Pulsed RF input with 4620 μS period, 50% duty cycle, measured per 3GPP TS 45.005
3. DC path to ground at RF– must be provided to achieve specified performance
4. State change activated on falling edge of SEN following data word
©2017 Peregrine Semiconductor Corp. All rights reserved.
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Document No. DOC-82123-3
│ UltraCMOS® RFIC Solutions
PE64906
Product Specification
Figure 3. Pin Configuration (Top View)
Table 3. Operating Ranges
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
2.30
2.75
4.80
V
Supply current (VDD = 2.75V)
IDD
140
200
μA
Parameter
Standby current (VDD = 2.75V)
IDD
Digital input high
VIH
1.2
1.8
3.1
V
VIL
0
0
0.57
V
RF input power (50Ω)
698–915 MHz
1710–1910 MHz
+34
+32
dBm
dBm
Peak operating RF voltage2
VP to VM
VP to RFGND
30
30
Vpk
Vpk
Digital input low
25
μA
1
Table 2. Pin Descriptions
Pin #
Pin Name
1
RF-
Negative RF port1
2
RF-
Negative RF port1
3
GND
Ground2
4
VDD
Power supply pin
5
SCL
Serial interface clock input
6
SEN
Serial interface latch enable input
7
SDA
Serial interface data input
8
RF+
Positive RF port1
9
RF+
Description
Positive RF port1
Operating temperature range
TOP
–40
+25
+85
°C
Storage temperature range
TST
–65
+25
+150
°C
Notes: 1. Maximum power available from 50Ω source. Pulsed RF input with
4620 μS period, 50% duty cycle, measured per 3GPP TS 45.005
measured in shunt between 50Ω ports, RF- connected to GND
2. Node voltages defined per Equivalent Circuit Model Schematic
(Figure 13). When DTC is used as a part of reactive network,
impedance transformation may cause the internal RF voltages (VP, VM)
to exceed peak operating RF voltage even with specified RF input
power levels. For operation above about +20 dBm (100 mW), the
complete RF circuit must be simulated using actual input power and
load conditions, and internal node voltages (VP, VM in Figure 13)
monitored to not exceed 30 Vpk
Table 4. Absolute Maximum Ratings
Parameter/Condition
ESD Voltage HBM
*
Symbol
Min
VESD
Max
Unit
2000
V
10
GND
Ground
Note: * Human Body Model (MIL-STD-883 Method 3015.7)
Pad
GND
Exposed pad: ground for proper operation2
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted
to the limits in the Operating Ranges table.
Operation between operating range maximum and
absolute maximum for extended periods may
reduce reliability.
Notes:
2
1. For optimal performance, recommend tying Pins 1-2 and Pins 8-9
together on PCB
2. For optimal performance, recommend tying Pins 3, 10 and
exposed ground pad together on PCB
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE64906 in the 10-lead 2 x 2 x 0.55 mm QFN
package is MSL1.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
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Page 3 of 11
PE64906
Product Specification
Performance Plots @ 25 °C and 2.75V, unless otherwise specified
Figure 4. Measured Shunt C (@ 100 MHz) vs State
Figure 5. Measured Shunt S11 (major states)
5
Capacitance(pF)
4
C0
C1
C2
C4
C8
C15
C31
3
2
1
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
State
Figure 6. Measured Step Size vs State
(frequency)
Frequency(800 - 900 MHz)
Figure 7. Measured Shunt C vs Frequency
(major states)
1000
Capacitance(fF)
800
20
100 MHz
1000 MHz
2000 MHz
700
600
500
400
300
200
100
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
State
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Page 4 of 11
C0
C1
C2
C4
C8
C15
C31
17.5
15
Capacitance(pF)
900
12.5
10
7.5
5
2.5
0
0
0.5
1
1.5
Frequency(GHz)
Document No. DOC-82123-3
2
2.5
│ UltraCMOS® RFIC Solutions
PE64906
Product Specification
Figure 9. Measured Shunt Q vs State
Figure 8. Measured Shunt Q vs Frequency
(major states)
100
60
C0
C1
C2
C4
C8
C15
C31
80
70
Q
60
50
50
40
Q
90
698 MHz
960 MHz
1710 MHz
2170 MHz
30
40
20
30
20
10
10
0
0
0.5
1
1.5
2
Frequency(GHz)
2.5
3
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
State
Figure 10. Measured Self Resonance Frequency
vs State
q
y
Self Resonance Frequency (GHz)
8
7
6
5
4
3
2
1
0
0
5
10
15
20
State [0..31]
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25
30
©2017 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
PE64906
Product Specification
Serial Interface Operation and Sharing
The PE64906 is controlled by a three wire SPI-compatible
interface. As shown in Figure 11, the serial master
initiates the start of a telegram by driving the SEN (Serial
Enable) line high. Each bit of the 8-bit telegram is clocked
in on the rising edge of the SCL (Serial Clock) line. SDA
bits are clocked by most significant bit (MSB) first, as
shown in Table 5 and Figure 11. Transactions on SDA
(Serial Data) are allowed on the falling edge of SCL. The
DTC activates the data on the falling edge of SEN. The
DTC does not count how many bits are clocked and only
maintains the last 8 bits it received.
More than 1 DTC can be controlled by one interface by
utilizing a dedicated enable (SEN) line for each DTC.
SDA, SCL, and VDD lines may be shared as shown in
Figure 12. Dedicated SEN lines act as a chip select such
that each DTC will only respond to serial transactions
intended for them. This makes each DTC change states
sequentially as they are programmed.
Alternatively, a dedicated SDA line with common SEN
can be used. This allows all DTCs to change states
simultaneously, but requires all DTCs to be programmed
even if the state is not changed.
Figure 11. Serial Interface Timing Diagram (oscilloscope view)
tEOW
tESU
tDSU tDHD
tR
tF
tSCL
tEHD
tSCLH tSCLL
SEN
SCL
SDA
DTC Data
b0
b6
b7
b5
Dm-2
0
b6
1
0
1
b5
STB
2
b2
b1
b0
Dm
Figure 12. Recommended Bus sharing
b4
b3
b2
b1
b0
d4
d3
d2
d1
d0
MSB (first in)
Notes:
b3
Dm-1
Table 5. Register Map
b7
b4
LSB (last in)
1. These bits are reserved and must be written to 0 for proper operation
2. The DTC is active when low (set to 0) and in low-current stand-by
mode when high (set to 1)
DTC 1
RF+
VDD
VDD
SDA
SCL
SEN1
SEN2
SDA
SCL
SEN
GND
DGND
Table 6. Serial Interface Timing Characteristics
RF-
VDD = 2.75V, –40 °C < TA < +85 °C, unless otherwise specified
Symbol
Parameter
Min
Max
tSCL
Serial clock period
38.4
ns
tSCLL
SCL low time
13.2
ns
tSCLH
SCL high time
13.2
ns
tR
SCL, SDA, SEN rise time
6.5
ns
tF
SCL, SDA, SEN fall time
6.5
ns
tESU
SEN rising edge to SCL rising edge
19.2
ns
tEHD
SCL rising edge to SEN falling edge
19.2
ns
tDSU
SDA valid to SCL rising edge
13.2
ns
tDHD
SDA valid after SCL rising edge
13.2
ns
tEOW
SEN falling edge to SEN rising edge
38.4
ns
©2017 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 11
DTC 2
RF+
Unit
VDD
SDA
SCL
SEN
GND
DGND
RF-
Document No. DOC-82123-3
│ UltraCMOS® RFIC Solutions
PE64906
Product Specification
Table 8. Equivalent Circuit Data
Equivalent Circuit Model Description
The DTC Equivalent Circuit Model includes all
parasitic elements and is accurate in both series
and shunt configurations, reflecting physical circuit
behavior accurately and providing very close
correlation to measured data. It can easily be used
in circuit simulation programs.
For VP and VM max operating limits, refer to
Table 3.
Figure 13. Equivalent Circuit Model Schematic
LS
VP
RS
CS
VM
LS
RF+
RFCP1
CP2
RP2
RP2
RP1
RP1
RFGND
Table 7. Equivalent Circuit Model Parameters
State
Parasitic Elements
DTC Core
RP1
[Ω]
RP2
[kΩ]
0.61
8.0
25.0
0.62
11.0
25.0
0.51
0.63
14.0
25.0
3.08
0.50
0.64
17.0
25.1
0.89
3.12
0.49
0.65
20.0
25.2
5
1.02
3.05
0.48
0.66
23.0
25.4
6
1.14
2.93
0.48
0.67
26.0
25.6
00111
7
1.27
2.78
0.47
0.68
29.0
26.0
0x08
01000
8
1.40
2.64
0.46
0.69
32.0
26.5
0x09
01001
9
1.52
2.51
0.45
0.70
35.0
27.2
0x0A
01010
10
1.65
2.39
0.45
0.71
38.0
28.0
0x0B
01011
11
1.78
2.27
0.44
0.72
41.0
29.0
0x0C
01100
12
1.90
2.17
0.43
0.73
44.0
30.2
0x0D
01101
13
2.03
2.08
0.42
0.73
47.0
31.6
0x0E
01110
14
2.16
2.00
0.42
0.74
50.0
33.2
0x0F
01111
15
2.29
1.93
0.41
0.75
53.0
35.1
Hex
Bin
Dec
CS
[pF]
RS [Ω]
CP1
[pF]
CP2
[pF]
0x00
00000
0
0.38
1.40
0.52
0x01
00001
1
0.51
2.27
0.51
0x02
00010
2
0.63
2.83
0x03
00011
3
0.76
0x04
00100
4
0x05
00101
0x06
00110
0x07
Variable
Equation (state = 0, 1, 2…31)
Units
0x10
10000
16
2.41
1.86
0.40
0.76
56.0
37.3
CS
0.127*state + 0.38
pF
0x11
10001
17
2.54
1.80
0.39
0.77
59.0
39.7
RS
20/[state+20/(state+0.7)] + 0.7
Ω
0x12
10010
18
2.67
1.75
0.39
0.78
62.0
42.5
RP1
8+3*state
Ω
0x13
10011
19
2.79
1.70
0.38
0.79
65.0
45.6
RP2
25000+3*state^3
Ω
0x14
10100
20
2.92
1.65
0.37
0.80
68.0
49.0
CP1
–0.0075*state+0.52
pF
0x15
10101
21
3.05
1.61
0.36
0.81
71.0
52.8
CP2
0.0096*state+0.61
pF
0x16
10110
22
3.17
1.57
0.36
0.82
74.0
56.9
LS
0.35
nH
0x17
10111
23
3.30
1.54
0.35
0.83
77.0
61.5
0x18
11000
24
3.43
1.51
0.34
0.84
80.0
66.5
0x19
11001
25
3.56
1.48
0.33
0.85
83.0
71.9
0x1A
11010
26
3.68
1.45
0.33
0.86
86.0
77.7
0x1B
11011
27
3.81
1.42
0.32
0.87
89.0
84.0
0x1C
11100
28
3.94
1.40
0.31
0.88
92.0
90.9
0x1D
11101
29
4.06
1.37
0.30
0.89
95.0
98.2
0x1E
11110
30
4.19
1.35
0.30
0.90
98.0
106.0
0x1F
11111
31
4.32
1.33
0.29
0.91
101.0
114.4
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Page 7 of 11
PE64906
Product Specification
Series Operation
In series configuration, the effective capacitance
between RF+ and RF- ports is represented by CS
and tuning ratio as CSmax/CSmin.
Figure 16. Measured Series S11/S22 (major states)
S11 C0
S22 C0
S11 C1
Figure 14. Effective Capacitance Diagram
S22 C1
S11 C2
S22 C2
S11 C4
S22 C4
S11 C8
S22 C8
S11 C15
S22 C15
S11 C31
Shunt configuration (looking into RF+ when RF- is
grounded) will have higher total capacitance at RF+
due to parallel combination of CS with parasitic
capacitance CP1 (CS + CP1), as demonstrated in
Figure 15 and Table 9.
Figure 17. Measured Series S21 vs. Frequency
(major states)
0
-5
Figure 15. Typical Capacitance vs. State
-10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-15
dB(S21)
Capacitance
S22 C31
Frequency(.3 - 3000 MHz)
-20
C0
C1
C2
C4
C8
C16
C31
-25
-30
0
5
10
15
Capacitance in Series
Configuration (Cs)
-35
Capacitance in Shunt
Configuration (Cs+Cp1)
-40
20
25
30
State
Table 9. Effective Capacitance Summary
Effective
Capacitance
Cmin
(state 0)
Series (RF+ to RF-)
CS
0.38
4.32
11.4:1
Shunt (RF+ to GND)
CS + CP1
0.90
4.6
5.1:1
Configuration
Cmax
Tuning
(state 31) Ratio
0
0.5
1
1.5
2
Frequency (GHz)
2.5
3
When the DTC is used as a part of a reactive
network, impedance transformation may cause the
internal RF voltages (VP and VM in Figure 13) to
exceed peak operating RF voltage. The complete
RF circuit must be simulated using actual input
power and load conditions to ensure neither VP nor
VM exceeds 30 VPK.
S11 and S21 for series configuration is illustrated in
Figures 16 and 17. S21 includes mismatch and
dissipative losses and is not indicative of tuning
network loss. Equivalent Circuit Model can be used
for simulation of tuning network loss.
©2017 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 11
Document No. DOC-82123-3
│ UltraCMOS® RFIC Solutions
PE64906
Product Specification
Layout Recommendations
Evaluation Board
For optimal results, place a ground fill directly under
the DTC package on the PCB. Layout isolation is
desired between all control and RF lines. When
using the DTC in a shunt configuration, it is
important to make sure the RF-pin is solidly
grounded to a filled ground plane. Ground traces
should be as short as possible to minimize
inductance. A continuous ground plane is preferred
on the top layer of the PCB. When multiple DTCs
are used together, the physical distance between
them should be minimized and the connection
should be as wide as possible to minimize series
parasitic inductance.
The 101-0675 Evaluation Board (EVB) was designed
for accurate measurement of the DTC impedance
and loss. Two configurations are available: 1 Port
Shunt (J3) and 2 Port Shunt (J4, J5). Three
calibration standards are provided. The open (J2)
and short (J1) standards (104 ps delay) are used for
performing port extensions and accounting for
electrical length and transmission line loss. The Thru
(J9, J10) standard can be used to estimate PCB
transmission line losses for scalar de-embedding of
the 2 Port Series configuration (J4, J5).
Figure 18. Recommended Schematic of
Multiple DTCs
The board consists of a 4 layer stack with 2 outer
layers made of Rogers 4350B (εr = 3.48) and 2 inner
layers of FR4 (εr = 4.80). The total thickness of this
board is 62 mils (1.57 mm). The inner layers provide
a ground plane for the transmission lines. Each
transmission line is designed using a coplanar
waveguide with ground plane (CPWG) model using a
trace width of 32 mils (0.813 mm), gap of 15 mils
(0.381 mm), and a metal thickness of 1.4 mils
(0.051 mm).
Figure 20. Evaluation Board Layout
Figure 19. Recommended Layout of Multiple DTCs
101-0675
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Page 9 of 11
PE64906
Product Specification
Figure 21. Package Drawing
10-lead 2 x 2 x 0.55 mm QFN
2.00
A
0.90±0.05
(2X)
B
0.25
(x10)
0.25±0.05
(x10)
0.10 C
0.45
(x10)
0.50
(x6)
6
9
0.90±0.05
2.00
0.20±0.05
(X10)
2.40
0.95
4
0.10 C
1
0.50
(2X)
(x6)
0.95
2.40
1.50
Pin #1 Corner
RECOMMENDED LAND PATTERN
BOTTOM VIEW
TOP VIEW
DOC-01865
0.10 C
0.10
0.05
0.60 MAX
0.05 C
C A B
C
ALL FEATURES
SEATING PLANE
0.152
Ref.
C
0.05
Notes: 1. Dimensions are in millimeters
2. Dimensions and tolerances per
ASME Y14.5M, 1994
SIDE VIEW
Figure 22. Top Marking Specifications
PPZZ
YWW
17-0112
Package
Marking
PP
DG*
ZZ
00-99
Y
0-9
WW
01-53
Definition
Part number marking for PE64906
Last two digits of lot code
Last digit of year, starting from 2009
(0 for 2010, 1 for 2011, etc)
Work week
* Note: (PP), the package marking specific to the PE64906, is shown in the figure instead of
the standard Peregrine package marking symbol (P)
©2017 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 11
Marking Spec
Symbol
Document No. DOC-82123-3
│ UltraCMOS® RFIC Solutions
PE64906
Product Specification
Figure 23. Tape and Reel Specifications
Tape Feed Direction
Table 10. Ordering Information
Order Code
Description
Package
Shipping Method
PE64906B-Z
PE64906 DTC
10-lead 2x2 mm QFN
3,000 units/T&R
EK64906-12
PE64906 Evaluation kit
Evaluation kit
1 set/box
Document Categories
Disclaimers
Advance Information
The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in
any manner without notice.
The information in this document is believed to be reliable. However, Peregrine
assumes no liability for the use of this information. Use shall be entirely at the user’s
own risk. No patent rights or licenses to any circuits described in this document are
implied or granted to any third party. Peregrine’s products are not designed or
intended for use in devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any application in which the
failure of the Peregrine product could create a situation in which personal injury or
death might occur. Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of its products in such
applications.
Preliminary Specification
The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice
in order to supply the best possible product.
Product Specification
The datasheet contains final data. In the event Peregrine decides to change the
specifications, Peregrine will notify customers of the intended changes by issuing a
CNF (Customer Notification Form).
Patent Statement
Peregrine products are protected under one or more of the following U.S. patents:
patents.psemi.com.
Sales Contact
Copyright and Trademark
For additional information, contact Sales at sales@psemi.com.
©2017, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine
name, logo, UTSi and UltraCMOS are registered trademarks and HaRP, MultiSwitch
and DuNE are trademarks of Peregrine Semiconductor Corp.
Document No. DOC-82123-3 │ www.psemi.com
©2017 Peregrine Semiconductor Corp. All rights reserved.
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