PE29101A-X

PE29101 Document Category: Product Specification UltraCMOS® High-speed FET Driver, 40 MHz Features Figure 1 • PE29101 Functional Diagram • High- and low-side FET drivers • Fast propagation delay, 11 ns LI FE VDD • Dead-time control Sync Boot Switch • Internal gate overvoltage management • Sub-nanosecond rise and fall time HSB UVLO • 2A/4A peak source/sink current IN • Package – flip chip VDDSYNC Dead Time Controller Level Shifter Output Driver HSGPU HSGPD HSS Logic LSB EN Level Shifter RDHL Applications Output Driver RDLH • DC–DC conversions • Wireless power O Product Description LSO F • LiDAR LSGPD LSS GND • AC–DC conversions LSGPU The PE29101 integrated high-speed driver is designed to control the gates of external power devices, such as enhancement mode gallium nitride (GaN) FETs. The outputs of the PE29101 are capable of providing switching transition speeds in the sub-nanosecond range for switching applications up to 40 MHz. High switching speeds result in smaller peripheral components and enable new applications such as wireless power charging. D The PE29101 operates from 4V to 6.5V and can support a high side floating supply voltage of 80V. An optional internal synchronous bootstrap circuit limits overcharging of the bootstrap capacitor during reverse body diode conduction, preventing the GaN FETs from exceeding their maximum gate-to-source voltage rating. The PE29101 also features a dead-time controller that allows timing of the LS and HS gates to eliminate any large shoot-through currents that could dramatically reduce the efficiency of the circuit and potentially damage the transistors. EN The PE29101 is available in a flip chip package and is manufactured on Peregrine’s UltraCMOS process, a patented advanced form of silicon-on-insulator (SOI) technology, offering the performance of GaAs with the economy and integration of conventional CMOS. ©2018, pSemi Corporation. All rights reserved. • Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-78681-7 – (07/2019) www.psemi.com PE29101 High-speed FET Driver Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions Latch-up Immunity LI FE When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 • Absolute Maximum Ratings for PE29101 Parameter/Condition Min Max Unit –0.3 7 V –0.3 7 V Input signal –0.3 7 V HSS to LSS –5 100 V 1000 V Low-side bias (LSB) to low-side source (LSS) F High-side bias (HSB) to high-side source (HSS) ESD voltage HBM(*), all pins EN D O Note: * Human body model (JEDEC JS–001, Table 2A). Page 2 of 15 DOC-78681-7 – (07/2019) www.psemi.com PE29101 High-speed FET Driver Recommended Operating Conditions Table 2 lists the recommended operating conditions for the PE29101. Devices should not be operated outside the recommended operating conditions listed below. Table 2 • Recommended Operating Conditions for PE29101 Min Supply for driver front-end, VDD Supply for high-side bias (HSB) to high-side source (HSS) Supply for low-side bias (LSB) to low-side source (LSS) Logic HIGH for control input Logic LOW for control input HSS range Operating temperature Max Unit 4.0 5.0 6.5 V 4.0 5.0 6.5 V 4.0 5.0 6.5 V 1.6 6.5 V 0 0.6 V 0 80 V –40 +105 °C –40 +125 °C EN D O F Junction temperature Typ LI FE Parameter DOC-78681-7 – (07/2019) Page 3 of 15 www.psemi.com PE29101 High-speed FET Driver Electrical Specifications Table 3 provides the key electrical specifications @ +25 °C, VDD = 5V, 100 pF load; RDHL and RDLH are ±1% tolerance unless otherwise specified. Table 3 • DC Characteristics Condition DC Characteristics Min Typ Max Unit LI FE Parameter VDD = 5V, RDHL = RDLH = 80.6 kΩ 0.9 mA HSB quiescent current HSB = 5V 2.5 mA LSB quiescent current LSB = 5V 2.5 mA Total quiescent current VDD =HSB=LSB=5V, RDHL = RDLH = 80.6 kΩ 5.9 VDD quiescent current VDD = 6.5V, RDHL = RDLH = 80.6 kΩ 1.3 mA HSB quiescent current HSB = 6.5V 3.8 mA LSB quiescent current LSB = 6.5V 3.9 mA Total quiescent current VDD =HSB=LSB=6.5V, RDHL = RDLH = 80.6 kΩ Under Voltage Lockout Under voltage hysteresis Gate Drivers O Under voltage release (rising) F VDD quiescent current 8.0 mA 9.0 11.5 mA 3.6 3.9 V 400 mV HSGPU/LSGPU pull-up resistance VDD = 6.5V, RDHL = RDLH = 80.6 kΩ 1.8 Ω HSGPD/LSGPD pull-down resistance VDD = 6.5V 1.5 Ω 4.5 Ω D VDDSYNC resistance HSGPU/LSGPU leakage current HSB–HSGPU = 5V, LSB–LSGPU = 5V 10 µA HSGPD/LSGPD leakage current HSGPD–HSS = 5V/LSGPD–HSS = 5V 50 µA HSB=LSB, 80.6 kΩ resistor to GND 1.4 V RDHL = 30 kΩ 0.8 ns RDHL = 80.6 kΩ 3.3 ns RDHL = 150 kΩ 6.5 ns RDHL = 255 kΩ 11.1 ns EN Dead-time Control Dead-time control voltages Dead-time from HSG going low to LSG going high Page 4 of 15 DOC-78681-7 – (07/2019) www.psemi.com PE29101 High-speed FET Driver Table 3 • DC Characteristics (Cont.) Parameter Condition Typ Max Unit RDLH = 30 kΩ 0.2 ns RDLH = 80.6 kΩ 2.6 ns RDHL = 150 kΩ 5.6 ns RDHL = 255 kΩ Switching Characteristics LSG turn-off propagation delay LI FE Dead-time from LSG going low to HSG going high Min 10.0 ns 11.0 ns HSG rise time 10%–90% with 100pF load 1.0 ns LSG rise time 10%–90% with 100pF load 1.0 ns HSG fall time 10%–90% with 100pF load 1.0 ns LSG fall time 10%–90% with 100pF load 1.0 ns Minimum output pulse width RDLH = RDLH = 30 kΩ 2.0 Max switching frequency @ 50% duty cycle RDHL = RDLH = 80.6 kΩ ns 47 MHz F Control Logic 40 4.0 Table 4 provides the control logic truth table for the PE29101. O Table 4 • Truth Table for PE29101 IN HSGPU–HSS HSGPD–HSS LSGPU–LSS LSGPD–LSS L Hi–Z L H Hi–Z H H Hi–Z Hi–Z L H L Hi–Z L Hi–Z L H H Hi–Z L Hi–Z L EN L EN D L DOC-78681-7 – (07/2019) Page 5 of 15 www.psemi.com PE29101 High-speed FET Driver Typical Performance Data Figure 2 through Figure 4 show the typical performance data @ +25 °C, VDD = 5V, load = 100 pF capacitor, unless otherwise specified. VDD = 4.0V 9 8 7 6 5 4 3 2 1 0 -40 VDD = 5.0V F Total Quiescent Current (mA) 10 LI FE Figure 2 • Total Quiescent Current 25 VDD = 6.5V 105 EN D O Temperature (°C) Page 6 of 15 DOC-78681-7 – (07/2019) www.psemi.com PE29101 High-speed FET Driver Figure 3 • UVLO Threshold UVLO Rising UVLO Falling 3.8 LI FE 3.7 UVLO Threshold (V) 3.6 3.5 3.4 3.3 3.2 3.1 3 2.9 -40 25 105 F Temperature (°C) O Figure 4 • Dead Time 12.00 TDHL_ns 30K TDHL_ns 80.6K TDHL_ns 150K TDHL_ns 255K TDLH_ns 30K TDLH_ns 80.6K TDLH_ns 150K TDLH_ns 255K 8.00 6.00 EN Dead-time (ns) D 10.00 4.00 2.00 0.00 -60 -40 -20 0 20 40 60 80 100 120 Temperature (°C) DOC-78681-7 – (07/2019) Page 7 of 15 www.psemi.com PE29101 High-speed FET Driver Test Diagram Figure 5 shows the test circuit used to characterize the PE29101. Figure 5 • Test Circuit for PE29101 LI FE VDD Sync Boot Switch VDDSYNC VDD HSB UVLO HSGPU Level Shifter Output Driver F HSGPD Dead Time Controller EN RDHL HSS Logic O PWMIN 100 pF Level Shifter LSB LSGPU Output Driver LSGPD 100 pF LSS GND LSO EN D RDLH Page 8 of 15 DOC-78681-7 – (07/2019) www.psemi.com PE29101 High-speed FET Driver Theory of Operation General LI FE The PE29101 is intended to drive both the high-side (HS) and the low-side (LS) gates of external power transistors, such as enhancement-mode GaN FETs, for power management applications. The PE29101 is suited for applications requiring higher switching speeds due to the reduced parasitic properties of the high resistivity insulating substrate inherent with Peregrine’s UltraCMOS process. The driver uses a single-ended pulse width modulation (PWM) input that feeds a dead-time controller, capable of generating a small and accurate dead-time. The propagation delay of the dead-time controller must be small to meet the fast switching requirements when driving GaN FETs. The differential outputs of the dead-time controller are then level-shifted from a low-voltage domain to a high-voltage domain required by the output drivers. Each of the output drivers includes two separate pull-up and pull-down outputs allowing independent control of the turn-on and turn-off gate loop resistance. The low impedance output of the drivers improves external power FETs switching speed and efficiency, and minimizes the effects of the voltage rise time (dv/dt) transients. Under-voltage Lockout Dead-time Adjustment F An internal under-voltage lockout (UVLO) feature prevents the PE29101 from powering up before input voltage rises above the UVLO threshold of 3.6V (typ), and 400 mV (typ) of hysteresis is built in to prevent false triggering of the UVLO circuit. The UVLO must be cleared and the EN pin must be released before the part will be enabled. O The PE29101 features a dead-time adjustment that allows the user to control the timing of the LS and HS gates to eliminate any large shoot-through currents, which could dramatically reduce the efficiency of the circuit and potentially damage the GaN FETs. Two external resistors control the timing of outputs in the dead-time controller block. The timing waveforms are illustrated in Figure 6. D The dead-time resistors only affect the LS output; the HS output will always equal the duty-cycle of the input. The HS FET gate node will track the duty cycle of the PWM input, as both rising and falling edges are shifted in the same direction. The LS FET gate node duty cycle can be controlled with the dead-time resistors as each resistor will move the rising and falling edges in opposite directions. RDLH will change the dead-time from lowside gate (LSG) falling to high-side gate (HSG) rising and RDHL will change the dead-time from HSG falling to LSG rising. Figure 7 shows the resulting dead-time versus the external resistor values EN High-side Gate Overvoltage Protection In cases where the GaN transistor body diode conduction is significantly longer than the bootstrap diode turn-on time, overcharging of the bootstrap capacitor can develop. The resulting overvoltage on the high-side supply may exceed the specified operating range of the transistor. The PE29101 features an internal synchronous bootstrap protection circuit (pin 4) designed to limit overcharging of the bootstrap capacitor during reverse body diode conduction. DOC-78681-7 – (07/2019) Page 9 of 15 www.psemi.com PE29101 High-speed FET Driver Figure 6 and Figure 7 provide the dead-time description for the PE29101. Figure 6 • Typical Dead-time Description LI FE IN HSG-HSS tDLH LSG-LSS Figure 7 • Dead-time vs. Dead-time Resistor TDHL F 12 10 O 8 6 4 2 D Dead-time between HSG and LSG (ns) TDLH tDHL 0 EN 0 50 100 150 200 250 300 Dead-time Resistance (kΩ) Page 10 of 15 DOC-78681-7 – (07/2019) www.psemi.com PE29101 High-speed FET Driver Application Circuit LI FE Figure 8 shows a typical application diagram of the PE29101 and its external components in a half-bridge, open-loop configuration. The PE29101 drives the low-side gate of Q2 referenced to ground, and the floating high-side gate of Q1 referenced to the switch node (HSS). Pin 4 of the PE29101 is connected to an external Schottky bootstrap diode with fast recovery time. The internal synchronous boot circuit limits overcharging of the bootstrap capacitor during reverse body diode conduction, which could potentially damage Q1 by exceeding its specified gate-to source voltage. The external gate resistors are required to de-Q the inductance in the gate loop and dampen any ringing on the FET gates and the SW node. Dead-time resistors RDHL and RDLH can be adjusted to fine-tune the dead time and to reduce unwanted losses during dead-time periods. Figure 8 • Applications Diagram for PE29101 VDD Sync Boot Switch VDDSYNC HSB VDD VIN F UVLO HSGPU Level Shifter O HSGPD Dead Time Controller PWMIN Q1 Output Driver CB HSS VOUT Logic LSB LSGPU D EN Level Shifter Output Driver Q2 LSGPD RDHL EN RDLH LSS GND LSO DOC-78681-7 – (07/2019) Page 11 of 15 www.psemi.com PE29101 High-speed FET Driver Pin Configuration 5 4 3 RDLH VDDSYNC HSB 2 1 HSS HSGPD 7 6 IN EN HSGPU 11 10 9 GND LSO LSGPU 16 15 14 13 12 RDHL VDD LSB LSS LSGPD Pin Name 1 HSGPD D EN Description High-side gate drive pull-down 2 HSS High-side source 3 HSB High-side bias 4 VDDSYNC 5 RDLH Dead-time control resistor sets LSG falling to HSG rising delay (external resistor to GND) 6 HSGPU High-side gate drive pull-up 7(*) EN Enable active low, tri-state outputs when high 8(*) IN Control input 9 LSGPU 10(*) LSO Look ahead for LSGPU. LSO precedes LSGPU and LSGPD by 4 ns. Leave open if unused. 11 GND Ground 12 LSGPD 13 LSS Low-side source 14 LSB Low-side bias 15 VDD +5V supply voltage 16 RDHL O 2040 µm (−20 / +30 µm) Pin No. F 8 1640 µm (−20 / +30 µm) Figure 9 • Pin Configuration (Top View—Bumps Down) Table 5 • Pin Descriptions for PE29101 LI FE This section provides pin information for the PE29101. Figure 9 shows the pin map of this device for the available package. Table 5 provides a description for each pin. High-side gate synchronous boot control. Connect to anode of external Schottky diode. Low-side gate drive pull-up Low-side gate drive pull-down Dead-time control resistor sets HSG falling to LSG rising delay (external resistor to ground) Note: * Internal 100k pull down resistor Page 12 of 15 DOC-78681-7 – (07/2019) www.psemi.com PE29101 High-speed FET Driver Die Mechanical Specifications This section provides the die mechanical specifications for the PE29101. Table 6 • Die Mechanical Specifications for PE29101 Min Die size, singulated (x,y) Typ Max 2040 × 1640 Wafer thickness 180 200 Wafer size Test Condition Including sapphire, max tolerance = –20/+30 µm 220 µm µm Bump pitch 400 Bump height 85 Bump diameter 110 Figure 10 • Recommended Land Pattern for PE29101 2.040+0.03 -0.02 µm µm µm max tolerance = ±17 0.40 0.22 (x14) F 0.40 O 1.640+0.03 -0.02 Ø0.110±0.017 (x16) BUMPS DOWN 0.20±0.02 Unit LI FE Parameter BUMPS UP Ø0.090±0.008 (x16) RECOMMENDED LAND PATTERN D 0.085±0.013 EN SIDE VIEW DOC-78681-7 – (07/2019) Page 13 of 15 www.psemi.com PE29101 High-speed FET Driver Tape and Reel Specification This section provides tape-and-reel information for the PE29101. Figure 11 • Tape and Reel Specifications for the PE29101. P1 SEE NOTE 1 D1 P0 P2 D0 LI FE T SEE NOTE 3 A E Bo Ao Ko F SEE NOTE 3 Wo A Direction of Feed Tolerance +/- 0.05 +/- 0.05 +/- 0.05 +/- 0.1 +0.3 / -0.1 +/- 0.05 +/- 0.05 + 0.1 / - 0 +/- 0.1 +/- 0.1 +/- 0.05 +/- 0.05 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2. 2. Camber in compliance with EIA 481. 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. F Nominal 1.9 2.3 0.4 4.0 8.0 3.5 0.5 1.5 1.8 4.0 2.0 0.2 Pin 1 Device Orientation in Tape EN D O Pocket Ao Bo Ko P1 Wo F D1 D0 E P0 P2 T Page 14 of 15 DOC-78681-7 – (07/2019) www.psemi.com PE29101 High-speed FET Driver Ordering Information Table 7 lists the available ordering codes for the PE29101. Table 7 • Order Codes for PE29101 Description PE29101 flip chip PE29101A-Z PE29101 flip chip Advance Information Die on tape and reel 500 units/T&R Die on tape and reel 3000 units/T&R O Document Categories Shipping Method F PE29101A-X Packaging LI FE Order Codes The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The datasheet contains preliminary data. Additional data may be added at a later date. pSemi reserves the right to change specifications at any time without notice in order to supply the best possible product. D Product Specification The datasheet contains final data. In the event pSemi decides to change the specifications, pSemi will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Sales Contact EN For additional information, contact Sales at sales@psemi.com. Disclaimers The information in this document is believed to be reliable. However, pSemi assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. pSemi’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the pSemi product could create a situation in which personal injury or death might occur. pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Patent Statement pSemi products are protected under one or more of the following U.S. patents: patents.psemi.com Copyright and Trademark ©2018, pSemi Corporation. All rights reserved. The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. Product Specification www.psemi.com DOC-78681-7 – (07/2019)