Product Specification
PE4237
Product Description
The PE4237 RF Switch is designed to cover a broad range of applications from near DC to 4000 MHz. This reflective switch integrates on-board CMOS control logic driven by a single-pin, low voltage CMOS or TTL control input. Using a nominal +3volt power supply, a 1 dB compression point of +32 dBm can be achieved. The PE4237 also exhibits outstanding isolation of better than 43 dB at 1000 MHz and is offered in a small 3x3 mm DFN package. The PE4237 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram
RFC
SPDT UltraCMOS™ RF Switch DC - 4000 MHz Features • Single 3.0-volt power supply
• Low insertion loss: 0.35 dB at
1000 MHz, 0.45 dB at 2000 MHz
• High isolation of 43 dB at 1000 MHz,
35 dB at 2000 MHz
• Typical 1 dB compression point of
+32 dBm
• Single-pin CMOS or TTL logic control • Available in a 6-lead DFN package
Figure 2. Package Type
6-lead DFN
RF1
RF2
CMOS Control Driver
CTRL
Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 50 Ω)
Parameter
Operation Frequency1 Insertion Loss Isolation – RFC to RF1/RF2 Isolation – RF1 to RF2 Return Loss ‘ON’ Switching Time ‘OFF’ Switching Time Video Feedthrough2 Input 1 dB Compression Input IP3 2000 MHz 2000 MHz, 17 dBm 30 50 1000 MHz 2000 MHz 1000 MHz 2000 MHz 1000 MHz 2000 MHz 1000 MHz 2000 MHz 50% CTRL to 0.1 dB final value, 2 GHz 50% CTRL to 25 dB isolation, 2 GHz 41 33 33.5 26.5 19 10.5
Conditions
Minimum
DC
Typical
0.35 0.45 43 35 35 28 24 14 200 90 15 32
Maximum
4000 0.50 0.60
Units
MHz dB dB dB dB dB dB dB dB ns ns mVpp dBm dBm
Notes: 1. Device linearity will begin to degrade below 10 MHz. 2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50 Ω test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
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PE4237
Product Specification
Figure 3. Pin Configuration
RF2 GND RF1 1 2 3
Exposed Solder Pad - Shorted to Pin 2 (bottom side)
Table 4. Absolute Maximum Ratings
Symbol Parameter/Conditions
Power supply voltage Voltage on any input except for the CTRL input Voltage on CTRL input Storage temperature range Input power (50 Ω) ESD voltage (Human Body Model) -65
Min
-0.3 -0.3
Max
4.0 VDD+ 0.3 5.0 150 35 250
Units
V V V °C dBm V
6 5 4
RFC CTRL
VDD VI VCTRL TST
VDD
PIN VESD
Table 2. Pin Descriptions
Pin No.
1
Pin Name
RF2 RF2 port.1
Description
2
GND
Ground Connection. Traces should be physically short and connected to the ground plane. This pin is connected to the exposed solder pad that also must be soldered to the ground plane for best performance. RF1 port.
1
Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability.
Control Logic Input The control logic input pin (CTRL) is typically driven by a 3-volt CMOS logic level signal. For flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a standard 5-volt TTL control signal. This TTL control signal input must not exceed 5-volts or damage to the switch could result. Table 5. Control Logic Truth Table
Control Voltage Signal Path
RFC to RF1 RFC to RF2 CTRL = CMOS or TTL High
3 4
RF1 VDD
Nominal 3 V supply connection. CMOS or TTL logic level: High = RFC to RF1 signal path Low = RFC to RF2 signal path Common RF port for switch.1
5
CTRL
6
RFC
Notes: 1. All RF pins must be DC blocked with an external series capacitor or held at 0 VDC.
Table 3. Operating Ranges
Parameter
VDD Power Supply Voltage IDD Power Supply Current (VDD = 3V, VCNTL = 3V) TOP Operating temperature range Control Voltage High Control Voltage Low -40 0.7xVDD 0.3xVDD
Min
2.7
Typ
3.0 29
Max
3.3 35 85
Units
V µA °C V V
CTRL = CMOS or TTL Low
Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up.
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Document No. 70-0071-05 │ U ltraCMOS™ RFIC Solutions
PE4237
Product Specification
Typical Performance Data @ -40 °C to 85 °C (Unless Otherwise Noted)
Figure 4. Insertion Loss - RFC to RF1
Figure 5. Input 1dB Compression Point
0 -40 C -0.25
1dB Compression Point (dBm)
40 -40 8C
30 85 8C 25 8C
Insertion Loss (dB)
-0.5 85 C -0.75 25 C
20
-1
10
-1.25
-1.5 0 500 1000 1500 2000 2500 3000 3500 4000
0 0 500 1000 1500 2000 2500 3000
Frequency (MHz)
Frequency (MHz)
Figure 6. Insertion Loss - RFC to RF2
Figure 7. Isolation - RFC to RF1 T = 25 °C
0 -40 C -0.25
0
-20
Insertion Loss (dB)
-0.5 25 C
Isolation (dB)
85 C -0.75
-40
-60
-1
-1.25
-80
-1.5 0 500 1000 1500 2000 2500 3000 3500 4000
-100 0 500 1000 1500 2000 2500 3000 3500 4000
Frequency (MHz)
Frequency (MHz)
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PE4237
Product Specification
Typical Performance Data @ 25 °C
Figure 8. Isolation – RFC to RF2
Figure 9. Isolation – RF1 to RF2, RF2 to RF1
0
0
-20
-20
RF2
Isolation (dB)
Isolation (dB)
-40
-40 RF1
-60
-60
-80
-80
- 100 0 500 1000 1500 2000 2500 3000 3500 4000
- 100 0 500 1000 1500 2000 2500 3000 3500 4000
F requency (MHz)
F requency (MHz)
Figure 10. Return Loss – RFC to RF1, RF2
Figure 11. Return Loss – RF1, RF2
0
0
-10 Return Loss (dB) Return Loss (dB)
-10
RF2 -20 RF1 -30
-20
-30
-40 0 500 1000 1500 2000 2500 3000 3500 4000
-40 0 500 1000 1500 2000 2500 3000 3500 4000
Frequency (MHz)
F requency (MHz)
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Document No. 70-0071-05 │ U ltraCMOS™ RFIC Solutions
PE4237
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE4237 SPDT switch. The RF common port is connected through a 50 Ω transmission line to the top left SMA connector, J1. Port 1 and Port 2 are connected through 50 Ω transmission lines to the top two SMA connectors on the right side of the board, J2 and J3. A through transmission line connects SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.0476”, trace gaps of 0.030”, dielectric thickness of 0.028”, metal thickness of 0.0021” and εr of 4.4. J6 provides a means for controlling DC and digital inputs to the device. Starting from the lower left pin, the second pin to the right (J6-3) is connected to the device CNTL input. The fourth pin to the right (J6-7) is connected to the device VDD input. A decoupling capacitor (100 pF) is provided on both CTRL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance.
Figure 12. Evaluation Board Layouts
Peregrine Specification 101/0085
Figure 13. Evaluation Board Schematic
Peregrine Specification 102/0110
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PE4237
Product Specification
Figure 14. Package Drawing
6-lead DFN
NOTE: The exposed solder pad (on the bottom of the package) is electrically connected to pin 2 (fused.)
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Document No. 70-0071-05 │ U ltraCMOS™ RFIC Solutions
PE4237
Product Specification
Figure 15. Tape and Reel Specifications
6-lead DFN
Table 6. Dimensions
Dimension
Ao Bo Ko P W T R7 Quantity R13 Quantity
DFN 3x3 mm
3.23 ± 0.1 3.17 ± 0.1 1.37 ± 0.1 4 ± 0.1 8 +0.3, -0.1 0.254 ± 0.02 3000 N.A.
Note: R7 = 7 inch Lock Reel, R13 = 13 inch Lock Reel
Table 7. Ordering Information
Order Code
4237-51 4237-52 4237-00
Part Marking
4237 4237 PE4237-EK
Description
PE4237G-06DFN 3x3mm-12800F PE4237G-06DFN 3x3mm-3000C PE4237-06DFN 3x3mm-EK
Package
Green 6-lead 3x3 mm DFN Green 6-lead 3x3 mm DFN Evaluation Kit
Shipping Method
Tape or loose 3000 units / T&R 1 / Box
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PE4237
Product Specification
Sales Offices
The Americas Peregrine Semiconductor Corporation
9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499
North Asia Pacific Peregrine Semiconductor K.K.
Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213
Europe Peregrine Semiconductor Europe
Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73
Peregrine Semiconductor, Korea
#B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305
South Asia Pacific Peregrine Semiconductor, China
Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652
Space and Defense Products
Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
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Document No. 70-0071-05 │ U ltraCMOS™ RFIC Solutions
