PE43073

Product Specification PE43703 Product Description The PE43703 is a HaRP™-enhanced, high linearity, 7-bit RF Digital Step Attenuator (DSA). This highly versatile DSA covers a 31.75 dB attenuation range in 0.25 dB, 0.5 dB, or 1.0 dB steps. The customer can choose which step size and associated specifications are best suited for their application. The Peregrine 50Ω RF DSA provides multiple CMOS control interfaces and an optional external Vss feature. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with Vdd due to on-board regulator. This next generation Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint. The PE43703 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Package Type 32-lead 5x5x0.85 mm QFN Package 50 Ω RF Digital Attenuator 7-bit, 31.75 dB, DC-6.0 GHz, VssEXT option Features • HaRP™-enhanced UltraCMOS™ device • Attenuation options: 0.25 dB, 0.5 dB, or 1.0 dB steps to 31.75 dB • 0.25 dB monotonicity for ≤ 4.0 GHz • 0.5 dB monotonicity for ≤ 5.0 GHz • 1 dB monotonicity for ≤ 6.0 GHz • High Linearity: Typical +59 dBm IIP3 • Excellent low-frequency performance • Optional External Vss Control (VssEXT) • 3.3 V or 5.0 V Power Supply Voltage • Fast switch settling time • Programming Modes: Direct Parallel Latched Parallel • Serial-Addressable: Program up to eight addresses 000 - 111 • High-attenuation state @ power-up (PUP) • • • CMOS Compatible • No DC blocking capacitors required Figure 2. Functional Schematic Diagram Switched Attenuator Array RF Input RF Output Parallel Control Serial In 7 Control Logic Interface CLK LE (optional) VssEXT ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 15 A0 A1 A2 P/S Document No. 70-0245-04 │ www.psemi.com PE43703 Product Specification Table 1. Electrical Specifications: 0.25 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND Parameter Frequency Range Attenuation Range Insertion Loss Attenuation Error Return Loss Relative Phase P1dB IIP3 Typical Spurious Value1 Video Feed Through Switching Time RF Trise/Tfall Settling Time 50% DC CTRL to 10% / 90% RF 10% / 90% RF RF settled to within 0.05 dB of final value. RBW = 5 MHz, Averaging ON. All States Input Two tones at +18 dBm, 20 MHz spacing VssEXT grounded 0 dB - 7.75 dB Attenuation settings 8 dB - 31.75 dB Attenuation settings 0 dB - 31.75 dB Attenuation settings 0.25 dB Step DC ≤ 4 GHz DC < 3 GHz DC < 3 GHz 3 GHz ≤ 4 GHz DC - 4 GHz DC - 4 GHz 20 MHz - 4 GHz 20 MHz - 4 GHz 1MHz 30 18 44 32 59 -110 10 650 400 4 25 Test Conditions Frequency Min Typical DC – 4 0 – 31.75 1.9 Max Units GHz dB 2.4 ±(0.2+1.5%) ±(0.15+4%) ±(0.25+4.5%) dB dB dB dB dB deg dBm dBm dBm mVpp ns ns µs Note: 1. To prevent negative voltage generator spurs, supply –2.7 volts to VssEXT. Performance Plots, 0.25 dB state Figure 3. 0.25 dB Step Error vs. Frequency* 200 MHz 2200 MHz 0.500 Figure 4. 0.25dB Attenuation vs. Attenuation State 0.25-dB PE43701 Attenuation 35 30 Attenuation dB Attenuation dB 900 MHz 1800 MHz 2200 MHz 3000 MHz 900 MHz 3000 MHz 1800 MHz 0.400 25 20 15 10 5 Step Error (dB.) 0.300 0.200 0.100 0.000 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB.) 0 0 5 10 15 20 Attenuation State 25 30 35 *Monotonicity is held so long as Step-Error does not cross zero Attenuation State Figure 5. 0.25 dB Major State Bit Error 0.25dB State 0.5 dB State 8dB State 1dB State 16dB State 2dB State 31.75dB State Figure 6. 0.25 dB Attenuation Error vs. Frequency 200 MHz 1.500 900 MHz 3000 MHz 1800 MHz 4000 MHz 2.00 1.50 4dB State 2200 MHZ 1.000 Attenuation Error (dB.) Bit Error (dB.) 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00 0.0 1.0 2.0 Frequency (GHz) 3.0 4.0 0.500 0.000 -0.500 -1.000 - 1.500 0.0 4.0 8.0 12.0 16.0 20.0 Attenuation Setting (dB.) 24.0 28.0 32.0 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 15 Document No. 70-0245-04 │ U ltraCMOS™ RFIC Solutions PE43703 Product Specification Table 2. Electrical Specifications: 0.5 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND Parameter Frequency Range Attenuation Range Insertion Loss Attenuation Error Return Loss Relative Phase P1dB IIP3 Typical Spurious Value Video Feed Through Switching Time RF Trise/Tfall Settling Time 50% DC CTRL to 10% / 90% RF 10% / 90% RF RF settled to within 0.05 dB of final value. RBW = 5 MHz, Averaging ON. 1 Test Conditions 0.5 dB Step Frequency Min Typical DC – 5 0 – 31.5 Max Units GHz dB DC ≤ 5 GHz 0 dB - 31.5 dB Attenuation settings 0 dB - 16.5 dB Attenuation settings 17 dB - 31.5 dB Attenuation settings All States Input Two tones at +18 dBm, 20 MHz spacing VssEXT grounded DC < 4 GHz 4 ≤ 5 GHz 4 ≤ 5 GHz DC - 5 GHz DC - 5 GHz 20 MHz - 5 GHz 20 MHz - 5 GHz 1 MHz 30 2.0 2.6 ±(0.25+4.5%) ±(0.3+5%) ±(1.3+0%) dB dB dB dB dB deg dBm dBm dBm mVpp ns ns 18 56 32 57 -110 10 650 400 4 25 µs Note: 1. To prevent negative voltage generator spurs, supply –2.7 volts to VssEXT. Performance Plots, 0.5 dB state Figure 7. 0.5 dB Step-Error vs. Frequency* 200 MHz 3000 MHz 1.000 Figure 8. 0.5 dB Attenuation vs. Attenuation State 0.5-dB PE43703 Attenuation 35 30 900 MHz 2200 MHz 3800 MHz 5000 MHz 900 MHz 4000 MHz 1800 MHz 5000 MHz 2200 MHz 0.750 Step Error (dB.) Attenuation dB Attenuation dB 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 25 20 15 10 5 0.500 0.250 0.000 0 0 5 10 15 20 Attenuation State 25 30 35 Attenuation Se tting (dB.) *Monotonicity is held so long as Step-Error does not cross zero Attenuation State Figure 9. 0.5 dB Major State Bit Error 0.5dB State 8dB State 2.00 1.50 Figure 10. 0.5 dB Attenuation Error vs. Frequency 4dB State 1.500 1.000 Attenuation Error (dB.) 1dB State 16dB State 2dB State 31.5dB State 200 MHz 3000 MHz 900 MHz 4000 MHz 1800 MHz 5000 MHz 2200 MHz 1.00 Bit Error (dB.) 0.50 0.00 -0.50 -1.00 -1.50 -2.00 0.0 1.0 2.0 Frequency (GHz) 3.0 4.0 5.0 0.500 0.000 -0.500 -1.000 -1.500 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Atte nuation Setting (dB.) Document No. 70-0245-04 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 15 PE43703 Product Specification Table 3. Electrical Specifications: 1 dB steps @ +25°C, VDD = 3.3 V or 5.0 V, VssEXT = -2.7 V or GND Parameter Frequency range Attenuation Range Insertion Loss 0 dB - 31 dB Attenuation settings 0 dB - 12 dB Attenuation settings 13 dB - 31 dB Attenuation setting 0 dB - 31 dB Attenuation settings All States Input Two tones at +18 dBm, 20 MHz spacing VssEXT grounded 50% DC CTRL to 10% / 90% RF 10% / 90% RF RF settled to within 0.05 dB of final value. RBW = 5 MHz, Averaging ON. 1 dB Step DC ≤ 6 GHz DC – 4 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz DC - 6 GHz DC - 6 GHz 20 MHz - 6 GHz 20 MHz - 6 GHz 1 MHz 30 18 74 32 53 -110 10 650 400 4 25 Test Conditions Frequency Min Typical DC – 6 0 - 31 2.3 Max Units GHz dB 2.8 ±(0.25+4.5%) +0.4+8% +1.4+0% -0.2-3% dB dB dB dB dB dB deg dBm dBm dBm mVpp ns ns µs Attenuation Error Return Loss Relative Phase P1dB IIP3 Typical Spurious Value1 Video Feed Through Switching Time RF Trise/Tfall Settling Time Note: 1. To prevent negative voltage generator spurs, supply –2.7 volts to VssEXT. Performance Plots, 1 dB state Figure 11. 1 dB Step-Error vs. Frequency* 200 MHz 3000 MHz 2.000 1.750 Figure 12. 1 dB Attenuation vs Attenuation State 1-dB PE43703 Attenuation 35 30 900 MHz 2200 MHz 3800 MHz 5800 MHz 900 MHz 4000 MHz 1800 MHz 5000 MHz 2200 MHz 6000 MHz AttenuationdB Attenuation dB 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 1.500 Step Error (dB.) 1.250 1.000 0.750 0.500 0.250 0.000 Attenuation Setting (dB.) 25 20 15 10 5 0 0 5 10 *Monotonicity is held so long as Step-Error does not cross zero Attenuation State 15 20 Attenuation State 25 30 35 Figure 13. 1 dB Major State Bit Error 2.00 1.50 Attenuation Error (dB.) 1dB State 8dB State 2dB State 16dB State 4dB State 31dB State Figure 14. 1dB Attenuation Error vs. Frequency 200 MHz 1.500 900 MHz 1800 MHz 2200 MHz 1.000 1.00 Bit Error (dB.) 0.50 0.00 -0.50 -1.00 -1.50 -2.00 0.0 1.0 2.0 3.0 Frequency (GHz) 4.0 5.0 6.0 0.500 0.000 -0.500 -1.000 - 1.500 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB.) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 15 Document No. 70-0245-04 │ U ltraCMOS™ RFIC Solutions PE43703 Product Specification Performance Plots, 1 dB state (continued) Figure 15. 1 dB Attenuation Error vs. Frequency 3000 MHz 1.500 Figure 16. Insertion Loss vs. Temperature -40C 0 -0.5 4000 MHz 5000 MHz 6000 MHz +25C +85C 1.000 Attenuation Error (dB.) Insertion Loss (dBm.) -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 0.500 0.000 -0.500 -1.000 -1.500 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Atte nuation Setting (dB.) -5 0.0 1.0 2.0 3.0 4.0 5.0 Frequency (GHz) 6.0 7.0 8.0 9.0 Figure 17. Input Return Loss vs. Attenuation T = +25C 0dB 0.25dB 8dB 0.5dB 16dB 1dB 31.75dB 2dB Figure 18. Output Return Loss vs. Attenuation T = +25C 0 -10 Return Loss (dB.) -20 -30 -40 -50 -60 0dB 4dB 0.25dB 8dB 0.5dB 16dB 1dB 31.75dB 2dB 0 -10 Return Loss (dB.) -20 -30 -40 -50 -60 -70 0 1 4dB 2 3 4 5 6 Frequency (GHz.) 7 8 9 0 1 2 3 4 5 Frequency (GHz.) 6 7 8 9 Figure 19. Input Return Loss vs. Temperature 16dB State -40C 25C 85C Figure 20. Output Return Loss vs. Temperature 16dB State 0 -5 -10 Return Loss (dB.) -15 -20 -25 -30 -35 -40 -45 -50 -40C 25C 85C 0 -5 Return Loss (dB.) -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 Frequency (GHz.) 7 8 9 0 1 2 3 4 5 6 Frequency (GHz.) 7 8 9 Document No. 70-0245-04 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 15 PE43703 Product Specification Performance Plots (continued) Figure 21. Relative Phase vs. Frequency 0dB 0.25dB 8dB 0.5dB 16dB 1dB 31.75dB 2dB 120 Relative Phase Error (Deg.) 100 4dB Figure 22. Relative Phase vs. Temperature 31.75dB State 35.00 30.00 Phase (deg.) 25.00 20.00 15.00 10.00 5.00 0.00 -40 -20 0 20 40 60 80 900 MHz 1800 MHz 3000 MHz 80 60 40 20 0 0 1 2 3 4 5 6 7 8 Frequency (GHz.) Temperature (Deg. C.) Figure 23. Attenuation Error vs. Attenuation Setting @ 900 MHz 900 MHz @ T=+25 C 0.500 Figure 24. Attenuation Error vs. Attenuation Setting @ 1800 MHz 1800 MHz @ T= +25C 0.500 0.300 0.100 -0.100 -0.300 -0.500 900 MHz @ T= -40C 900 MHz @ T= +85C 1800 MHz @ T= -40C 1800 MHz @ T= +85C 0.300 Attenuation Error (dB.) 0.100 -0.100 -0.300 - 0.500 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB.) Attenuation Error (dB.) 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB.) Figure 25. Attenuation Error vs. Attenuation Setting @ 3000 MHz 3000 MHz @ T= +25C 0.500 Figure 26. Input IP3 vs. Frequency 0dB 4dB 70 65 3000 MHz @ T= -40C 3000 MHz @ T= +85C 0.25dB 8dB 0.5dB 16dB 1dB 31.75dB 2dB 0.300 Attenuation Error (dB.) Input IP3 (dBm.) 60 55 50 45 40 35 0.100 -0.100 -0.300 -0.500 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB.) 30 0 1000 2000 3000 4000 5000 6000 7000 Frequency (MHz.) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 15 Document No. 70-0245-04 │ U ltraCMOS™ RFIC Solutions PE43703 Product Specification Figure 27. Pin Configuration (Top View) C0.25 C0.5 C16 C1 C2 C4 C8 SI Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. 32 31 30 29 28 27 26 25 24 23 22 NC VDD P/S A0 GND GND RF1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK LE A1 A2 VssEXT GND RF2 GND Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Exposed Solder pad 21 20 19 18 17 Optional External Vss Control (VssEXT) For proper operation, the VssEXT control must be grounded or at the Vss voltage specified in the Operating Ranges table. When the VssEXT control pin on the package is grounded the switch FET’s are biased with an internal low spur negative voltage generator. For applications that require the lowest possible spur performance, VssEXT can be applied to bypass the internal negative voltage generator to eliminate the spurs. GND GND GND GND GND GND GND Table 4. Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 - 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Paddle Pin Name N/C VDD P/S A0 GND GND RF1 GND RF2 GND VssEXT A2 A1 LE CLK SI C16 C8 C4 C2 C1 C0.5 C0.25 GND No Connect Description GND Switching Frequency The PE43703 has a maximum 25 kHz switching rate when VssEXT is grounded. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Power supply pin Serial/Parallel mode select Address Bit A0 (LSB) Ground Ground RF1 port Ground RF2 port Ground External Vss Control Address Bit A2 Address Bit A1 Latch Enable input Serial interface clock input Serial Interface input Attenuation control bit, 16 dB Attenuation control bit, 8 dB Attenuation control bit, 4 dB Attenuation control bit, 2 dB Attenuation control bit, 1 dB Attenuation control bit, 0.5 dB Attenuation control bit, 0.25 dB Ground for proper operation Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE43703 in the 5x5 QFN package is MSL1. Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Document No. 70-0245-04 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 15 PE43703 Product Specification Table 5. Operating Ranges Parameter VDD Power Supply Voltage VDD Power Supply Voltage VssEXT Negative Power Supply Voltage1 IDD Power Supply Current Digital Input High PIN Input power (50Ω): 1 Hz ≤ 20 MHz 20 MHz ≤ 6 GHz TOP Operating temperature range Digital Input Low Digital Input Leakage -40 0 25 2.6 -3.0 Min 3.0 Typ 3.3 5.0 -2.7 70 5.5 -2.4 350 5.5 See fig. 28 +23 85 1 15 Max Units V V V Table 6. Absolute Maximum Ratings Symbol VDD VssEXT VI µA V dBm dBm °C V µA Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7) PIN Parameter/Conditions Power supply voltage Vss External Negative Power Supply Voltage (optional) Voltage on any Digital input Input power (50Ω) 1 Hz ≤ 20 MHz 20 MHz ≤ 6 GHz Storage temperature range ESD voltage (HBM)1 ESD voltage (Machine Model) -65 Min -0.3 -4.0 -0.3 Max 6.0 0.3 5.8 See fig. 28 +23 150 500 100 Units V V V dBm dBm °C V V TST VESD Note: 1. Applied only when external VSS power supply used. Pin 20 must be grounded when using internal Vss supply Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Figure 28. Maximum Power Handling Capability: Z0 = 50 Ω 30.0 25.0 20.0 Pin dBm 15.0 10.0 5.0 0 .0 1.0E+03 1.0E+04 1.0E+05 1.0E+06 Hz 1.0E+07 1.0E+08 1.0E+09 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 15 Document No. 70-0245-04 │ U ltraCMOS™ RFIC Solutions PE43703 Product Specification Table 7. Control Voltage State Low High Bias Condition 0 to +1.0 Vdc at 2 µA (typ) +2.6 to +5 Vdc at 10 µA (typ) Table 10. Serial Address Word Truth Table Address Word A7 (MSB) X X X A6 X X X X X X X X A5 X X X X X X X X A4 X X X X X X X X A3 X X X X X X X X A2 L L L L H H H H A1 L L H H L L H H A0 L H L H L H L H Address Setting 000 001 010 011 100 101 110 111 Table 8. Latch and Clock Specifications Latch Enable 0 ↑ Shift Clock ↑ X Function Shift Register Clocked Contents of shift register transferred to attenuator core X X X X X Table 9. Parallel Truth Table Parallel Control Setting D6 L L L L L L L H H Table 11. Serial Attenuation Word Truth Table Attenuation Setting RF1-RF2 Reference I.L. 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.75 dB Attenuation Word D7 X X X X X X X X X D5 L L L L L L H L H D4 L L L L L H L L H D3 L L L L H L L L H D2 L L L H L L L L H D1 L L H L L L L L H D0 L H L L L L L L H D6 L L L L L L L H H D5 L L L L L L H L H D4 L L L L L H L L H D3 L L L L H L L L H D2 L L L H L L L L H D1 L L H L L L L L H D0 (LSB) L H L L L L L L H Attenuation Setting RF1-RF2 Reference I.L. 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.75 dB Table 12. Serial-Addressable Register Map MSB (last in) Q15 A7 Q14 A6 Q13 A5 Q12 A4 Q11 A3 Q10 A2 Bits can either be set to logic high or logic low Q9 A1 Q8 A0 Q7 D7 Q6 D6 Q5 D5 Q4 D4 Q3 D3 Q2 D2 LSB (first in) Q1 D1 Q0 D0 Address Word Attenuation Word Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state at address 3: Address word: XXXXX011 Attenuation Word: Multiply by 4 and convert to binary → 4 * 18.25 dB → 73 → X1001001 Serial Input: XXXXX011X1001001 Document No. 70-0245-04 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 15 PE43703 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE43703. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of seven CMOScompatible control lines that select the desired attenuation state, as shown in Table 9. The parallel interface timing requirements are defined by Fig. 30 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 30) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface The serial-addressable interface is a 16-bit serialin, parallel-out shift register buffered by a transparent latch. The 16-bits make up two words comprised of 8-bits each. The first word is the Attenuation Word, which controls the state of the DSA. The second word is the Address Word, which is compared to the static (or programmed) logical states of the A0, A1 and A2 digital inputs. If there is an address match, the DSA changes state; otherwise its current state will remain unchanged. Fig. 29 illustrates a example timing diagram for programming a state. It is recommended that all parallel control inputs be grounded when the DSA is used in Serial Mode. The serial-addressable interface is controlled using three CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first, beginning with the attenuation word. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Address word and attenuation word truth tables are listed in Table 10 & Table 11, respectively. A programming example of the serial-addressable register is illustrated in Table 12. The serial-addressable timing diagram is illustrated in Fig. 29. Power-up Control Settings The PE43703 will always initialize to the maximum attenuation setting (31.75 dB) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In direct-parallel mode, the DSA can be preset to any state within the 31.75 dB range by pre-setting the parallel control pins prior to powerup. In this mode, there is a 400-µs delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (31.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 15 Document No. 70-0245-04 │ U ltraCMOS™ RFIC Solutions PE43703 Product Specification Figure 29. Serial-Addressable Timing Diagram Bits can either be set to logic high or logic low DI[6:0] TDISU TDIH ADD[2:0] P/S VALID TASU TAH TPSSU TPSH SI TSISU TSIH D[0] D[1] D[2] D[3] D[4] D[5] D[6] A[0] A[1] A[2] CLK TCLKL TCLKH TLESU LE TLEPW TPD VALID DO[6:0] Figure 30. Latched-Parallel/Direct-Parallel Timing Diagram P/S TPSSU TPSH VALID TDISU TDIH DI[6:0] LE TLEPW DO[6:0] TDIPD VALID TPD Table 13. Serial Interface AC Characteristics VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol FCLK TCLKH TCLKL TLESU TLEPW TSISU TSIH TDISU TDIH TASU TAH TPSSU TPSH TPD Note: Table 14. Parallel and Direct Interface AC Characteristics VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol TLEPW TDISU TDIH Parameter Serial clock frequency Serial clock HIGH time Serial clock LOW time Last serial clock rising edge setup time to Latch Enable rising edge Latch Enable min. pulse width Serial data setup time Serial data hold time Parallel data setup time Parallel data hold time Address setup time Address hold time Parallel/Serial setup time Parallel/Serial hold time Digital register delay (internal) Min 30 30 10 30 10 10 100 100 100 100 100 100 - Max 10 10 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Latch Enable minimum pulse width Parallel data setup time Parallel data hold time Parallel/Serial setup time Parallel/Serial hold time Digital register delay (internal) Digital register delay (internal, direct mode only) Min 30 100 100 100 100 - Max 10 5 Unit ns ns ns ns ns ns ns TPSSU TPSIH TPD TDIPD fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 15 Document No. 70-0245-04 │ www.psemi.com PE43703 Product Specification Evaluation Kit The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE43703 Digital Step Attenuator. Direct-Parallel Programming Procedure For automated direct-parallel programming, connect the test harness provided with the EVK from the parallel port of the PC to the J1 & Serial header pin and set the D0-D6 SP3T switches to the ‘MIDDLE’ toggle position. Position the Parallel/ Serial (P/S) select switch to the Parallel (or left) position. The evaluation software is written to operate the DSA in either Parallel or SerialAddressable Mode. Ensure that the software is set to program in Direct-Parallel mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. For manual direct-parallel programming, disconnect the test harness provided with the EVK from the J1 and Serial header pins. Position the Parallel/Serial (P/S) select switch to the Parallel (or left) position. The LE pin on the Serial header must be tied to VDD. Switches D0-D6 are SP3T switches which enable the user to manually program the parallel bits. When any input D0-D6 is toggled ‘UP’, logic high is presented to the parallel input. When toggled ‘DOWN’, logic low is presented to the parallel input. Setting D0-D6 to the ‘MIDDLE’ toggle position presents an OPEN, which forces an on-chip logic low. Table 9 depicts the parallel programming truth table and Fig. 30 illustrates the parallel programming timing diagram. Latched-Parallel Programming Procedure For automated latched-parallel programming, the procedure is identical to the direct-parallel method. The user only must ensure that Latched-Parallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now the LE pin on the Serial header must be logic low as the parallel bits are applied. The user must then pulse LE from 0V to VDD and back to 0V to latch the programming word into the DSA. LE must be logic low prior to programming the next word. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 15 Figure 31. Evaluation Board Layout Peregrine Specification 101-0312 Note: Reference Fig. 32 for Evaluation Board Schematic Serial-Addressable Programming Procedure Position the Parallel/Serial (P/S) select switch to the Serial (or right) position. Prior to programming, the user must define an address setting using the ADD header pin. Jump the middle pins on the ADD header A0-A2 (or lower) row of pins to set logic high, or jump the middle pins to the upper row of pins to set logic low. If the ADD pins are left open, then 000 become the default address. The evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Serial-Addressable mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. Document No. 70-0245-04 │ U ltraCMOS™ RFIC Solutions PE43703 Product Specification Figure 32. Evaluation Board Schematic Peregrine Specification 102-0381 Note: Capacitors C1-C8, C13, & C14 may be omitted. Figure 33. Package Drawing QFN 5x5 mm MAX 0.900 0.850 0.800 A NOM MIN Document No. 70-0245-04 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 15 PE43703 Product Specification Figure 34. Tape and Reel Drawing Tape Feed Direction Pin 1 Top of Device Device Orientation in Tape Figure 35. Marking Specifications 43703 YYWW ZZZZZ Table 15. Ordering Information Order Code Part Marking PE43703MLI PE43703MLI-Z EK43703-01 43703 43703 43703 YYWW = Date Code ZZZZZ = Last five digits of Lot Number Description PE43703 G - 32QFN 5x5mm-75A PE43703 G – 32QFN 5x5mm-3000C PE43703 G – 32QFN 5x5mm-EK Package Green 32-lead 5x5mm QFN Green 32-lead 5x5mm QFN Evaluation Kit Document No. 70-0245-04 Shipping Method Bulk or tape cut from reel 3000 units / T&R 1 / Box │ U ltraCMOS™ RFIC Solutions ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 15 PE43703 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 High-Reliability and Defense Products Americas San Diego, CA, USA Phone: 858-731-9475 Fax: 848-731-9499 Europe/Asia-Pacific Aix-En-Provence Cedex 3, France Phone: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 15 of 15 Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0245-04 │ www.psemi.com