Product Specification
PE43704
UltraCMOS® RF Digital Step
Attenuator, 7-bit, 31.75 dB
with Optional VssEXT Bypass Mode
9 kHz - 8 GHz
Product Description
The PE43704 is a HaRP™ technology-enhanced, high
linearity, 7-bit 50Ω RF digital step attenuator (DSA). It
offers maximum power handling of 28 dBm up to 8 GHz
and covers a 31.75 dB attenuation range in 0.25 dB,
0.5 dB, or 1.0 dB steps. The PE43704 is a pin-compatible
version of PE43703. It provides multiple CMOS control
interfaces and an optional VssEXT bypass mode to improve
spurious performance. It maintains high attenuation
accuracy over frequency and temperature and exhibits
very low insertion loss and low power consumption. No
blocking capacitors are required if DC voltage is not
present on the RF ports.
The PE43704 is manufactured on pSemi’s UltraCMOS®
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the
performance of GaAs with the economy and integration of
conventional CMOS.
Features
HaRP™ technology enhanced
Safe attenuation state transitions
Attenuation options: covers a 31.75 dB
Figure 1. Package Type
32-lead 5x5 QFN
range in 0.25 dB, 0.5 dB, or 1.0 dB steps
0.25 dB monotonicity for ≤ 6 GHz
0.50 dB monotonicity for ≤ 7 GHz
1.00 dB monotonicity for ≤ 8 GHz
High power handling @ 8 GHz in 50Ω
28 dBm CW
31 dBm instantaneous power
High linearity
IIP3 of 61 dBm
1.8V/3.3V control logic
Programming modes
Direct parallel
Latched parallel
Serial
Serial Addressable
High-attenuation state @ power-up (PUP)
ESD performance
1.5kV HBM on all pins
Figure 2. Functional Diagram
DOC-02161
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Page 1 of 21
PE43704
Product Specification
Table 1. Electrical Specifications: 0.25 dB steps @ +25°C, VDD = 2.3V to 5.5V, VssEXT = 0V or
VDD = 3.4V to 5.5V, VssEXT = -3.4V (ZS = ZL = 50Ω ) unless otherwise noted
Parameter
Condition
Frequency
Operating frequency
Min
Typ
9 kHz
Attenuation range
0.25 dB Step
Unit
6000 MHz
As shown
0 – 31.75
9 kHz – 2 GHz
2 GHz – 4 GHz
4 GHz – 6 GHz
Insertion loss
Max
dB
1.6
2.0
2.8
1.3
1.7
2.4
+ (0.15 + 4.5% of
Attenuation Setting)
- (0.1 + 2% of
Attenuation Setting)
9 KHz ≤ 4 GHz
0 dB – 15.75 dB Attenuation settings
+ (0.15 + 6% of
Attenuation Setting)
- (0.15+1% of
Attenuation Setting)
4 GHz – 6 GHz
Attenuation error
+ (0.15 + 4.5% of
Attenuation Setting)
- (0.1 + 2.5% of
Attenuation Setting)
9 KHz ≤ 4 GHz
16 dB – 31.75 dB Attenuation settings
+ (0.25 + 6.5% of
Attenuation Setting)
- (0.2+1% of
Attenuation Setting)
4 GHz – 6 GHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Return loss
Input port
9 kHz – 4 GHz
4 GHz – 6 GHz
20
15
dB
dB
Return loss
Output port
9 kHz – 4 GHz
4 GHz – 6 GHz
17
13
dB
dB
0 dB – 31.75 dB Attenuation settings
9 kHz – 6 GHz
58
deg
34
dBm
61
dBm
VssEXT = 0V
–140
dBm
10% / 90% RF
600
ns
Relative phase
Input 1dB compression point
IIP3
Typical spurious value
RF Trise/Tfall
50 MHz – 6 GHz
1
Two tones at +18 dBm, 20 MHz spacing
2
Settling time
RF settled to within 0.05 dB of final value
Switching time
50% CTRL to 90% or 10% RF
32
50 MHz – 6 GHz
2
µs
1.1
µs
Notes: 1. The input 1dB compression point is a linearity figure of merit. Refer to Table 5 for the RF input power PIN (50Ω)
2. To prevent negative voltage generator spurs, supply –3.4 volts to VssEXT
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Page 2 of 21
Document No. DOC-16514-9 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Table 2. Electrical Specifications: 0.5 dB steps @ +25°C, VDD = 2.3V to 5.5V, VssEXT = 0V or
VDD = 3.4V to 5.5V, VssEXT = -3.4V (ZS = ZL = 50Ω ) unless otherwise noted
Parameter
Condition
Frequency
Operating frequency
Min
Typ
9 kHz
Attenuation range
0.5 dB Step
Unit
7000 MHz
As shown
0 – 31.5
9 kHz – 2 GHz
2 GHz – 4 GHz
4 GHz – 6 GHz
6 GHz – 7 GHz
Insertion loss
Max
1.3
1.7
2.4
2.5
dB
1.6
2.0
2.8
2.9
+ (0.15 + 4.5% of
Attenuation Setting)
- (0.1 + 2% of
Attenuation Setting)
9 KHz ≤ 4 GHz
0 dB – 15.5 dB Attenuation settings
+ (0.25 + 5.5% of
Attenuation Setting)
- (0.15+1% of
Attenuation Setting)
4 GHz – 7 GHz
Attenuation error
+ (0.15 + 4.5% of
Attenuation Setting)
- (0.1 + 2.5% of
Attenuation Setting)
9 KHz ≤ 4 GHz
16 dB – 31.5 dB Attenuation settings
+ (0.25 + 6.5% of
Attenuation Setting)
- (0.25 + 2.5% of
Attenuation Setting)
4 GHz – 7 GHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Return loss
Input port
9 kHz – 4 GHz
4 GHz – 7 GHz
20
16
dB
dB
Return loss
Output port
9 kHz – 4 GHz
4 GHz – 7 GHz
17
14
dB
dB
Relative phase
0 dB – 31.5 dB Attenuation settings
9 kHz – 7 GHz
65
deg
34
dBm
61
dBm
VssEXT = 0V
–140
dBm
RF Trise/Tfall
10% / 90% RF
600
ns
Settling time
RF settled to within 0.05 dB of final value
2
µs
Switching time
50% CTRL to 90% or 10% RF
1.1
µs
Input 1dB compression point1
IIP3
Typical spurious value
50 MHz – 7 GHz
Two tones at +18 dBm, 20 MHz spacing
2
32
50 MHz – 7 GHz
Notes: 1. The input 1dB compression point is a linearity figure of merit. Refer to Table 5 for the RF input power PIN (50Ω)
2. To prevent negative voltage generator spurs, supply –3.4 volts to VssEXT
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PE43704
Product Specification
Table 3. Electrical Specifications: 1 dB steps @ +25°C, VDD = 2.3V to 5.5V, VssEXT = 0V or
VDD = 3.4V to 5.5V, VssEXT = -3.4V (ZS = ZL = 50Ω ) unless otherwise noted
Parameter
Condition
Frequency
Operating frequency
Min
Typ
9 kHz
Attenuation range
1 dB Step
As shown
1.6
2.0
2.8
3.2
+ (0.15 + 4.5% of
Attenuation Setting)
- (0.1 + 2% of
Attenuation Setting)
+ (0.25 + 6% of
Attenuation Setting)
- (0.25 + 2% of
Attenuation Setting)
4 GHz ≤ 7 GHz
+ (0.25 + 7% of
Attenuation Setting)
- (0.25 + 2% of
Attenuation Setting)
7 GHz – 8 GHz
Attenuation error
+ (0.15 + 4.5% of
Attenuation Setting)
- (0.1 + 2.5% of
Attenuation Setting)
9 kHz ≤ 4 GHz
16dB – 31 dB Attenuation settings
8000 MHz
dB
1.3
1.7
2.4
2.9
9 kHz ≤ 4 GHz
0 dB – 15 dB Attenuation settings
Unit
0 - 31
9 kHz – 2 GHz
2 GHz – 4 GHz
4 GHz – 6 GHz
6 GHz – 8 GHz
Insertion loss
Max
+ (0.25 + 6.5% of
Attenuation Setting)
- (0.25 + 3% of
Attenuation Setting)
4 GHz ≤ 7 GHz
+ (0.25 + 7% of
Attenuation Setting)
- (0.25 + 4% of
Attenuation Setting)
7 GHz – 8 GHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Return loss
Input port
9 kHz – 4 GHz
4 GHz – 8 GHz
20
14.5
dB
dB
Return loss
Output port
9 kHz – 4 GHz
4 GHz – 8 GHz
17
12.5
dB
dB
0 dB – 31 dB Attenuation settings
9 kHz – 8 GHz
80
deg
34
dBm
61
dBm
Relative phase
Input 1dB compression point
IIP3
Typical spurious value
50 MHz – 8 GHz
1
Two tones at +18 dBm, 20 MHz spacing
32
50 MHz – 8 GHz
VssEXT = 0V
–140
dBm
RF Trise/Tfall
10% / 90% RF
600
ns
Settling time
RF settled to within 0.05 dB of final value
2
µs
1.1
µs
2
Switching
timeinput 1dB compression
50%
CTRL
to 90%figure
or 10%
RF Refer to Table 5 for the RF input power P (50Ω)
Notes:
1. The
point
is a linearity
of merit.
IN
2. To prevent negative voltage generator spurs, supply –3.4 volts to VssEXT
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Document No. DOC-16514-9 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Figure 3. Pin Configuration (Top View)
Table 5. Operating Ranges
Symbol
Min
Supply voltage (normal
mode, VssEXT = 0V)1
VDD
2.3
Supply voltage (bypass
mode, VssEXT = -3.4V,
VDD≥ 3.4V for full spec.
compliance)2
VDD
2.7
Negative supply voltage
(bypass mode)2
VssEXT
-3.6
Supply current (normal
mode, VssEXT = 0V)1
IDD
Supply current (bypass
mode, VssEXT = -3.4V)2
IDD
Negative supply current
(bypass mode, VssEXT =
-3.4V)2
ISS
-40
Digital input high
VIH
1.17
3.6
V
Digital input low
VIL
-0.3
0.6
V
ICTRL
15
μA
PMAX,CW
see
Fig. 4
+28
dBm
dBm
see
Fig. 4
+31
dBm
dBm
+85
°C
Parameter
Table 4. Pin Descriptions
Pin #
Pin Name
1
N/C
Description
No connect
Digital input current
RF input power, CW
9 kHz < 50 MHz
50 MHz ≤ 8 GHz
Max
Unit
5.5
V
5.5
V
-2.4
V
130
200
μA
50
80
μA
3.4
-16
3
2
VDD
Supply voltage
3
P/S
Serial/parallel mode select
4
A0
Address bit A0 connection
5, 6,
8-17, 19
GND
Ground
RF input power, pulsed4
9 kHz < 50 MHz PMAX,PULSED
50 MHz ≤ 8 GHz
7
RF11
RF1 port (RF input)
Operating temperature
range
18
RF21
RF2 port (RF output)
20
VssEXT2
21
A2
Address bit A2 connection
22
A1
Address bit A1 connection
23
LE
Serial interface latch enable input
24
CLK
25
SI
26
C16 (D6)
Parallel control bit, 16 dB
27
C8 (D5)3
Parallel control bit, 8 dB
28
C4 (D4)3
Parallel control bit, 4 dB
29
C2 (D3)
Parallel control bit, 2 dB
30
C1 (D2)
31
C0.5 (D1)
32
C0.25 (D0)
Pad
GND
External Vss negative voltage control
Typ
Notes:
TOP
-40
25
μA
1. Normal mode: connect VssEXT (pin 20) to GND (VssEXT = 0V) to
enable internal negative voltage generator
2. Bypass mode: use VssEXT (pin 20) to bypass and disable internal
negative voltage generator
3. 100% duty cycle, all bands, 50Ω
4. Pulsed, 5% duty cycle of 4620 µs period, 50Ω
Serial interface clock input
Serial interface data input
3
3
Parallel control bit, 1 dB
3
3
3
Parallel control bit, 0.5 dB
Parallel control bit, 0.25 dB
Exposed pad: ground for proper operation
Notes: 1. RF pins 7 and 18 must be at 0V DC. The RF pins do not require DC
blocking capacitors for proper operation if the 0V DC
requirement is met
2. Use VssEXT (pin 20) to bypass and disable internal
negative voltage generator. Connect VssEXT (pin 20) to GND (VssEXT = 0V)
to enable internal negative voltage generator
3. Ground C0.25, C0.5, C1 C2, C4, C8, C16 if not in use
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Page 5 of 21
PE43704
Product Specification
Table 6. Absolute Maximum Ratings
Parameter/Condition
Supply voltage
Digital input voltage
RF input power, max
9 kHz < 50 MHz
50 MHz ≤ 8 GHz
Switching Frequency
Symbol
Min
Max
Unit
VDD
-0.3
5.5
V
VCTRL
-0.3
3.6
V
see
Fig. 4
+34
dBm
dBm
+150
°C
PMAX,ABS
Storage temperature range
TST
ESD voltage HBM , all pins
VESD,HBM
1500
V
ESD voltage MM2, all pins
VESD,MM
200
V
ESD voltage CDM3, all pins
VESD,CDM
250
V
1
Notes:
-65
1. Human Body Model (MIL-STD 883 Method 3015)
2. Machine Model (JEDEC JESD22-A115)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
The PE43704 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 20 = GND). The rate at which the
PE43704 can be switched is only limited to the
switching time (Tables 1-3) if an external negative
supply is provided (pin 20 = VssEXT).
Switching frequency is defined to be the speed at
which the DSA can be toggled across attenuation
states. Switching time is the time duration
between the point the control signal reaches 50%
of the final value and the point the output signal
Optional External Vss Control (VssEXT)
For proper operation, the VssEXT control pin must
be grounded or tied to the Vss voltage specified in
Table 5. When the VssEXT control pin is grounded,
FETs in the switch are biased with an internal
voltage generator. For applications that require
the lowest possible spur performance, VssEXT can
be applied externally to bypass the internal
Table 7. Latch and Clock Specifications
Latch Enable
Shift Clock
Function
0
↑
Shift register clocked
↑
X
Contents of shift register
transferred to attenuator core
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
Moisture Sensitivity Level
The moisture sensitivity level rating for the
PE43704 in the 5x5 QFN package is MSL1.
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Safe Attenuation State Transitions
The PE43704 features a novel architecture to
provide safe transition behavior when changing
attenuation states. When RF input power is
applied, positive output power spikes are
prevented during attenuation state changes by
optimized internal timing control.
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UltraCMOS® RFIC Solutions
PE43704
Product Specification
Figure 4. Power De-rating Curve (50Ω , -40°C to 85°C Ambient)
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PE43704
Product Specification
Table 8. Parallel Truth Table
Table 9. Serial Attenuation Word Truth Table
Parallel Control Setting
Attenuation Word
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
Attenuation
Setting
RF1-RF2
D6
D5
D4
D3
D2
D1
D0
Attenuation
Setting
RF1-RF2
L
L
L
L
L
L
L
Reference I.L.
L
L
L
L
L
L
L
L
Reference I.L.
L
L
L
L
L
L
H
0.25 dB
L
L
L
L
L
L
L
H
0.25 dB
L
L
L
L
L
H
L
0.5 dB
L
L
L
L
L
L
H
L
0.5 dB
L
L
L
L
H
L
L
1 dB
L
L
L
L
L
H
L
L
1 dB
L
L
L
H
L
L
L
2 dB
L
L
L
L
H
L
L
L
2 dB
L
L
H
L
L
L
L
4 dB
L
L
L
H
L
L
L
L
4 dB
L
H
L
L
L
L
L
8 dB
L
L
H
L
L
L
L
L
8 dB
H
L
L
L
L
L
L
16 dB
L
H
L
L
L
L
L
L
16 dB
H
H
H
H
H
H
H
31.75 dB
L
H
H
H
H
H
H
H
31.75 dB
Table 10. Serial Address Word Truth Table
Address Word
A0
Address
Setting
L
L
000
L
H
001
A7
(MSB)
A6
A5
A4
A3
A2
A1
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
H
L
010
X
X
X
X
X
L
H
H
011
X
X
X
X
X
H
L
L
100
X
X
X
X
X
H
L
H
101
X
X
X
X
X
H
H
L
110
X
X
X
X
X
H
H
H
111
Table 11. Serial-Addressable Register Map
Bits can either be set to logic high or logic low
MSB (last in)
LSB (first in)
D7 must be set to logic low
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Address Word
Attenuation Word
Attenuation word is derived directly from the attenuation value. For example, to program the 18.25 dB state
at address 3:
Address word: XXXXX011
Attenuation sord: Multiply by 4 and convert to binary → 4 * 18.25 dB → 73 → 01001001
Serial input: XXXXX01101001001
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Document No. DOC-16514-9 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Programming Options
Parallel/Serial Selection
Either a parallel or serial-addressable interface can be
used to control the PE43704. The P/S bit provides this
selection, with P/S = LOW selecting the parallel
interface and P/S = HIGH selecting the serialaddressable interface.
Parallel Mode Interface
The parallel interface consists of seven CMOScompatible control lines that select the desired
attenuation state, as shown in Table 8.
The parallel interface timing requirements are defined
by Figure 6 (Parallel Interface Timing Diagram),
Table 13 (Parallel and Direct Interface AC
Characteristics) and switching time (Tables 1-3).
For latched-parallel programming the latch enable (LE)
should be held LOW while changing attenuation state
control values, then pulse LE HIGH to LOW (per
Figure 6) to latch new attenuation state into device.
For direct parallel programming, the LE line should be
pulled HIGH. Changing attenuation state control values
will change device state to new attenuation. Direct
mode is ideal for manual control of the device (using
hardwire, switches, or jumpers).
In parallel mode, serial-in (SI) and clock (CLK) pins are
“don’t care” and may be tied to logic LOW or logic
HIGH.
Serial Interface
The serial-addressable interface is a 16-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The 16-bits make up two words comprised of 8bits each. The first word is the Attenuation Word, which
controls the state of the DSA. The second word is the
Address Word, which is compared to the static (or
programmed) logical states of the A0, A1 and A2 digital
inputs. If there is an address match, the DSA changes
state; otherwise its current state will remain unchanged.
Figure 5 illustrates an example timing diagram for
programming a state. It is required that all parallel
control inputs be grounded when the DSA is used in
serial-addressable mode.
The serial-interface is controlled using three CMOScompatible signals: serial-in (SI), clock (CLK), and latch
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enable (LE). The SI and CLK inputs allow data to
be serially entered into the shift register. Serial data
is clocked in LSB first, beginning with the
attenuation word.
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data into the DSA. Attenuation word and
address word truth tables are listed in Table 9 and
Table 10. A programming example of the serial
register is illustrated in Table 11. The serial timing
diagram is illustrated in Figure 5.
Power-up Control Settings
The PE43704 will always initialize to the maximum
attenuation setting (31.75 dB) on power-up for both
the serial-addressable and latched-parallel modes
of operation and will remain in this setting until the
user latches in the next programming word. In direct
-parallel mode, the DSA can be preset to any state
within the 31.75 dB range by pre-setting the parallel
control pins prior to power-up. In this mode, there is
a 400-µs delay between the time the DSA is
powered-up to the time the desired state is set.
During this power-up delay, the device attenuates
to the maximum attenuation setting (31.75 dB)
before defaulting to the user defined state. If the
control pins are left floating in this mode during
power-up, the device will default to the minimum
attenuation setting (insertion loss state).
Dynamic operation between serial and parallel
programming modes is possible.
If the DSA powers up in serial mode (P/S = HIGH),
all the parallel control inputs DI[6:0] must be set to
logic low. Prior to toggling to parallel mode, the
DSA must be programmed serially to ensure D[7] is
set to logic low.
If the DSA powers up in either latched or directparallel mode, all parallel pins DI[6:0] must be set to
logic low prior to toggling to serial-addressable
mode (P/S = HIGH), and held low until the DSA has
been programmed serially to ensure bit D[7] is set
to logic low.
The sequencing is only required once on power-up.
Once completed, the DSA may be toggled between
serial and parallel programming modes at will.
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PE43704
Product Specification
Figure 5. Serial Addressable Timing Diagram
Figure 6. Latched-Parallel/Direct-Parallel Timing Diagram
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UltraCMOS® RFIC Solutions
PE43704
Product Specification
Table 12. Serial Interface AC Characteristics
VDD = 3.4V or 5.0V, -40°C < TA < 85°C, unless otherwise specified
Parameter
Symbol
Min
Max
Unit
Serial clock frequency
FCLK
-
10
MHz
Serial clock HIGH time
TCLKH
30
-
ns
Serial clock LOW time
TCLKL
30
-
ns
Last serial clock rising edge setup
time to Latch Enable rising edge
TLESU
10
-
ns
Latch enable min. pulse width
TLEPW
30
-
ns
Serial data setup time
TSISU
10
-
ns
Serial data hold time
TSIH
10
-
ns
Parallel data setup time
TDISU
100
-
ns
Parallel data hold time
TDIH
100
-
ns
Address setup time
TASU
100
-
ns
Address hold time
TAH
100
-
ns
Parallel/serial setup time
TPSSU
100
-
ns
Parallel/serial hold time
TPSIH
100
-
ns
Table 13. Parallel and Direct Interface AC Characteristics
VDD = 3.4V or 5.0V, -40°C < TA < 85°C, unless otherwise
specified
Symbol
Parameter
Min
Max
Unit
TLEPW
Latch enable minimum pulse
width
30
-
ns
TDISU
Parallel data setup time
100
-
ns
TDIH
Parallel data hold time
100
-
ns
TPSSU
Parallel/serial setup time
100
-
ns
TPSIH
Parallel/serial hold time
100
-
ns
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Page 11 of 21
Document No. DOC-16514-9 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Typical Performance Data, 0.25 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 7. 0.25 dB Step Attenuation vs. Frequency*
* Monotonicity is held so long as step-attenuation does not cross below –0.25 dB
Figure 8. 0.25 dB Step, Actual vs. Frequency
Figure 9. 0.25 dB Major State Bit Error vs.
Attenuation Setting
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Figure 10. 0.25 dB Attenuation Error vs.
Frequency
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Page 12 of 21
PE43704
Product Specification
Typical Performance Data, 0.5 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 11. 0.5 dB Step Attenuation vs. Frequency*
* Monotonicity is held so long as step-attenuation does not cross below –0.5 dB
Figure 12. 0.5 dB Step, Actual vs. Frequency
Figure 13. 0.5 dB Major State Bit Error vs.
Attenuation Setting
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Page 13 of 21
Figure 14. 0.5 dB Attenuation Error vs.
Frequency
Document No. DOC-16514-9 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Typical Performance Data, 1 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 15. 1 dB Step Attenuation vs. Frequency*
* Monotonicity is held so long as step-attenuation does not cross below –1.0 dB
Figure 16. 1 dB Step, Actual vs. Frequency
Figure 17. 1 dB Major State Bit Error vs.
Attenuation Setting
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Page 14 of 21
PE43704
Product Specification
Typical Performance Data, 1 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 18. 1 dB Attenuation Error vs. Frequency
Figure 19. Insertion Loss vs. Temperature
Figure 20. Input Return Loss vs.
Attenuation Setting
Figure 21. Output Return Loss vs.
Attenuation Setting
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Page 15 of 21
Document No. DOC-16514-9 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Typical Performance Data, 1 dB Step @ 25°C and VDD = 3.4V unless otherwise specified
Figure 22. Input Return Loss vs. Temperature
for 16 dB Attenuation Setting
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Figure 23. Output Return Loss vs. Temperature
for 16 dB Attenuation Setting
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Page 16 of 21
PE43704
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 24. Relative Phase Error vs.
Attenuation Setting
Figure 25. Relative Phase Error for 31.75 dB
Attenuation Setting vs. Frequency
Figure 26. Attenuation Error @ 900 MHz vs.
Temperature
Figure 27. Attenuation Error @ 1800 MHz vs.
Temperature
Figure 28. Attenuation Error @ 3000 MHz vs.
Temperature
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Page 17 of 21
Figure 29. IIP3 vs. Attenuation Setting
Document No. DOC-16514-9 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Figure 31. Evaluation Board Layout
Evaluation Kit
The Digital Attenuator Evaluation Board (EVB) was
designed to ease customer evaluation of the
PE43704 digital step attenuator. PE43704 EVB
supports direct-parallel, latched-parallel, and serial
modes.
A0
Evaluation Kit Setup
Connect the EVB with the USB dongle board and
USB cable as shown in Figure 30.
Figure 30. Evaluation Kit
PRT-13505
Direct-Parallel Programming Procedure
Direct-parallel programming is suitable for manual
operation without software programming. For
manual direct-parallel programming, position the
parallel/serial (P/S) select switch to the parallel (or
left) position. The LE pin of J1 (pin 15) must be tied
to HIGH voltage. Switches D0–D6 are SP3T
switches that enable the user to manually program
the parallel bits. When D0–D6 are toggled to the
‘HIGH’ position, logic high is presented to the
parallel input. When toggled to the ‘LOW’ position,
logic low is presented to the parallel input. Setting
D0–D6 to the ‘AUTO’ position presents as OPEN,
which is set for software programming of latchedparallel and serial mode. Table 8 depicts the
parallel programming truth table.
Latched-Parallel Programming Procedure
For automated latched-parallel programming,
connect the USB dongle board and cable that is
provided with the evaluation kit (EVK) from the
USB port of the PC to the J1 header of the
PE43704 EVB, and set the D0–D6 SP3T switches
to the ‘AUTO’ position. Position the parallel/serial
(P/S) select switch to the parallel (or left) position.
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The evaluation software is written to operate the
DSA in parallel mode. Ensure that the software
GUI is set to latched-parallel mode. Use the
software GUI to enable the desired attenuation
state. The software GUI automatically programs
the DSA each time an attenuation state is
enabled.
Serial-Addressable Programming Procedure
For automated serial programming, connect the
USB dongle board and cable that is provided with
the evaluation kit (EVK) from the USB port of the
PC to the J1 header of the PE43704 EVB, and set
the D0–D6 SP3T switches to the ‘AUTO’ toggle
position. Position the parallel/serial (P/S) select
switch to the serial (or right) position. Prior to
programming, the user must define an address
setting using the HDR4 header pin. Jump the
middle row of pins on the HDR4 header (A0–A2)
to the lower row of pins to set logic low, or jump
the middle row of pins to the upper row of pins to
set logic high. If the HDR4 pins are left open, then
000 becomes the default address. The software
GUI is written to operate the DSA in serial mode.
Use the software GUI to enable each setting to
the desired attenuation state. The software GUI
automatically programs the DSA each time an
attenuation state is enabled.
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PE43704
Product Specification
Figure 32. Evaluation Board Schematic
DOC-16527
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Document No. DOC-16514-9 |
UltraCMOS® RFIC Solutions
PE43704
Product Specification
Figure 33. Package Drawing
32-lead 5x5 QFN
DOC-01872
Figure 34. Top Marking Specification
43704
YYWW
ZZZZZZZ
= Pin 1 designator
YY = Last two digits of assembly year
WW = Assembly work week
DOC-66072
Document No. DOC-16514-9 |
ZZZZZZZ = Assembly lot code (maximum seven characters)
www.psemi.com
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Page 20 of 21
PE43704
Product Specification
Figure 35. Tape and Reel Drawing
Tape Feed Direction
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±.02
2. Camber not to exceed 1 mm in 100 mm
3. Material: PS + C
4. Ao and Bo measured as indicated
5. Ko measured from a plane on the inside bottom of the pocket to the
top surface of the carrier
6. Pocket position relative to sprocket hole measured as true position
of pocket, not pocket hole
Ao = 5.25 mm
Bo = 5.25 mm
Ko = 1.1 mm
Table 14. Ordering Information
Order Code
Description
Package
Shipping Method
PE43704B-Z
PE43704 Digital step attenuator
32-lead 5x5 mm QFN
3000 units / T&R
EK43704-12
PE43704 Evaluation kit
Evaluation kit
1 / Box
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
©2012–2020 pSemi Corp. All rights reserved.
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Document No. DOC-16514-9 |
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