PE43712A-Z

PE43712 Document Category: Product Specification UltraCMOS® RF Digital Step Attenuator, 9 kHz–6 GHz Features Figure 1 • PE43712 Functional Diagram • Flexible attenuation steps of 0.25 dB, 0.5 dB and 1 dB up to 31.75 dB Switched Attenuator Array RF Input • Glitch-less attenuation state transitions RF Output • Monotonicity: 0.25 dB up to 4 GHz, 0.5 dB up to 5 GHz and 1 dB up to 6 GHz • Extended +105 °C operating temperature • Parallel and Serial programming interfaces with Serial Addressability • Packaging—32-lead 5 × 5 mm QFN Applications • 3G/4G wireless infrastructure • Land mobile radio (LMR) system • Point-to-point communication system Parallel Control ×7 Serial In Control Logic Interface CLK LE A0 A1 A2 P/S Product Description The PE43712 is a 50Ω, HaRP™ technology-enhanced,7-bit RF digital step attenuator (DSA) that supports a broad frequency range from 9 kHz to 6 GHz. It features glitch-less attenuation state transitions and supports 1.8V control voltage and an extended operating temperature range to +105 °C, making this device ideal for many broadband wireless applications. The PE43712 is a pin-compatible upgraded version of the PE43601 and PE43701. An integrated digital control interface supports both Serial Addressable and Parallel programming of the attenuation, including the capability to program an initial attenuation state at power-up. The PE43712 covers a 31.75 dB attenuation range in 0.25 dB, 0.5 dB and 1 dB steps. It is capable of maintaining 0.25 dB monotonicity through 4GHz, 0.5 dB monotonicity through 5 GHz and 1 dB monotonicity through 6 GHz. In addition, no external blocking capacitors are required if 0 VDC is present on the RF ports. The PE43712 is manufactured on pSemi’s UltraCMOS® process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate. ©2017–2022, pSemi Corporation. All rights reserved. • Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator pSemi’s HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 • Absolute Maximum Ratings for PE43712 Parameter/Condition Min Max Unit Supply voltage, VDD –0.3 5.5 V Digital input voltage –0.3 3.6 V Figure 5 +31 dBm dBm +150 °C ESD voltage HBM, all pins(1) 3000 V ESD voltage CDM, all pins(2) 1000 V RF input power, 50Ω 9 kHz–48 MHz >48 MHz–6 GHz Storage temperature range –65 Notes: 1) Human body model (MIL–STD 883 Method 3015). 2) Charged device model (JEDEC JESD22–C101). Page 2 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Recommended Operating Conditions Table 2 lists the recommending operating condition for the PE43712. Devices should not be operated outside the recommended operating conditions listed below. Table 2 • Recommended Operating Condition for PE43712 Parameter Min Supply voltage, VDD Typ 2.3 Supply current, IDD 150 Max Unit 5.5 V 200 µA Digital input high 1.17 3.6 V Digital input low –0.3 0.6 V 17.5 µA RF input power, CW(1) 9 kHz–48 MHz >48 MHz–6 GHz Figure 5 +23 dBm dBm RF input power, pulsed(2) 9 kHz–48 MHz >48 MHz–6 GHz Figure 5 +28 dBm dBm +105 °C Digital input current Operating temperature range –40 +25 Notes: 1) 100% duty cycle, all bands, 50Ω. 2) Pulsed, 5% duty cycle of 4620 µs period, 50Ω. DOC-85209-5 – (5/2022) Page 3 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Electrical Specifications Table 3 provides the PE43712 key electrical specifications at 25 °C, VDD = 3.3V, RF1 = RFIN, RF2 = RFOUT (ZS = ZL = 50Ω), unless otherwise specified. Table 3 • PE43712 Electrical Specifications Parameter Condition Frequency Typ 9 kHz Operating frequency Attenuation range Min 0.25 dB step 0.5 dB step 1 dB step Unit 6 GHz As shown dB dB dB 0–31.75 0–31.50 0–31.00 9 kHz–1.0 GHz 1.0–2.2 GHz 2.2–4.0 GHz 4.0–6.0 GHz Insertion loss Max 1.3 1.6 1.95 2.45 1.5 1.85 2.4 2.8 dB dB dB dB 9 kHz–2.2 GHz ± (0.20 + 1.5% of attenuation setting) dB 9 kHz–2.2 GHz ± (0.20 + 2.0% of attenuation setting) dB >2.2–3.0 GHz ± (0.15 + 3.0% of attenuation setting) dB >3.0–4.0 GHz ± (0.25 + 3.5% of attenuation setting) dB 9 kHz–2.2 GHz ± (0.20 + 1.5% of attenuation setting) dB 9 kHz–2.2 GHz ± (0.20 + 2.0% of attenuation setting) dB >2.2–3.0 GHz ± (0.15 + 3.0% of attenuation setting) dB >3.0–5.0 GHz ± (0.25 + 5.0% of attenuation setting) dB 0.25 dB step 0–8 dB 8.25–31.75 dB 0–31.75 dB 0–31.75 dB Attenuation error 0.50 dB step 0–8 dB 8.5–31.5 dB 0–31.5 dB 0–31.5 dB Page 4 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Table 3 • PE43712 Electrical Specifications (Cont.) Parameter Condition Frequency Min Typ Max Unit 9 kHz–2.2 GHz ± (0.20 + 1.5% of attenuation setting) dB 9 kHz–2.2 GHz ± (0.20 + 2.0% of attenuation setting) dB >2.2–3.0 GHz ± (0.15 + 3.0% of attenuation setting) dB >3.0–5.0 GHz ± (0.25 + 5.0% of attenuation setting) dB >5.0–6.0 GHz ± (0.25 + 5.0% of attenuation setting) dB 1 dB step 0–8 dB 9–31 dB Attenuation error 0–31 dB 0–31 dB 0–31 dB Return loss Input port or output port 9 kHz–4 GHz 4–6 GHz 13 15 dB dB Relative phase All states 9 kHz–4 GHz 4–6 GHz 27 42 deg deg 48 MHz–6 GHz 31 dBm 4 GHz 6 GHz 57 56 dBm dBm Input 0.1dB compression point(*) Input IP3 Two tones at +18 dBm, 20 MHz spacing RF Trise/Tfall 10%/90% RF 200 ns Settling time RF settled to within 0.05 dB of final value 1.6 µs Switching time 50% CTRL to 90% or 10% RF 275 ns 0.3 dB Attenuation transient (envelope) 2 GHz Note: * The input 0.1dB compression point is a linearity figure of merit. Refer to Table 2 for the operating RF input power (50Ω). DOC-85209-5 – (5/2022) Page 5 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Switching Frequency Table 5 • Serial Address Word Truth Table The PE43712 has a maximum 25 kHz switching rate. Switching frequency is defined to be the speed at which the DSA can be toggled across attenuation states. Switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. Address Word Address Setting A7 A6 A5 A4 A3 A2 A1 A0 (MSB) X X X X X L L L 000 X X X X X L L H 001 Spurious Performance X X X X X L H L 010 The typical spurious performance of the PE43712 is -165 dBm/Hz. X X X X X L H H 011 X X X X X H L L 100 Glitch-less Attenuation State Transitions X X X X X H L H 101 The PE43712 features a novel architecture to provide the best-in-class glitch-less transition behavior when changing attenuation states. When RF input power is applied, the output power spikes are greatly reduced (≤0.3 dB) during attenuation state changes when comparing to previous generations of DSAs. X X X X X H H L 110 X X X X X H H H 111 Table 6 • Serial Attenuation Word Truth Table Attenuation Word Truth Tables D7 D6 D5 D4 D3 D2 D1 Table 4–Table 6 provide the truth tables for the PE43712. Table 4 • Parallel Truth Table Parallel Control Setting D0 (LSB) Attenuation Setting RF1–RF2 L L L L L L L L Reference IL L L L L L L L H 0.25 dB L L L L L L H L 0.5 dB L L L L L H L L 1 dB L L L L H L L L 2 dB D6 D5 D4 D3 D2 D1 D0 Attenuation Setting RF1–RF2 L L L L L L L Reference IL L L L H L L L L 4 dB L L L L L L H 0.25 dB L L H L L L L L 8 dB L L L L L H L 0.5 dB L H L L L L L L 16 dB L L L L H L L 1 dB L H H H H H H H 31.75 dB L L L H L L L 2 dB L L H L L L L 4 dB L H L L L L L 8 dB H L L L L L L 16 dB H H H H H H H 31.75 dB Page 6 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Serial Addressable Register Map Figure 2 provides the Serial Addressable register map for the PE43712. Figure 2 • Serial Addressable Register Map Bits can either be set to logic high or logic low D7 must be set to logic low MSB (last in) LSB (first in) Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Address Word Attenuation Word The attenuation word is derived directly from the value of the attenuation state. To find the attenuation word, multiply the value of the state by four, then convert to binary. For example, to program the 18.25 dB state at address 3: 4 × 18.25 = 73 73 → 01001001 Address Word: XXXXX011 Attenuation Word: 01001001 Serial Input: XXXXX01101001001 DOC-85209-5 – (5/2022) Page 7 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Programming Options Parallel/Serial Selection Either a Parallel or Serial addressable interface can be used to control the PE43712. The P/S bit provides this selection, with P/S = LOW selecting the Parallel interface and P/S = HIGH selecting the Serial interface. Parallel Mode Interface The Parallel interface consists of seven CMOScompatible control lines that select the desired attenuation state, as shown in Table 4. The Parallel interface timing requirements are defined by Figure 4 (Parallel Interface Timing Diagram), Table 9 (Parallel and Direct Interface AC Characteristics) and switching time (Table 3). For Latched Parallel programming, the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 4) to latch new attenuation state into the device. For Direct Parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface The Serial-Addressable interface is a 16-bit Serial-In, Parallel-Out shift register buffered by a transparent latch. The 16-bits make up two words comprised of 8bits each. The first word is the Attenuation Word, which controls the state of the DSA. The second word is the Address Word, which is compared to the static (or programmed) logical states of the A0, A1 and A2 digital inputs. If there is an address match, the DSA changes state; otherwise its current state will remain unchanged. Figure 3 illustrates an example timing diagram for programming a state. It is required that all Parallel control inputs be grounded when the DSA is used in Serial-Addressable mode. The Serial-Addressable interface is controlled using three CMOS-compatible signals: SI, Clock (CLK) and LE. The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. The Address Word truth table is listed in Table 5. The Attenuation Word truth table is listed in Table 6. A programming example of the serial register is illustrated in Figure 2. The Serial timing diagram is illustrated in Figure 3. Power-up Control Settings The PE43712 will always initialize to the maximum attenuation setting (31.75 dB) on power-up for both the Serial Addressable and Latched Parallel modes of operation and will remain in this setting until the user latches in the next programming word. In Direct Parallel mode, the DSA can be preset to any state within the 31.75 dB range by pre-setting the Parallel control pins prior to power-up. In this mode, there is a 400 µs delay between the time the DSA is poweredup to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (31.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). Dynamic operation between Serial and Parallel programming modes is possible. If the DSA powers up in Serial mode (P/S = HIGH), all the Parallel control inputs DI[6:0] must be set to logic LOW. Prior to toggling to Parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic LOW. If the DSA powers up in either Latched or Direct Parallel mode, all Parallel pins DI[6:0] must be set to logic LOW prior to toggling to Serial Addressable mode (P/S = HIGH), and held LOW until the DSA has been programmed serially to ensure bit D[7] is set to logic LOW. The sequencing is only required once on power-up. Once completed, the DSA may be toggled between Serial and Parallel programming modes at will. Page 8 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 3 • Serial Timing Diagram DI[6:0] Parallel control inputs Bits can either be set to logic high or logic low Serial bit D[7] must be set to logic low DI[6:0] TDISU A[2:0] TDIH Valid TASU TAH TPSSU TPSIH P/S SI D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] TSISU TSIH CLK TCLKL TCLKH TLESU LE TLEPW Figure 4 • Latched Parallel/Direct Parallel Timing Diagram DI[6:0] P/S Parallel control inputs TPSIH TPSSU DI[6:0] Valid TDISU LE TDIH TLEPW Table 7 • Latch and Clock Specifications Latch Enable Shift Clock Function 0 ↑ Shift register clocked ↑ X Contents of shift register transferred to attenuator core DOC-85209-5 – (5/2022) Page 9 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Table 8 • Serial Interface AC Characteristics(*) Parameter/Condition Min Serial clock frequency, FCLK Max Unit 10 MHz Serial clock HIGH time, TCLKH 30 ns Serial clock LOW time, TCLKL 30 ns Last Serial clock rising edge setup time to Latch Enable rising edge, TLESU 10 ns Latch Enable minimum pulse width, TLEPW 30 ns Serial data setup time, TSISU 10 ns Serial data hold time, TSIH 10 ns Parallel data setup time, TDISU 100 ns Parallel data hold time, TDIH 100 ns Address setup time, TASU 100 ns Address hold time, TAH 100 ns Parallel/Serial setup time, TPSSU 100 ns Parallel/Serial hold time, TPSIH 100 ns Note: * VDD = 3.3V or 5.0V, –40 °C < TA < +105 °C, unless otherwise specified. Table 9 • Parallel and Direct Interface AC Characteristics(*) Parameter/Condition Min Max Unit Latch Enable minimum pulse width, TLEPW 30 ns Parallel data setup time, TDISU 100 ns Parallel data hold time, TDIH 100 ns Parallel/Serial setup time, TPSSU 100 ns Parallel/Serial hold time, TPSIH 100 ns Note: * VDD = 3.3V or 5.0V, –40 °C < TA < +105 °C, unless otherwise specified. Page 10 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Maximum RF Input Power (dBm) Figure 5 • Power De-rating Curve, 9 kHz–6 GHz, –40 to +105 °C Ambient, 50? 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 0.01 0.05 P0.1 dB Compression (≥ 48 MHz) Pulsed (≥ 48 MHz) CW & Pulsed (< 48 MHz) CW (≥ 48 MHz) 0.50 5.00 50.00 500.00 5000.00 Frequency (MHz) DOC-85209-5 – (5/2022) Page 11 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Typical Performance Data Figure 6–Figure 32 show the typical performance data at 25 °C and VDD = 3.3V, RF1 = RFIN, RF2 = RFOUT (ZS = ZL = 50Ω) unless otherwise specified. Figure 6 • Insertion Loss vs Temperature -40°C 25°C 85°C 105°C 0 Insertion Loss (dB) -1 -2 -3 -4 -5 -6 0 1 2 3 4 5 6 Frequency (GHz) Page 12 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 7 • Input Return Loss vs Attenuation Setting 0 dB 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 28 dB 31.75 dB 2 3 0 -5 Return Loss (dB) -10 -15 -20 -25 -30 -35 -40 -45 0 1 4 5 6 Frequency (GHz) Figure 8 • Output Return Loss vs Attenuation Setting 0 dB 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 28 dB 31.75 dB 0 -5 Return Loss (dB) -10 -15 -20 -25 -30 -35 -40 -45 -50 0 1 2 3 4 5 6 Frequency (GHz) DOC-85209-5 – (5/2022) Page 13 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 9 • Input Return Loss for 16 dB Attenuation Setting vs Temperature -40°C 25°C 85°C 105°C 0 -5 Return Loss (dB) -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 5 6 Frequency (GHz) Figure 10 • Output Return Loss for 16 dB Attenuation Setting vs Temperature -40°C 25°C 85°C 105°C 0 Return Loss (dB) -5 -10 -15 -20 -25 0 1 2 3 4 Frequency (GHz) Page 14 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 11 • Relative Phase Error vs Attenuation Setting 0 dB 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.75 dB 2 3 Relative Phase Error (deg) 60 50 40 30 20 10 0 -10 0 1 4 5 6 Frequency (GHz) Figure 12 • Relative Phase Error for 31.75 dB Attenuation Setting vs Frequency 0.9 GHz 1.8 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 6 GHz Relative Phase Error (deg) 60 50 40 30 20 10 0 -40 25 85 105 Temperature (°C) DOC-85209-5 – (5/2022) Page 15 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 13 • Attenuation Error @ 900 MHz vs Temperature -40°C 25°C 85°C 105°C Attenuation Error (dB) 0.75 0.5 0.25 0 -0.25 0 4 8 12 16 20 24 28 32 24 28 32 Attenuation Setting (dB) Figure 14 • Attenuation Error @ 1800 MHz vs Temperature -40°C 25°C 85°C 105°C Attenuation Error (dB) 0.75 0.5 0.25 0 -0.25 0 4 8 12 16 20 Attenuation Setting (dB) Page 16 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 15 • Attenuation Error @ 2200 MHz vs Temperature -40°C 25°C 85°C 105°C Attenuation Error (dB) 0.75 0.5 0.25 0 -0.25 0 4 8 12 16 20 24 28 32 24 28 32 Attenuation Setting (dB) Figure 16 • Attenuation Error @ 3000 MHz vs Temperature -40°C 25°C 85°C 105°C Attenuation Error (dB) 0.75 0.5 0.25 0 -0.25 0 4 8 12 16 20 Attenuation Setting (dB) DOC-85209-5 – (5/2022) Page 17 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 17 • Attenuation Error @ 4000 MHz vs Temperature -40°C 25°C 85°C 105°C Attenuation Error (dB) 1 0.75 0.5 0.25 0 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Figure 18 • IIP3 vs Attenuation Setting 0 dB 3.5 dB 7.5 dB 11 dB 14 dB 17.5 dB 21.5 dB 24.75 dB 28 dB 31.75 dB Input IP3 (dBm) 70 65 60 55 50 3 4 5 6 Frequency (GHz) Page 18 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 19 • 0.25 dB Step Attenuation vs Frequency(*) 1 GHz 2.2 GHz 3 GHz 4 GHz 0.2 Step Attenuation (dB) 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 4 8 12 16 20 24 28 32 28 32 Attenuation Setting (dB) Note: * Monotonicity is held so long as step attenuation does not cross below –0.25 dB. Figure 20 • 0.25 dB Step, Actual vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz 35 Actual Attenuation (dB) 30 25 20 15 10 5 0 0 4 8 12 16 20 24 Ideal Attenuation (dB) DOC-85209-5 – (5/2022) Page 19 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 21 • 0.25 dB Major State Bit Error vs Attenuation Setting 0.25 dB 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.75 dB 1 Attenuation Error (dB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 1 2 3 4 Frequency (GHz) Figure 22 • 0.25 dB Attenuation Error vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz Attenuation Error (dB) 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Page 20 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 23 • 0.5 dB Step Attenuation vs Frequency(*) 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 0.2 Step Attenuation (dB) 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 4 8 12 16 20 24 28 32 28 32 Attenuation Setting (dB) Note: * Monotonicity is held so long as step attenuation does not cross below –0.5 dB. Figure 24 • 0.5 dB Step, Actual vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 35 Actual Attenuation (dB) 30 25 20 15 10 5 0 0 4 8 12 16 20 24 Ideal Attenuation (dB) DOC-85209-5 – (5/2022) Page 21 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 25 • 0.5 dB Major State Bit Error vs Attenuation Setting 0.5 dB 1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB 1.2 Attenuation Error (dB) 1 0.8 0.6 0.4 0.2 0 -0.2 0 1 2 3 4 5 Frequency (GHz) Figure 26 • 0.5 dB Attenuation Error vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 1.2 Attenuation Error (dB) 1 0.8 0.6 0.4 0.2 0 -0.2 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Page 22 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 27 • 1 dB Step Attenuation vs Frequency(*) 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 6 GHz 0.25 Step Attenuation (dB) 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Note: * Monotonicity is held so long as step attenuation does not cross below –1 dB. Figure 28 • 1 dB Step, Actual vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 6 GHz 35 Actual Attenuation (dB) 30 25 20 15 10 5 0 0 4 8 12 16 20 24 28 32 Ideal Attenuation (dB) DOC-85209-5 – (5/2022) Page 23 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 29 • 1 dB Major State Bit Error vs Attenuation Setting 1 dB 2 dB 4 dB 8 dB 16 dB 31 dB 1.2 Attenuation Error (dB) 1 0.8 0.6 0.4 0.2 0 -0.2 0 1 2 3 4 5 6 Frequency (GHz) Figure 30 • 1 dB Attenuation Error vs Frequency 1 GHz 2.2 GHz 3 GHz 4 GHz 5 GHz 6 GHz 1.2 Attenuation Error (dB) 1 0.8 0.6 0.4 0.2 0 -0.2 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) Page 24 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 31 • Attenuation Transient (15.75–16 dB), Typical Switching Time = 275 ns Power (dBm) -15.4 Envelope Power (dBm) -15.6 Trigger starts ~730 ns -15.8 -16.0 -16.2 Glitch = 0.15 dB -16.4 -16.6 -16.8 -17.0 0 400 800 1200 1600 2000 2400 2800 3200 2400 2800 3200 Time (ns) Figure 32 • Attenuation Transient (16–15.75 dB), Typical Switching Time = 275 ns Power (dBm) -15.4 Envelope Power (dBm) -15.6 Trigger starts ~730 ns -15.8 -16.0 Glitch = 0.03 dB -16.2 -16.4 -16.6 -16.8 -17.0 0 400 800 1200 1600 2000 Time (ns) DOC-85209-5 – (5/2022) Page 25 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Evaluation Kit The digital step attenuator evaluation board (EVB) was designed to ease customer evaluation of the PE43712 digital step attenuator. The PE43712 EVB supports Direct Parallel, Latched Parallel and Serial modes. Evaluation Kit Setup Connect the EVB with the USB dongle board and USB cable as shown in Figure 33. Direct Parallel Programming Procedure Direct Parallel programming is suitable for manual operation without software programming. For manual Direct Parallel programming, position the Parallel/ Serial (P/S) select switch to the Parallel position. The LE switch must be switched to HIGH position. Switches D0–D6 are SP3T switches that enable the user to manually program the parallel bits. When D0–D6 are toggled to the HIGH position, logic high is presented to the parallel input. When toggled to the LOW position, logic low is presented to the parallel input. Setting LE and D0–D6 to the EXT position presents as OPEN, which is set for software programming of Latched Parallel and Serial modes. Table 4 depicts the Parallel truth table. Latched Parallel Programming Procedure For automated Latched Parallel programming, connect the USB dongle board and cable that is provided with the evaluation kit (EVK) from the USB port of the PC to the J5 header of the PE43712 EVB, and set the LE and D0–D6 SP3T switches to the EXT position. Position the Parallel/Serial (P/S) select switch to the Parallel position. The evaluation software is written to operate the DSA in Parallel mode. Ensure that the software GUI is set to Latched Parallel mode. Use the software GUI to enable the desired attenuation state. The software GUI automatically programs the DSA each time an attenuation state is enabled. Serial Addressable Programming Procedure For automated Serial programming, connect the USB dongle board and cable that is provided with the EVK from the USB port of the PC to the J5 header of the PE43712 EVB, and set the LE and D0–D6 SP3T switches to the EXT position. Position the Parallel/ Serial (P/S) select switch to the Serial position. Prior to programming, the user must define an address setting using the HDR2 header pin. Jump the middle column of pins on the HDR2 header (A0–A2) to the left column of pins to set logic LOW, or jump the middle row of pins to the right column of pins to set logic HIGH. If the HDR2 pins are left open, then 000 becomes the default address. The software GUI is written to operate the DSA in Serial mode. Use the software GUI to enable each setting to the desired attenuation state. The software GUI automatically programs the DSA each time an attenuation state is enabled. Page 26 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 33 • Evaluation Kit for PE43712 DOC-85209-5 – (5/2022) Page 27 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Figure 34 • Evaluation Kit Layout for PE43712 Page 28 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Pin Information This section provides pinout information for the PE43712. Figure 35 shows the pin map of this device for the available package. Table 10 provides a description for each pin. C0.25 C0.5 C1 C2 C4 C8 C16 SI 31 30 29 28 27 26 25 Pin 1 Dot Marking 32 Figure 35 • Pin Configuration (Top View) Table 10 • Pin Descriptions for PE43712 Pin No. Pin Name Description 1, 5, 6, 8–17, 19, 20 GND 2 VDD Supply voltage 3 P/S Serial/Parallel mode select 4 A0 Address bit A0 connection 7 RF1(1) RF1 port (RF input) RF2 port (RF output) Ground GND 1 24 CLK VDD 2 23 LE P/S 3 22 A1 18 RF2(1) A0 4 21 A2 21 A2 Address bit A2 connection GND 5 20 GND 22 A1 Address bit A1 connection GND 6 19 GND 23 LE Serial interface Latch Enable input RF1 7 18 RF2 GND CLK Serial interface Clock input 17 GND 24 8 25 SI Serial interface Data input 26 C16 (D6)(2) Parallel control bit, 16 dB 27 C8 (D5)(2) Parallel control bit, 8 dB 28 C4 (D4)(2) Parallel control bit, 4 dB 29 C2 (D3)(2) Parallel control bit, 2 dB 30 C1 (D2)(2) Parallel control bit, 1 dB 31 C0.5 (D1)(2) 32 C0.25 (D0)(2) Parallel control bit, 0.25 dB 16 GND 15 GND 14 GND 13 GND 12 GND GND 11 10 GND GND 9 Exposed Ground Pad Pad GND Parallel control bit, 0.5 dB Exposed pad: ground for proper operation Notes: 1) RF pins 7 and 18 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is met. 2) Ground C0.25, C0.5, C1, C2, C4, C8 and C16 if not in use. DOC-85209-5 – (5/2022) Page 29 of 32 www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Packaging Information This section provides packaging data including the moisture sensitivity level, package drawing, package marking and tape-and-reel information. Moisture Sensitivity Level The moisture sensitivity level rating for the PE43712 in the 32-lead 5 × 5 mm QFN package is MSL1. Package Drawing Figure 36 • Package Mechanical Drawing for 32-lead 5 × 5?× 0.85 mm QFN 0.10 C A 5.00 (2X) 3.10±0.05 0.40±0.05 (x32) B 17 0.60 (x32) 24 0.30 (x32) 0.50 (x28) 0.50 (x28) 16 25 5.00 3.10±0.05 0.25±0.05 (x32) 0.10 C 3.15 5.40 32 9 8 (2X) 1 3.50 REF PIN #1 CORNER TOP VIEW CHAMFER 0.35 x 45° 3.15 5.40 BOTTOM VIEW RECOMMENDED LAND PATTERN 0.10 C 0.10 0.05 0.85±0.05 0.05 C SEATING PLANE C A B C ALL FEATURES 0.203 REF 0.05 REF C SIDE VIEW Top-Marking Specification Figure 37 • Package Marking Specifications for PE43712 43712 YYWW ZZZZZZZ = YY = WW = ZZZZZZZ = Pin 1 indicator Last two digits of assembly year Assembly work week Assembly lot code (maximum seven characters) Page 30 of 32 DOC-85209-5 – (5/2022) www.psemi.com PE43712 UltraCMOS® RF Digital Step Attenuator Tape and Reel Specification PE43712 Figure 38 • Tape and Reel Specifications for 32-lead 5 × 5?× 0.85 mm QFN Direction of Feed Section A-A P1 P0 see note 1 T P2 see note 3 D1 D0 A E F see note 3 B0 A0 K0 A0 B0 K0 D0 D1 E F P0 P1 P2 T W0 5.25 5.25 1.10 1.50 + 0.1/ -0.0 1.5 min 1.75 ± 0.10 5.50 ± 0.05 4.00 8.00 2.00 ± 0.05 0.30 ± 0.05 12.00 ± 0.30 A W0 Pin 1 Notes: 1. 10 Sprocket hole pitch cumulative tolerance ±0.2 2. Camber in compliance with EIA 481 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole Dimensions are in millimeters unless otherwise specified DOC-85209-5 – (5/2022) Device Orientation in Tape Page 31 of 32 www.psemi.com UltraCMOS® RF Digital Step Attenuator PE43712 Ordering Information Table 11 lists the available ordering codes for the PE43712 as well as available shipping methods. Table 11 • Order Codes for PE43712 Order Codes Description Packaging Shipping Method PE43712B-Z PE43712 Digital step attenuator Green 32-lead 5 × 5 mm QFN 3000 units / T&R EK43712-03 PE43712 Evaluation kit Evaluation kit 1 / Box Document Categories Advance Information The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The datasheet contains preliminary data. Additional data may be added at a later date. pSemi reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The datasheet contains final data. In the event pSemi decides to change the specifications, pSemi will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Product Brief This document contains a shortened version of the datasheet. For the full datasheet, contact sales@psemi.com. Sales Contact For additional information, contact Sales at sales@psemi.com. Disclaimers The information in this document is believed to be reliable. However, pSemi assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. pSemi’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the pSemi product could create a situation in which personal injury or death might occur. pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Patent Statement pSemi products are protected under one or more of the following U.S. patents: patents.psemi.com Copyright and Trademark ©2017–2022, pSemi Corporation. All rights reserved. The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. Product Specification www.psemi.com DOC-85209-5 – (5/2022)