PE64907MLAA-Z

Product Specification PE64907 UltraCMOS® Digitally Tunable Capacitor (DTC) 100-3000 MHz Product Description PE64907 is a DuNE™ technology-enhanced Digitally Tunable Capacitor (DTC) based on Peregrine’s UltraCMOS® technology. This highly versatile product supports a wide variety of tuning circuit topologies with emphasis on impedance matching and aperture tuning applications. PE64907 offers high RF power handling and ruggedness while meeting challenging harmonic and linearity requirements enabled by Peregrine’s HaRP™ technology. The device is controlled through the widely supported 3-wire (SPI compatible) interface. All decoding and biasing is integrated on-chip and no external bypassing or filtering components are required. DuNE™ devices feature ease of use while delivering superior RF performance in the form of tuning accuracy, monotonicity, tuning ratio, power handling, size, and quality factor. With built-in bias voltage generation and ESD protection, DTC products provide a monolithically integrated tuning solution for demanding RF applications. Figure 1. Functional Diagram  3-wire (SPI) compatible serial interface with built-in bias voltage generation and ESD protection  DuNE™ technology enhanced  5-bit 32-state Digitally Tunable Capacitor  Shunt configuration C = 0.85 pF to 2.4 pF (2.82:1 tuning ratio) in discrete 50 fF steps  High RF power handling (30 Vpk RF) and linearity  Wide power supply range (2.3V to 4.8V) and low current consumption (typ. 140 μA at 2.75V)  High ESD tolerance of 2kV HBM on all pins  Applications include:  Tunable antennas  Tunable matching networks  Tunable filter networks Figure 2. Package Type 10-lead 2 x 2 x 0.55 mm QFN RF- RF+ ESD Serial Interface Features ESD CMOS Control Driver and ESD DOC-02169 Document No. DOC-85325-1 │ www.psemi.com ©2017 Peregrine Semiconductor Corp. All rights reserved. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com Page 1 of 10 PE64907 Product Specification Table 1. Electrical Specifications @ 25°C, VDD = 2.75V (In shunt configuration, RF- connected to GND) Parameter Condition Min Operating frequency Typ 100 Max Unit 3000 MHz Minimum capacitance (Cmin) State 00000, 100 MHz 0.68 0.85 1.02 pF Maximum capacitance (Cmax) State 11111, 100 MHz 1.92 2.40 2.88 pF Tuning ratio Cmax/Cmin, 100 MHz 2.82:1 Step size 5 bits (32 states), 100 MHz 0.050 Quality factor at Cmin1 698 - 960 MHz, with LS removed 1710 - 2170 MHz, with LS removed 41 37 Quality Factor at Cmax1 698 - 960 MHz, with LS removed 1710 - 2170 MHz, with LS removed 34 16 Self resonant frequency State 00000 State 11111 8.3 3.5 Harmonics2 2fo, 3fo: 698 - 915 MHz; PIN +34 dBm, 50Ω 2fo, 3fo: 1710 - 1910 MHz; PIN +32 dBm, 50Ω -36 -36 dBm dBm IMD3 Bands I,II,V/VIII, +20 dBm CW @ TX freq, -15 dBm CW @ 2Tx-Rx freq, 50Ω -105 dBm Third order intercept point (IP3) Shunt configuration derived from IMD3 spec IP3 = (2PTX + Pblock - IMD3) / 2 Switching time3,4 State change to 10/90% delta capacitance between any two states 12 μs Time from VDD within specification to all performances within specification 70 μs State change from Standby mode to RF state to all performances within specification 70 μs Start-up time 3 Wake-up time3,4 pF GHz 65 dBm Notes: 1. Q for a shunt DTC based on a series RLC equivalent circuit Q = XC / R = (X - XL) / R, where X = XL + XC , XL = 2*pi*f*L, XC = -1 / (2*pi*f*C), which is equal to removing the effect of parasitic inductance LS 2. In shunt between 50Ω ports. Pulsed RF input with 4620 μS period, 50% duty cycle, measured per 3GPP TS 45.005 3. DC path to ground at RF— must be provided to achieve specified performance 4. State change activated on falling edge of SEN following data word ©2017 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 10 Document No. DOC-85325-1 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com │ UltraCMOS® RFIC Solutions PE64907 Product Specification Figure 3. Pin Configuration (Top View) Table 3. Operating Ranges Symbol Min Typ Max Unit Supply voltage VDD 2.30 2.75 4.80 V Supply current (VDD = 2.75V) IDD 140 200 μA Standby current (VDD = 2.75V) IDD 25 Control voltage high VIH 1.2 1.8 3.1 V Control voltage low VIL 0 0 Parameter Table 2. Pin Descriptions 0.57 V RF input power (50Ω)1 698 - 915 MHz 1710 - 1910 MHz +34 +32 dBm dBm Peak operating RF voltage2 VP to VM VP to RFGND 30 30 Vpk Vpk Operating temperature range TOP -40 +25 +85 °C Storage temperature range TST -65 +25 +150 °C Notes: Pin # Pin Name Description 1 RF- Negative RF port1 2 RF- Negative RF port1 3 GND Ground2 4 VDD Power supply pin 5 SCL Serial interface clock input 6 SEN Serial interface latch enable input 7 SDA Serial interface data input 8 RF+ Positive RF port1 9 RF+ Positive RF port1 10 GND Ground2 Pad GND Exposed pad: ground for proper operation2 Notes: 1. For optimal performance, recommend typing Pins 1-2 and Pins 8-9 together on PCB 2. For optimal performance, recommend tying Pins 3, 10, and exposed ground pad together on PCB Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE64907 in the 10-lead 2 x 2 x 0.55 mm QFN package is MSL1. μA 1. Maximum power available from 50Ω source. Pulsed RF input with 4620 μS period, 50% duty cycle, measured per 3GPP TS 45.005 measured in shunt between 50Ω ports, RF- connected to GND 2. Node voltages defined per Equivalent Circuit Model Schematic (Figure 13). When DTC is used as a part of reactive network, impedance transformation may cause the internal RF voltages (VP, VM) to exceed peak operating RF voltage even with specified RF input power levels. For operation above about +20 dBm (100 mW), the complete RF circuit must be simulated using actual input power and load conditions, and internal node voltages (VP, VM in Figure 13) monitored to not exceed 30 Vpk Table 4. Absolute Maximum Ratings Parameter/Condition ESD Voltage HBM 1 Symbol Min VESD Max Unit 2000 V Note 1: Human Body Model (MIL-STD-883 Method 3015.7) Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS® device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS® devices are immune to latch-up. Document No. DOC-85325-1 │ www.psemi.com ©2017 Peregrine Semiconductor Corp. All rights reserved. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com Page 3 of 10 PE64907 Product Specification Performance Plots @ 25°C and 2.75V unless otherwise specified Figure 4. Measured Shunt C (@ 100 MHz) vs State Figure 5. Measured Shunt S11 (major states) 3 Capacitance (pF) 2.5 2 C0 C1 C2 C4 C8 C15 C31 1.5 1 0.5 0 0 5 10 15 State 20 25 30 Figure 6. Measured Step Size vs State (frequency) 200 Frequency(800 - 900 MHz) Figure 7. Measured Shunt C vs Frequency (major states) q 100 MHz 1000 MHz 2000 MHz 180 4 Capacitance (pF) Step size (fF) 140 100 80 j C0 C1 C2 C4 C8 C15 C31 4.5 160 120 y 5 3.5 3 2.5 2 1.5 60 1 40 20 0.5 0 5 10 15 State 20 25 0 30 Figure 8. Measured Shunt Q vs Frequency (major states) q y ( j ) 30 20 20 10 0 0.5 1 1.5 2 Frequency(GHz) 2.5 ©2017 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 10 2.5 40 40 0 1.5 2 Frequency(GHz) 50 Q Q 60 1 60 C0 C1 C2 C4 C8 C15 C31 80 0.5 Figure 9. Measured Shunt Q vs State 120 100 0 698 MHz 960 MHz 1710 MHz 2170 MHz 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 State Document No. DOC-85325-1 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com │ UltraCMOS® RFIC Solutions PE64907 Product Specification Serial Interface Operation and Sharing DTC does not count how many bits are clocked and only maintains the last 8 bits it received. The PE64907 is controlled by a three wire SPIcompatible interface with enable active high. As shown in Figure 10, the serial master initiates the start of a telegram by driving the SEN (Serial Enable) line high. Each bit of the 8-bit telegram (MSB first in) is clocked in on the rising edge of SCL (Serial Clock), as shown in Table 5 and Figure 10. Transitions on SDA (Serial Data) are allowed on the falling edge of SCL. The DTC activates the data on the falling edge of SEN. The More than 1 DTC can be controlled by one interface by utilizing a dedicated enable (SEN) line for each DTC. SDA, SCL, and VDD lines may be shared as shown in Figure 11. Dedicated SEN lines act as a chip select such that each DTC will only respond to serial transactions intended for them. This makes each DTC change states sequentially as they are programmed. Figure 10. Serial Interface Timing Diagram tEOW tESU tDSU tDHD tR tF tSCL tEHD tSCLH tSCLL SEN SCL SDA DTC Data b0 b6 b7 b5 Dm-2 0 1 b6 0 1 b5 STB 2 b3 b2 b1 b4 b3 b2 b1 b0 d4 d3 d2 d1 d0 MSB (first in) Dm Figure 11. Recommended Bus Sharing DTC 1 RF+ LSB (last in) Notes: 1. These bits are reserved and must be written to 0 for proper operation 2. The DTC is active when low (set to 0) and in low-current stand-by mode when high (set to 1) VDD VDD SDA SCL SEN1 SEN2 SDA SCL SEN Table 6. Serial Interface Timing Characteristics GND VDD = 2.75V, -40 °C < TA < +85 °C, unless otherwise specified Symbol b0 Dm-1 Table 5. 8-Bit Serial Programming Register Map b7 b4 Parameter Min Max RF- Unit tSCL Serial Clock Period 38.4 ns tSCLL SCL Low Time 13.2 ns tSCLH SCL High Time 13.2 DTC 2 RF+ ns VDD SDA SCL tESU SEN rising edge to SCL rising edge 19.2 ns SEN tEHD SCL rising edge to SEN falling edge 19.2 ns tDSU SDA valid to SCL rising edge 13.2 ns tDHD SDA valid after SCL rising edge 13.2 ns tEOW SEN falling edge to SEN rising edge 38.4 ns tR SCL, SDA, SEN Rise Time tF SCL, SDA, SEN Fall Time Document No. DOC-85325-1 │ www.psemi.com ns 6.5 6.5 ns GND RF- ©2017 Peregrine Semiconductor Corp. All rights reserved. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com Page 5 of 10 PE64907 Product Specification Equivalent Circuit Model Description The DTC Equivalent Circuit Model includes all parasitic elements and is accurate in both series and shunt configurations, reflecting physical circuit behavior accurately and providing very close correlation to measured data. It can easily be used in circuit simulation programs. RS Cs [pF] Rs [Ω] CP1 CP2 0x00 00000 0 0.38 1.40 0.47 0.61 0x01 00001 1 0.44 2.27 0.46 0.62 0x02 00010 2 0.49 2.83 0.46 0.63 0x03 00011 3 0.55 3.08 0.45 0.64 0x04 00100 4 0.60 3.12 0.45 0.65 0x05 00101 5 0.66 3.05 0.44 0.66 0x06 00110 6 0.72 2.93 0.43 0.67 0x07 00111 7 0.77 2.78 0.43 0.68 0x08 01000 8 0.83 2.64 0.42 0.69 0x09 01001 9 0.88 2.51 0.42 0.70 RP1 0x0A 01010 10 0.94 2.39 0.41 0.71 0x0B 01011 11 1.00 2.27 0.40 0.72 RFGND 0x0C 01100 12 1.05 2.17 0.40 0.73 0x0D 01101 13 1.11 2.08 0.39 0.73 0x0E 01110 14 1.16 2.00 0.38 0.74 0x0F 01111 15 1.22 1.93 0.38 0.75 0x10 10000 16 1.28 1.86 0.37 0.76 0x11 10001 17 1.33 1.80 0.37 0.77 0x12 10010 18 1.39 1.75 0.36 0.78 0x13 10011 19 1.44 1.70 0.35 0.79 0x14 10100 20 1.50 1.65 0.35 0.80 0x15 10101 21 1.56 1.61 0.34 0.81 0x16 10110 22 1.61 1.57 0.34 0.82 0x17 10111 23 1.67 1.54 0.33 0.83 0x18 11000 24 1.72 1.51 0.32 0.84 0x19 11001 25 1.78 1.48 0.32 0.85 0x1A 11010 26 1.84 1.45 0.31 0.86 CS VM LS RF- CP2 RP2 RP2 RP1 Table 7. Equivalent Circuit Model Parameters Variable Equation (state = 0, 1, 2…31) Unit CS 0.056*state + 0.38 pF RS 20/(state+20/(state+0.7)) + 0.7 Ω RP1 8+state Ω RP2 25000+3*state^3 Ω CP1 -0.0061*state + 0.47 pF CP2 0.0096*state + 0.61 pF LS 0.35 nH ©2017 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 10 Parasitic Elements Dec RF+ CP1 DTC Core Bin Figure 12. Equivalent Circuit Model Schematic VP State Hex For VP and VM max operating limits, refer to Table 3. LS Table 8. Equivalent Circuit Data 0x1B 11011 27 1.89 1.42 0.31 0.87 0x1C 11100 28 1.95 1.40 0.30 0.88 0x1D 11101 29 2.00 1.37 0.29 0.89 0x1E 11110 30 2.06 1.35 0.29 0.90 0x1F 11111 31 2.12 1.33 0.28 0.91 Document No. DOC-85325-1 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com │ UltraCMOS® RFIC Solutions PE64907 Product Specification Series Operation In Series configuration, the effective capacitance between RF+ and RF- ports is represented by Cs and tuning ratio as CSmax/CSmin. Figure 15. Measured Series S11/S22 (major states) S11 C0 S22 C0 S11 C1 S22 C1 Figure 13. Effective Capacitance Diagram S11 C2 S22 C2 S11 C4 S22 C4 S11 C8 S22 C8 S11 C15 S22 C15 S11 C31 S22 C31 Frequency(.3 - 3000 MHz) Shunt Configuration (looking into RF+ when RF- is grounded) will have higher total capacitance at RF+ due to parallel combination of Cs with parasitic capacitance CP1 (CS + CP1), as demonstrated in Figure 14 and Table 9. Figure 16. Measured Series S21 vs. Frequency 0 -5 -10 Figure 14. Typical Capacitance vs. State dB(S21) -15 Capacitance 3.0 -20 2.5 -25 2.0 -30 1.5 -35 1.0 Capacitance in Series Configuration (Cs) 0.5 Capacitance in Shunt Configuration (Cs+Cp1) 0.0 0 5 10 15 20 25 30 State Table 9. Effective Capacitance Summary Effective Capacitance Cmin (state 0) Series (RF+ to RF-) CS 0.38 2.12 5.58:1 Shunt (RF+ to GND) CS + CP1 0.85 2.4 2.82:1 Configuration Cmax Tuning (state 31) Ratio -40 C0 C1 C2 C4 C8 C16 C31 0 0.5 1 1.5 2 Frequency (GHz) 2.5 3 When the DTC is used as a part of a reactive network, impedance transformation may cause the internal RF voltages (VP and VM in Figure 12) to exceed peak operating RF voltage. The complete RF circuit must be simulated using actual input power and load conditions to ensure neither VP nor VM exceeds 30 Vpk. S11 and S21 for series configuration is illustrated in Figures 15 and 16. S21 includes mismatch and dissipative losses and is not indicative of tuning network loss. Equivalent Circuit Model can be used for simulation of tuning network loss. Document No. DOC-85325-1 │ www.psemi.com ©2017 Peregrine Semiconductor Corp. All rights reserved. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com Page 7 of 10 PE64907 Product Specification Layout Recommendations Evaluation Board For optimal results, place a ground fill directly under the DTC package on the PCB. Layout isolation is desired between all control and RF lines. When using the DTC in a shunt configuration, it is important to make sure the RF-pin is solidly grounded to a filled ground plane. Ground traces should be as short as possible to minimize inductance. A continuous ground plane is preferred on the top layer of the PCB. When multiple DTCs are used together, the physical distance between them should be minimized and the connection should be as wide as possible to minimize series parasitic inductance. The 101-0675 Evaluation Board (EVB) was designed for accurate measurement of the DTC impedance and loss. Two configurations are available: 1 Port Shunt (J3) and 2 Port Shunt (J4, J5). Three calibration standards are provided. The open (J2) and short (J1) standards (104 ps delay) are used for performing port extensions and accounting for electrical length and transmission line loss. The Thru (J9, J10) standard can be used to estimate PCB transmission line losses for scalar de-embedding of the 2 Port Series configuration (J4, J5). Figure 17. Recommended Schematic of Multiple DTCs The board consists of a 4 layer stack with 2 outer layers made of Rogers 4350B (εr = 3.48) and 2 inner layers of FR4 (εr = 4.80). The total thickness of this board is 62 mils (1.57 mm). The inner layers provide a ground plane for the transmission lines. Each transmission line is designed using a coplanar waveguide with ground plane (CPWG) model using a trace width of 32 mils (0.813 mm), gap of 15 mils (0.381 mm), and a metal thickness of 1.4 mils (0.051 mm). Figure 19. Evaluation Board Layout Figure 18. Recommended Layout of Multiple DTCs 101-0675 ©2017 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 10 Document No. DOC-85325-1 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com │ UltraCMOS® RFIC Solutions PE64907 Product Specification Figure 20. Package Drawing 10-lead 2 x 2 x 0.55 mm QFN 2.00 A 0.90±0.05 (2X) B 0.25 (x10) 0.25±0.05 (x10) 0.10 C 0.45 (x10) 0.50 (x6) 6 9 0.90±0.05 2.00 0.20±0.05 (X10) 2.40 0.95 4 0.10 C 1 0.50 (2X) (x6) 0.95 2.40 1.50 Pin #1 Corner RECOMMENDED LAND PATTERN BOTTOM VIEW TOP VIEW DOC-01865 0.10 C 0.10 0.05 0.60 MAX 0.05 C C A B C ALL FEATURES SEATING PLANE 0.152 Ref. 0.05 C Notes: 1. Dimensions are in millimeters 2. Dimensions and tolerances per ASME Y14.5M, 1994 SIDE VIEW Figure 21. Top Marking Specifications PPZZ YWW 17-0112 Document No. DOC-85325-1 │ www.psemi.com Marking Spec Symbol Package Marking PP DH* ZZ 00-99 Y 0-9 WW 01-53 Definition Part number marking for PE64907 Last two digits of lot code Last digit of year, starting from 2009 (0 for 2010, 1 for 2011, etc) Work week * Note: (PP), the package marking specific to the PE64906, is shown in the figure instead of the standard Peregrine package marking symbol (P) ©2017 Peregrine Semiconductor Corp. All rights reserved. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com Page 9 of 10 PE64907 Product Specification Figure 22. Tape and Reel Specifications Tape Feed Direction Pin 1 Top of Device Device Orientation in Tape Table 10. Ordering Information Order Code Description Package Shipping Method PE64907B-Z PE64907 DTC 10-lead 2x2 QFN 3,000 units/T&R EK64907-12 PE64907 Evaluation kit Evaluation kit 1 set/box Sales Contact and Information For sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. ©2017 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 10 No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com. Document No. DOC-85325-1 Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com │ UltraCMOS® RFIC Solutions