RL2048PAG-712

DATASHEET Lighting Imaging Telecom Imaging Product Line P-Series Linear Photodiode Array Imagers 14µm, single output, 512, 1024, 2048 elements Description In the P-series linear imagers, PerkinElmer has combined the best features of high-sensitivity photodiode array detection and high-speed chargecoupled scanning to offer an uncompromising solution to the increasing demands of advanced imaging applications. These high-performance imagers feature low noise, high sensitivity, impressive charge storage capacity, and lag-free dynamic imaging in a convenient single-output architecture. The 14 µm square contiguous pixels in these imagers reproduce images with minimum information loss and artifact generation, while their unique photodiode structure provides excellent blue response extending below 250 nm in the ultraviolet. The two-phase CCD readout register requires only five volts for clocking yet achieves excellent charge transfer efficiency. Additional electrodes provide independent control of exposure and antiblooming. Finally, the high-sensitivity readout amplifier provides a large output signal to relax the noise requirements on the camera electronics that follow. Available in array lengths of 512, 1024 and 2048 elements with either lowcost glass or UV-enhanced fused silica windows, these versatile imagers are widely used in high-speed document reading, web inspection, mail sorting, production measurement and gauging position sensing, spectroscopy and many other industrial and scientific applications requiring peak imager performance. Note: While the P-Series imagers have been designed to resist electrostatic discharge (ESD), they can be damaged from such discharges. Always observe proper ESD precautions when handling and storing this imager. Features • Extended spectral range—250 to 1000 nm • 40 MHz pixel readout rate • 2500:1 dynamic range • 5-volt clocking • Line rates to 70 kHz • Ultra low image lag • Electronic exposure control • Antiblooming control • Square pixels with 100% fill factor w ww.perkinelmer.com/opto DSP-101 01H - 7/2002W Page 1 Linear Photodiode Array Imagers Description (cont.) Figure 2a: Spectral Sensitivity Curve 100 90 80 70 60 50 40 30 20 10 0 250 350 450 550 650 750 850 950 1050 100 90 Right Scale 80 70 60 50 40 QE (%) Responsivity (V/ J/cm 2 ) P-series imagers combine high-performance photodiodes with high-speed CCD readout registers and a highsensitivity readout amplifier. Refer to Figure 1 for construction details. Left Scale 30 20 10 0 Light Detection Area The light detection area in P-series imagers is a linear array of contiguous pinned photodiodes on 14 µm centers. These photodiodes are constructed using PerkinElmer’s advanced photodiode design that extends short-wavelength sensitivity into the deep UV below 250 nm, while preserving 100% fill factor and delivering extremely low image lag. This unique design also avoids polysilicon layers in the light detection area that reduces the quantum efficiency of most CCD imagers. The P-series imagers are supplied with glass windows for general visible use, and fused silica windows for use in the ultraviolet below 350 nm. See Figure 2 for the sensitivity and window transmission curves. For lowest lag, all P-series imagers feature pinned photodiodes. Pinning, which requires a special semiconductor process step, provides a uniform internal voltage reference for the charge stored in every photodiode. This stable reference assures that every photodiode is fully discharged after every scan. Wavelength (nm) Figure 2b: Window Transmission Curve 100 90 80 Fused Silica Transmission (%) 70 60 50 40 30 20 10 0 150 250 350 450 550 650 750 850 950 1050 Glass Wavelength (nm) Photodiodes covered with light shields included at one or both ends of the imager provide a dark current reference for clamping. These are separated from the active photodiodes by two unshielded transition pixels that assure uniform response out to the last active photodiode. Due to the potential for light leakage, the two dark pixels nearest the transition pixels should not be used as a dark reference. Figure 1: Imager Functional Diagram N = 512 for the RL0512P N = 1024 for the RL1024P N = 2048 for the RL2048P 3 10 2 N 2 10 Isolation stages Dark pixels (D1 ... D10) Transition pixels (T1, T2) (Light shield ends between D10 and T1) Active pixels (1...N) Transition pixels (T3, T4) (Light shield ends between T4 and D11) Dark pixels (D11...D20) (Not used in RL0512P) Antiblooming/Exposure Control Gate D1 . . . . . . . . . . . . . . . . . . . .D10 T1 T2 1 2 3 . . . . . . . . . N-1 N T3 T4 D11 . . . . . . . . . . . . . . . . . . . .D20 Transfer Gate Output 2-Phase Buried Channel CCD Shift Register { 3 CCD Isolation Stages Amp www.perkinelmer.com/opto DSP-101 01H - 7/2002W Page 2 Linear Photodiode Array Imagers Horizontal Shift Registers Charge packets collected in the photodiodes as light is received are converted to a serialized output stream through a buried-channel, two-phase CCD shift register that provides high charge transfer efficiency at shift frequencies up to 40 MHz. The PerkinElmer 5-volt CCD process used in this design enables low-power, high-speed operation with inexpensive, readily available driver devices. The transfer gate (ØTG) controls the movement of charge packets from the photodiodes to the CCD shift register. During charge integration, the voltage controlling the transfer gate is held in its low state to isolate the photodiodes from the shift register. When transfer of charge to the shift register is desired, øTG is switched to its high state to create a transfer channel between the photodiodes and the shift register. The charge transfer sequence, detailed in Figure 4, proceeds as follows: After readout of a particular image line (n), the shift register is empty of charge and ready to accept new charge packets from the photodiodes representing image line (n+1). To begin the transfer sequence, the horizontal clock pulses (ø1 and ø2) are stopped with ø1 held in its high state, and ø2 in its low state. The transfer gate voltage phase (øTG) is then switched high to start the transfer of charge to the shift register. Once the transfer gate reaches its high state, the photo gate voltage (øPG) is set high to complete the transfer. It is recommended that the photo gate voltage be held in the high state for at least 0.1 µs to ensure complete transfer. After this interval, the photo gate voltage is returned to its low state, and when that is completed, the transfer gate voltage is also returned to the low state. The details of the transfer timing are shown in Figure 3 with ranges and tolerances in Table 1. After transfer, the charge is transported along the shift register by the alternate action of two horizontal phase voltages Figure 3: Transfer Timing Diagram t6 t1 ØPG t5 t3 t2 ØTG t4 t6 ØAB t8 t7 Ø1 VOut Note 1 Note 2 Notes: 1. Transition and dark pixels 2. Active pixels Table 1. Transfer Timing Requirements Item Delay of øTG falling edge from øPG falling edge Delay of øTG rising edge from end of ø1 and ø2 clocks Delay of øAB rising edge from øPG falling edge Sym t1 Min 5 ns Typ 20 ns Max - t2 t3 t4 t5 t6 t7 t8 0 ns 5 ns 100 ns 100 ns 10 ns 0 ns - 10 ns 5 ns 500 ns 400 ns 20 ns 750 ns1 - øTG pulse width øPG pulse width Rise/fall time Integration time øAB pulse width Note 1: 750ns is the typical time to fully reset the photodiode. Figure 4: Readout Timing Waveforms t1 Ø1 t2 Ø2 t6 t4 t5 ØRG www.perkinelmer.com/opto DSP-101 01H - 7/2002W Page 3 Linear Photodiode Array Imagers Horizontal Shift Registers (cont.) Table 2. Readout Timing Requirements Item Sym t1 t2 t4 t5 t6 Min 25 ns 5 ns 0 ns Typ 5 ns 5 ns Max - ø1 and ø2. While the two-phase CCD shift register architecture allows relaxed timing tolerances over those required in three- or four-phase designs, optimum charge transfer efficiency and lowest power dissipation is obtained when the overlap of the twophase CCD clocks occurs around the 50% transition level. Additionally, the phase difference between signals ø1 and ø2 should be maintained near 180° and the duty cycle of both signals should be set near 50% to prevent loss of full-well charge storage capacity and charge transfer efficiency. Readout timing details are shown in Figure 4 with ranges and tolerances in Table 2. ø1, ø2 clock period ø1, ø2 rise/fall time øRG rise/fall time øRG clock - high duration Delay of ø1 high - low transition from øRG low* Note: The cross over point for ø1 and ø2 clock transitions should occur within the 10 - 90% level of the clock amplitude. Table 3. Imager Performance (Typical) Pixel count 512 elements (RL0512P) 1024 elements (RL1024P) 2048 elements (RL2048P) Pixel size Exposure control Horizontal clocking Number of outputs Dynamic range1 Readout noise (rms) amplifier reset transistor total noise without CDS Saturation exposure2 Noise equivalent exposure2 Amplifier sensitivity Saturation output voltage Saturation charge capacity Charge transfer efficiency Peak responsivity PRNU match across array Dead pixels Lag Spectral response range Data rate (per output) Notes: 1. Defined as Qsat/rms noise (total). 2. For illumination at 750 nm. 14 µm x 14 µm yes 2Ø (5V clock amplitude) 1 2500:1 25 electrons 55 electrons 60 electrons 24 nJ/cm2 9.6 pJ/cm2 4 µV/electrons 600 mv 150,000 electrons 0.99995 25V/µJ/cm2 ±10% 0 < 1% 250 nm - 1000 nm 40 MHz Timing Requirements In high-speed applications, fast waveform transitions allow maximum settling time of the output signal. However, it is generally advisable to use the slowest rise and fall times consistent with required video performance because fast edges tend to introduce more transition noise into the video waveform. When the highest speeds are required, careful smoothing of the waveform transitions may improve the balance between speed and video quality. Output Amplifier Charge emerging from the last stage of the shift register is converted to a voltage signal by a charge integrator and video amplifier. The integrator, a capacitor created by a floating diffusion, is initially set to a DC reference voltage (VRD), by setting the reset transistor voltage (øRG) to its high state. To read out the charge, øRG is pulsed low turning the reset transistor off and isolating the integrator from VRD. The next time ø1 goes low, the charge packet is transferred to the integrator where it generates a voltage proportional to the packet size. The reset transistor voltage, øRG, must reach its low state prior to the high-to-low transition of ø1. An apparent clipping of the video signal will result if this www.perkinelmer.com/opto DSP-101 01H - 7/2002W Page 4 Linear Photodiode Array Imagers Output Amplifier (cont.) condition is not satisfied. Figure 4 details the clock waveform requirements and overlap tolerances. The video amplifier buffers the signal from the integrator for output from the imager. Care must be taken to keep the load on this amplifier within its ability to drive highly reactive or low impedance loads. The half power bandwidth into an external load of 10 pF is 150 MHz. It is recommended that the output video signal be buffered with a wide bandwidth emitter follower or other appropriate amplifier to provide a large ZIN to the output amplifier. Keep the external amplifier close to the output pins to minimize stray inductive and capacitive coupling of the output signal that can harm signal quality. Table 4. Operating Voltages Signal ø1 , ø2 Function Horizontal Clocks Transfer Gate Photo Gate Antiblooming Gate Output Gate Reset Gate Amplifier Voltage Supply Amplifier Reset Drain Amplifier Return / Light Shield High Low State High Low High Low High Low High Low Voltage 5 0 8 0 8 -4 4 -4 3 8 0 12 9.5 0 Tolerance ±5% ±10% ±5% ±5% ±5% ±10% ±5% ±5% øTG øPG øAB VOG øRG VDD VRD VRD/LS Table 5. Absolute Maximum Rating Above Which Useful Life May Be Impaired Min Temperature empera Storage Operating Voltage (with respect to GND) oltage GND) Pins 3, 4, 17 - 19 Pins 2, 10, 20 Pins 1, 11 Pins 15, 16 -25 -25 -0.3 -0.3 -0.3 -4.3 Max +85 +55 +18 +18 +0 +18 Units °C °C V V V V Exposure Control and Antiblooming An exposure control feature in the P-series imagers supports variable charge accumulation time in the photodiode. When the antiblooming gate voltage (øAB) is set to its high state, charge is drained from the pixel storage gate to the exposure control drain. During normal charge collection in the photodiode, øAB is set to its low state. Due to the timing requirements of the exposure control mode, charge is always accumulated at the end of the period just before the charge is transferred to the readout register. Figure 3 includes the timing requirements for exposure control with the antiblooming gate. The exposure control timing shown will act on the charge packets that emerge as video data on the next readout cycle. Precautionary Note: The CCD output pin (Pin #2) must never be shorted to either VSS or VDD while power is applied to the device. Catastrophic device failure will result! Imager Performance In P-series images each element performs its own function admirably while integrating smoothly with the other elements on the team. The photodiodes efficiently transform light to charge, the readout registers accurately transport the charge to the amplifier, and the amplifier delivers a clean, robust signal for use in image processing electronics. While the actual performance of these imagers depends strongly on the details of the electronics and timing the camera provides, their straightforward implementation requirements facilitate optimum designs. www.perkinelmer.com/opto DSP-101 01H - 7/2002W Page 5 Linear Photodiode Array Imagers Table 6. Pinout Description and Capacitance Values of Clocked Phases Operating Conditions For optimum performance and longest life, carefully follow the operational requirements of these imagers. Provide stable voltage sources free of noise and variation and clean waveforms with controlled edges. Protect the imager from electrostatic discharge and excessive voltages and temperature. Do not violate the limits on output register speed or reduce timing margins below the minimums. Capacitance (pF) (Typ) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Sym VSS VOut Function Amplifier return Signal output CCD horizontal phase 2 CCD horizontal phase 1 No connection No connection No connection No connection No connection Amplifier drain supply Light shield/die attach No connection No connection No connection Antiblooming gate Photo gate Transfer gate Output gate Reset gate Reset drain 70 100 90 8 7 35 50 50 8 2 20 25 25 8 2 Pixels 2048 50 75 270 350 1024 30 45 140 180 512 20 30 70 90 ø2 ø1 N/C N/C N/C N/C N/C VDD LS N/C N/C N/C Imager Configuration All P-series imagers are constructed using ceramic packages and opticallyflat windows. Imager die are secured to precision leadframes by thermal silver-filled epoxy. Packages are baked before sealing to elminate moisture, and tested for seal integrity. øAB øPG øTG VOG øRG VRD Figure 5. Pinout Configuration VSS VOut ØH2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VRD Ø RG VOG Ø TG Ø PG Ø AB N/C N/C N/C LS ØH1 N/C N/C N/C N/C N/C VDD w ww.perkinelmer.com/opto DSP-101 01H - 7/2002W Page 6 Linear Photodiode Array Imagers Figure 6: Outline Drawings A Pixel 1 * Measurements in inches (millimeters) * Maximum angular error is ±15 milliradians 0.205 ± 0.0075 (5.21 ± 0.19) • Sensing Area 14 m 0.395 ± 0.008 (10.03 ± 0.20) 0.020 ± 0.002 (0.508 ± 0.05) 0.020 ± 0.002 (0.508 ± 0.05) 0.080 ± 0.009 (2.032 ± 0.23) 0.450 ± 0.0075 (11.43 ± 0.19) B 0.020 ± 0.002 (0.50 ± 0.05) 0.300 0.018 ± 0.002 (7.62) (0.46 ± 0.05) 0.100 ± 0.005 (2.54 ± 0.13) 0.900 ± 0.005 (22.86 ± 0.13) 0.170 (4.32) 0.400 ± 0.010 (10.16 ± 0.25) (at stand off) Ordering Information The RL0512, RL1024 and RL2048 P-series imagers are available with either glass or fused silica windows. On special orders, PerkinElmer can supply anti-reflectance coated windows or windowless packages. Imagers are individually packed in electrostaticresistant boxes and identified by lot number for tracking. Table 7. Package Dimensions and Tolerances A Device RL0512P RL1024P RL2048P Inches 0.284 0.566 1.131 mm 7.224 14.392 28.728 Inches 1.500 ± 0.15 1.500 ± 0.15 1.500 ± 0.15 B mm 38.1 ± 0.381 38.1 ± 0.381 38.1 ± 0.381 Notes: 1. Includes active and transition pixels. Table 8. Stock Part Numbers Active Pixels Window Glass Fused Silica 512 RL0512PAG-712 RL0512PAQ-712 1024 RL1024PAG-712 RL1024PAQ-712 2048 RL2048PAG-712 RL2048PAQ-712 www.perkinelmer.com/opto DSP-101 01H - 7/2002W Page 7 Linear Photodiode Array Imagers Table 9. Sales Offices North America United States PerkinElmer Optoelectronics 2175 Mission College Blvd. Santa Clara, CA 95054 Toll Free: 800-775-OPTO (6786) Phone: +1-408-565-0830 Fax: +1-408-565-0703 Europe Germany PerkinElmer Optoelectronics GmbH Wenzel-Jaksch-Str. 31 D-65199 Wiesbaden, Germany Phone: +49-611-492-570 Fax: +49-611-492-165 Asia Japan PerkinElmer Optoelectronics NEopt. 18F, Parale Mitsui Building 8 Higashida-Cho, Kawasaki-Ku Kawasaki-Shi, Kanagawa-Ken 210-0005 Japan Phone: +81-44-200-9170 Fax: +81-44-200-9160 www.neopt.co.jp 47 Ayer Rajah Crescent #06-12 Singapore 139947 Phone: +65-770-4925 Fax: +65-777-1008 For more information e-mail us at opto@perkinelmer.com or visit our web site at www.perkinelmer.com/opto. All values are nominal; specifications subject to change without notice. Singapore © 2000 PerkinElmer Inc. All rights reserved. PerkinElmer, the PerkinElmer logo and the stylized “P” are trademarks of PerkinElmer, Inc. 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