74ABT5074D

INTEGRATED CIRCUITS 74ABT5074 Synchronizing dual D-type flip-flop with metastable immune characteristics Product data Supersedes data of 1994 Dec 15 2002 Dec 17 Philips Semiconductors Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 FEATURES • Metastable immune characteristics • Pin compatible with 74F74 and 74F5074 • Typical fMAX = 200 MHz • Output skew guaranteed less than 2.0 ns • High source current (IOH = 15 mA) ideal for clock driver applications Set (SDn) and reset (RDn) are asynchronous active-LOW inputs and operate independently of the clock (CPn) input. Data must be stable just one set-up time prior to the LOW-to-HIGH transition of the clock for guaranteed propagation delays. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output. The 74ABT5074 is designed so that the outputs can never display a metastable state due to set-up and hold time violations. If set-up time and hold time are violated the propagation delays may be extended beyond the specifications, but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74ABT5074 are: τ ≅ 94 ps and To ≅ 1.3 × 107 sec • Output capability: +20 mA / –15 mA • Latch-up protection exceeds 50 0mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model DESCRIPTION The 74ABT5074 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set and reset inputs; also true and complementary outputs. where τ represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state. QUICK REFERENCE DATA SYMBOL tPLH tPHL CIN ICC PARAMETER Propagation delay CPn to Qn or Qn Input capacitance Total supply current CONDITIONS Tamb = 25 °C; GND = 0 V CL = 50 pF; VCC = 5 V VI = 0 V or VCC Outputs disabled; VCC =5.5 V TYPICAL 2.8 2.4 3 2 UNIT ns pF µA ORDERING INFORMATION PACKAGES 14-Pin plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C PART NUMBER 74ABT5074D 74ABT5074DB 74ABT5074PW DWG NUMBER SOT108-1 SOT337-1 SOT402-1 PIN CONFIGURATION RD0 D0 CP0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RD1 D1 CP1 SD1 Q1 Q1 PIN DESCRIPTION PIN 2, 12 3, 11 4, 10 1, 13 5, 9 6, 8 7 14 SYMBOL D0, D1 CP0, CP1 SD0, SD1 RD0, RD1 Q0, Q1 Q0, Q1 GND VCC NAME AND FUNCTION Data inputs Clock inputs (active rising edge) Set inputs (active-LOW) Reset inputs (active-LOW) Data outputs (active-LOW), non-inverting Data outputs (active-LOW), inverting Ground (0 V) Positive supply voltage SA00001 2002 Dec 17 2 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 LOGIC SYMBOL 2 12 IEC/IEEE SYMBOL 4 D0 D1 3 4 1 11 10 13 CP0 SD0 1 RD0 CP1 10 SD1 RD1 Q0 Q0 Q1 Q1 11 C2 12 2D 13 R 5 6 9 8 8 S 9 R S 3 C1 2 1D 6 5 VCC = Pin 14 GND = Pin 7 SA00002 SA00003 LOGIC DIAGRAM FUNCTION TABLE INPUTS OUTPUTS D X X X h l X Q H L L H L NC Q L H H L H NC OPERATING MODE Asynchronous set Asynchronous reset Undetermined* Load “1” Load “0” Hold SD L RD H L L H H H CP X X X ↑ ↑ ↑ SD 4, 10 RD 1, 13 5, 9 Q H L CP 3, 11 6, 8 H Q H 2, 12 H D VCC = Pin 14 GND = Pin 7 SF00048 NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to LOW-to-HIGH clock transition L = LOW voltage level l = LOW voltage level one set-up time prior to LOW-to-HIGH clock transition NC= No change from the previous set-up X = Don’t care ↑ = LOW-to-HIGH clock transition ↑ = Not LOW-to-HIGH clock transition * = This set-up is unstable and will change when either set or reset return to the HIGH level 2002 Dec 17 3 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 METASTABLE IMMUNE CHARACTERISTICS Philips Semiconductors uses the term ‘metastable immune’ to describe characteristics of some of the products in its family. By running two independent signal generators (see Figure 1) at nearly the same frequency (in this case 10 MHz clock and 10.02 MHz data) the device-under-test can often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build a waveform. An experiment was run by continuously operating the devices in the region where metastability will occur. After determining the T0 and τ of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74ABT5074 for synchronizing asynchronous data that is arriving at 10 MHz (as measured by a frequency counter), has a clock frequency of 50 MHz, and has decided that he would like to sample the output of the 74ABT5074 7 nanoseconds after the clock edge. He simply plugs his number into the following equation: MTBF = e(t’/τ)/ TO*fC*fI In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t’ is the time after the clock pulse that the output is sampled (t’ > h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying fI by fC gives an answer of 1015 Hz2. From Figure 2 it is clear that the MTBF is greater than 1010 seconds. Using the above formula the actual MTBF is 1.69 × 1010 seconds or about 535 years. SIGNAL GENERATOR D Q TRIGGER DIGITAL SCOPE SIGNAL GENERATOR CP Q INPUT SA00004 Figure 1. Test Setup E13 E6 E8 E10 E12 E14 E15 = fc*fi E12 10,000 YEARS E11 E10 MTBF (SECONDS) 100 YEARS E9 E8 ONE YEAR E7 E6 ONE WEEK E5 4 5 6 t’ (NANOSECONDS) 7 8 VCC = 5 V, Tamb = 25 °C, τ =94 ps, To = 1.3x107 sec MTBF = e(t’/τ)/TO*fC*fI SA00005 Figure 2. Mean Time Between Failures (MTBF) versus t’ 2002 Dec 17 4 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCCS AND TEMPERATURES VCC 5.5 V 5.0 V 4.5 V Tamb = –40 °C τ 84 ps 84 ps 89 ps T0 1.0 × 106 sec 2.7 × 108 sec τ 93 ps 94 ps 103 ps Tamb = 25 °C T0 3.8 × 106 sec 1.3 × 107 sec τ 89 ps 106 ps 115 ps 74ABT5074 Tamb = 85 °C T0 1.5 × 109 sec 2.2 × 106 sec 4.4 × 106 sec 1.0 × 109 sec 2.1 × 107 sec ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK VI IOK VOUT IOUT Tstg DC supply voltage DC input diode current DC input voltage3 VO < 0 V Output in Off or HIGH state Output in LOW state VI < 0 V PARAMETER CONDITIONS RATING –0.5 to +7.0 –18 –1.2 to +7.0 –50 –0.5 to +5.5 40 –65 to 150 UNIT V mA V mA V mA °C DC output diode current DC output voltage3 DC output current Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VI VIH VIL IOH IOL ∆t/∆v Tamb DC supply voltage Input voltage HIGH-level input voltage LOW-level Input voltage HIGH-level output current LOW-level output current Input transition rise or fall rate Operating free-air temperature range PARAMETER MIN 4.5 0 2.0 – – – 0 –40 MAX 5.5 VCC – 0.8 –15 20 10 +85 V V V V mA mA ns/V °C UNIT 2002 Dec 17 5 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH VOL II IOFF IO ICC ∆ICC Input clamp voltage HIGH-level output voltage LOW-level output voltage Input leakage current Power-off leakage current Output current1 VCC = 4.5 V; IIK = –18 mA VCC = 4.5 V; IOH = –15 mA; VI = VIL or VIH VCC = 4.5 V; IOL = 20 mA; VI = VIL or VIH VCC = 5.5 V; VI = GND or 5.5 V VCC = 0.0 V; VO or VI v 4.5 V VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; VI = GND or VCC VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND – 2.5 – – – –50 – – Tamb = +25 °C TYP –0.9 2.9 0.35 ±0.01 ±5.0 –75 2 0.25 MAX –1.2 – 0.5 ±1.0 ±100 –180 50 500 Tamb = –40 °C to +85 °C MIN – 2.5 – – – –50 – – MAX –1.2 – 0.5 ±1.0 ±100 –180 50 500 V V V µA µA mA µA µA UNIT Quiescent supply current Additional supply current per input pin2 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4 V. AC CHARACTERISTICS GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 Ω LIMITS SYMBOL PARAMETER WAVEFORM MIN fmax tPLH tPHL tPLH tPHL tsk(o) Maximum clock frequency Propagation delay CPn to Qn or Qn Propagation delay SDn, RDn to Qn or Qn Output skew1, 2 CPn to Qn to Qn 1 1 2 4 180 1.0 1.0 1.0 1.0 – Tamb = +25 °C VCC = +5.0 V TYP 250 2.8 2.4 3.5 3.1 – MAX – 3.9 3.5 4.6 4.2 1.5 Tamb = –40 °C to +85 °C VCC = +5.0 V ±0.5 V MIN 150 1.0 1.0 1.0 1.0 – MAX – 4.5 3.7 5.5 4.7 2.0 ns ns ns ns UNIT NOTES: 1. | tPN actual - tPM actual | for any output compared to any other output where N and M are either LH or HL. 2. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). AC SET-UP REQUIREMENTS GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25 °C VCC = +5.0 V MIN ts(H) ts(L) th(H) th(L) tw (H) tw (L) tw (L) trec Set-up time, HIGH or LOW Dn to CPn Hold time, HIGH or LOW Dn to CPn CPn pulse width, HIGH or LOW SDn or RDn pulse width, LOW Recovery time SDn or RDn to CPn 1 1 1 2 3 2.5 2.5 0 0 1.5 2.4 2.0 2.4 TYP 1.5 1.5 –1.4 –1.4 0.6 1.8 1.3 1.3 Tamb = –40 °C to +85 °C VCC = +5.0 V ±0.5 V MIN 2.5 2.5 0 0 1.5 2.9 2.2 2.8 ns ns ns ns ns UNIT 2002 Dec 17 6 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 AC WAVEFORMS VM = 1.5 V, VIN = GND to 3.0 V The shaded areas indicate when the input is permitted to change for the predictable output performance. Dn CPn Qn Qn Waveform 1. Propagation Delay for Data to Output, Data Set-up Time and Hold Time, and Clock Width SDn or RDn Waveform 3. Recovery Time for Set or Reset to Output 2002 Dec 17 ÉÉÉÉÉÉÉÉÉ ÉÉÉ É ÉÉÉÉÉÉÉÉÉ ÉÉÉ É VM VM VM VM ts(L) th(L) fMAX ts(H) th(H) tw(H) VM VM tw(L) VM tPLH VM tPHL VM tPHL VM tPLH VM SDn VM tw(L) VM tw(L) RDn tPLH Qn VM VM tPHL VM VM tPLH Qn tPHL VM VM SA00008 SA00009 Waveform 2. Propagation Delay for Set and Reset to Output, Set and Reset Pulse Width VM Qn, Qn VM tREC tSK(0) CPn VM Qn, Qn VM SA00010 SA00011 Waveform 4. Output Skew 7 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 TEST CIRCUIT AND WAVEFORM VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% 0V tTLH (tr ) 90% AMP (V) tTLH (tr ) 90% POSITIVE PULSE VM 10% tw 90% VM tTHL (tf ) AMP (V) Test Circuit for 3-State Outputs DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS FAMILY amplitude 74ABT 3.0V rep. rate 1MHz tw 500ns tR 2.5ns tF 2.5ns SA00058 2002 Dec 17 8 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 2002 Dec 17 9 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 2002 Dec 17 10 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 2002 Dec 17 11 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 REVISION HISTORY Rev _2 Date 20021217 Description Product data (9397 750 10847); ECN 853-1775 29293 of 12 December 2002. Supersedes data of 15 December 1994. Modifications: • Ordering information table: remove 74ABT5074N package offering. _1 19941215 Product specification. ECN 853-1775 14470 of 15 December 1994. 2002 Dec 17 12 Philips Semiconductors Product data Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 Data sheet status Level I Data sheet status [1] Objective data Product status [2] [3] Development Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 12-02 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 9397 750 10847 Philips Semiconductors 2002 Dec 17 13